JP2003046253A - Multilayer circuit board - Google Patents
Multilayer circuit boardInfo
- Publication number
- JP2003046253A JP2003046253A JP2001230882A JP2001230882A JP2003046253A JP 2003046253 A JP2003046253 A JP 2003046253A JP 2001230882 A JP2001230882 A JP 2001230882A JP 2001230882 A JP2001230882 A JP 2001230882A JP 2003046253 A JP2003046253 A JP 2003046253A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating
- circuit board
- cavity
- multilayer circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、多層回路基板に関
するものであり、特に抗折強度を向上させた多層回路基
板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board, and more particularly to a multilayer circuit board having improved bending strength.
【０００２】[0002]
【従来の技術】従来より多層回路基板は、複数の絶縁層
からなる積層基板の各層間に内部配線層を、各絶縁層の
厚み方向にビアホール導体を夫々形成し、表面（一方の
主面）に、ＩＣチップや各種チップ状電子部品などの回
路構成部品を搭載するための表面配線層やキャビティが
形成されており、裏面（他方の主面）にグランド電極や
外部出力電極などが形成されていた。2. Description of the Related Art Conventionally, in a multilayer circuit board, an internal wiring layer is formed between layers of a laminated board composed of a plurality of insulating layers, and via hole conductors are formed in the thickness direction of each insulating layer, and the surface (one main surface) Has a surface wiring layer and a cavity for mounting circuit components such as an IC chip and various chip-shaped electronic components, and has a ground electrode and an external output electrode formed on the back surface (the other main surface). It was
【０００３】また、積層基板の各絶縁層には、内部配線
層間を接続したり、また、内部配線層と表面配線層とを
接続したりするためのビアホール導体が形成されてい
た。尚、ビアホール導体については、上述の所定回路網
を形成する以外に、例えば、多層回路基板にＩＣチップ
が収容するキャビティを設け、このキャビティ内のＩＣ
チップで発生する熱が多層回路基板外に放出するビアホ
ール導体を形成しても構わない。Further, via holes conductors for connecting the internal wiring layers and for connecting the internal wiring layers and the surface wiring layers have been formed in each insulating layer of the laminated substrate. Regarding the via-hole conductor, in addition to forming the above-mentioned predetermined circuit network, for example, a cavity for accommodating an IC chip is provided in a multilayer circuit board, and the IC in this cavity is provided.
A via-hole conductor may be formed in which heat generated in the chip is released to the outside of the multilayer circuit board.
【０００４】また、多層回路基板の表面には、上述の表
面配線層やこの表面配線層の一部を露出させて、オーバ
ーコートガラス層が形成されている。そして、このオー
バーコートガラス層から露出した部位に、各種電子部品
などを搭載していた。On the surface of the multilayer circuit board, an overcoat glass layer is formed by exposing the above-mentioned surface wiring layer and a part of this surface wiring layer. And various electronic parts etc. were mounted in the site | part exposed from this overcoat glass layer.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、積層基
板をマザーボードに実装した状態で、マザーボードから
積層基板に大きな曲げ荷重が作用した場合、そのたわみ
応力が集中する回路基板の中央部付近に位置し、しか
も、多層回路基板中、構造的に最もキャビティ部分に過
度の荷重がかかり、その結果、キャビティの開口稜線部
分にクラックなどが発生してしまうという問題点があっ
た。特に、近年、積層基板の低背化の要求に伴い、基体
厚みを薄くした場合、これらの問題点は顕著になってい
た。However, when a large bending load is applied from the mother board to the laminated board in a state where the laminated board is mounted on the motherboard, the flexural stress is located near the central portion of the circuit board, Moreover, in the multilayer circuit board, an excessive load is structurally applied to the cavity portion, and as a result, a crack or the like occurs at the opening ridgeline portion of the cavity. In particular, in recent years, these problems have become noticeable when the thickness of the base body is reduced in accordance with the demand for a reduced height of the laminated substrate.
【０００６】本発明は、上述の問題点に鑑みて案出され
たものであり、その目的には、大きな曲げ荷重が作用し
た場合において、キャビティの開口の周囲で割れやクラ
ックが発生することのない多層回路基板を提供するもの
である。The present invention has been devised in view of the above-mentioned problems, and an object thereof is to prevent cracks or cracks around the opening of a cavity when a large bending load is applied. No multi-layer circuit board is provided.
【０００７】[0007]
【課題を解決するための手段】本発明の多層回路基板
は、絶縁層を積層してなる積層基板の各絶縁層間に内部
配線層を、表面に表面配線層、及び回路構成部品を収納
したキャビティを形成してなる多層回路基板において、
前記積層基板のキャビティの開口周囲に、該積層基板の
表面から突出する絶縁突出層を周設したことを特徴とす
る多層回路基板である。A multi-layer circuit board of the present invention is a cavity in which an internal wiring layer is housed between each insulating layer of a laminated board formed by laminating insulating layers, a surface wiring layer is housed on the surface, and circuit components. In a multilayer circuit board formed by
The multilayer circuit board is characterized in that an insulating projecting layer projecting from a surface of the laminated board is provided around an opening of a cavity of the laminated board.
【０００８】また、前記絶縁突出層は、前記絶縁層と同
一の絶縁材料から構成されていることを特徴とする。Further, the insulating protruding layer is made of the same insulating material as that of the insulating layer.
【０００９】また、前記表面配線層は、オーバーコート
ガラス層で被覆されているとともに、前記絶縁突出層
は、該オーバーコートガラス層と同一の材料からなるこ
とを特徴とする。Further, the surface wiring layer is covered with an overcoat glass layer, and the insulating protrusion layer is made of the same material as the overcoat glass layer.
【００１０】また、前記絶縁層は、１１００℃以下で焼
成可能なガラスと無機物フィラとからなるガラス−セラ
ミック材料で構成されていることを特徴とする。Further, the insulating layer is characterized in that it is made of a glass-ceramic material composed of glass and an inorganic filler which can be fired at 1100 ° C. or lower.
【００１１】また、キャビティの周辺に沿って突出する
絶縁突出層は、基板主面から１〜３０μｍの高さで突出
している。The insulating protrusion layer protruding along the periphery of the cavity protrudes from the main surface of the substrate at a height of 1 to 30 μm.
【作用】本発明の多層回路基板によれば、積層基板の主
面に配置したキャビティ開口の周囲に沿って突出する絶
縁突出層を形成している。これにより、キャビティ開口
の周囲が局部的に基板の厚み厚くなっている。このた
め、基板の抗折強度が向上し、曲げ荷重に対して、キャ
ビティの開口周囲にクラックが発生しない多層回路基板
となる。尚、キャビティ開口の周辺に沿って突出する絶
縁突出層は、基板主面から１〜３０μｍの高さで突出し
ている。この突出量が１μｍ未満では、抗折強度が充分
に得られない。また、３０μｍを越える場合、キャビテ
ィ開口の周囲に回路構成部品を表面実装にて搭載すべ
く、クリーム半田を印刷塗布しようとしても、絶縁突出
層６の高さが邪魔になり、安定したクリーム半田の塗布
が困難となる。According to the multilayer circuit board of the present invention, the insulating protruding layer is formed so as to protrude along the periphery of the cavity opening arranged on the main surface of the laminated board. This locally thickens the substrate around the cavity opening. Therefore, the bending strength of the board is improved, and a multilayer circuit board in which cracks do not occur around the opening of the cavity against bending load. The insulating protrusion layer protruding along the periphery of the cavity opening protrudes from the main surface of the substrate at a height of 1 to 30 μm. If this protrusion amount is less than 1 μm, sufficient bending strength cannot be obtained. Further, when the thickness exceeds 30 μm, the height of the insulating protruding layer 6 becomes an obstacle even when the cream solder is applied by printing so as to mount the circuit components around the cavity opening by surface mounting, and the stable cream solder is not formed. Difficult to apply.
【００１２】また、絶縁突出層は、絶縁層と同一の絶縁
材料、オーバーコートガラス層と同一の材料、あるいは
１１００℃以下で焼成可能なガラスと無機物フィラとか
らなるガラス−セラミック材料で構成することにより、
絶縁層やオーバーコートガラス層と同時に形成すること
ができ、実質的な工程の付加とはならず、簡単且つ安価
に形成することができる。The insulating protruding layer is made of the same insulating material as the insulating layer, the same material as the overcoat glass layer, or a glass-ceramic material composed of glass that can be fired at 1100 ° C. or less and an inorganic filler. Due to
It can be formed at the same time as the insulating layer and the overcoat glass layer, does not require any additional steps, and can be formed easily and inexpensively.
【００１３】[0013]
【発明の実施の形態】以下、本発明の多層回路基板を図
面に基づいて説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The multilayer circuit board of the present invention will be described below with reference to the drawings.
【００１４】図１は、本発明に係る多層回路基板の外観
斜視図である。図２は、図１の多層回路基板の平面図及
び正面図である。図３は、図１の多層回路基板の断面図
である。FIG. 1 is an external perspective view of a multilayer circuit board according to the present invention. FIG. 2 is a plan view and a front view of the multilayer circuit board of FIG. FIG. 3 is a cross-sectional view of the multilayer circuit board of FIG.
【００１５】図において、１０は多層回路基板、１は積
層基板、４は内部配線層、３はビアホール導体、２は表
面配線層、５、１５は回路構成部品、６は基板周辺部の
絶縁突出層、７は分離線、８はオーバーコートガラス
層、９はキャビティ、１６はキャビティ周辺部の絶縁突
出層である。尚、回路構成部品１５はキャビティ９の内
部に収容される回路構成部品であり、例えばボンディン
グワイヤなどにより接合されるＩＣチップ、弾性表面波
装置などである。In the figure, 10 is a multilayer circuit board, 1 is a laminated board, 4 is an internal wiring layer, 3 is a via hole conductor, 2 is a surface wiring layer, 5 and 15 are circuit components, and 6 is an insulating protrusion in the peripheral portion of the board. A layer, 7 is a separation line, 8 is an overcoat glass layer, 9 is a cavity, and 16 is an insulating protruding layer around the cavity. The circuit component 15 is a circuit component housed inside the cavity 9, and is, for example, an IC chip bonded by a bonding wire or the like, a surface acoustic wave device, or the like.
【００１６】以下、多層回路基板１０について詳細に説
明する。The multilayer circuit board 10 will be described in detail below.
【００１７】積層基板１を構成する絶縁層１ａ〜１ｄ
は、１層あたり例えば５０〜３００μｍ程度の厚みを有
し、その材質としては、セラミック材料、結晶化ガラス
成分などからなり、また、低温焼成化が可能な酸化物な
どが用いられる。具体的には、無機物フィラーであるセ
ラミック材料としては、例えばＡｌ2Ｏ3、ＢａＯ−Ｔｉ
Ｏ2系、ＣａＯ−ＴｉＯ2系、ＭｇＯ−ＴｉＯ2系など
が、また低温焼成化が可能な酸化物としては、例えばＢ
ｉＶＯ4、ＣｕＯ、Ｌｉ2Ｏ、Ｂ2Ｏ3などが選ばれる。Insulating layers 1a to 1d constituting the laminated substrate 1
Has a thickness of, for example, about 50 to 300 μm per layer, and as its material, a ceramic material, a crystallized glass component, or the like, and an oxide or the like that can be fired at low temperature is used. Specifically, examples of the ceramic material that is an inorganic filler include Al 2 O 3 and BaO—Ti.
O 2 type, CaO—TiO 2 type, MgO—TiO 2 type, and the like, and oxides that can be fired at low temperature include, for example, B
iVO 4 , CuO, Li 2 O, B 2 O 3 and the like are selected.
【００１８】絶縁層１ａ〜１ｄの各層の厚み方向に貫く
ビアホール導体３が形成されている。また、絶縁層１ａ
〜１ｄの層間には、容量を形成する容量電極、インダク
タンス成分を形成する導体、ストリップ線路を形成する
導体など所定回路網を形成する内部配線層４が形成され
ている。Via-hole conductors 3 are formed so as to penetrate the insulating layers 1a to 1d in the thickness direction. Also, the insulating layer 1a
Between the layers 1d to 1d, an internal wiring layer 4 that forms a predetermined circuit network such as a capacitance electrode that forms a capacitance, a conductor that forms an inductance component, and a conductor that forms a strip line is formed.
【００１９】また、絶縁層１ａの表面には、回路構成部
品５を搭載するための電極パッドや外部回路と接続する
接続端子を含む表面配線層２が形成されている。また、
表面配線層２の一部には、機械的な保護、耐湿性保護を
かねたオーバーコートガラス層８が被着形成されてい
る。裏面側主面においては、外部のマザーボードと接続
するための外部端子電極を含む。Further, on the surface of the insulating layer 1a, a surface wiring layer 2 including electrode pads for mounting the circuit component 5 and connection terminals for connecting to an external circuit is formed. Also,
An overcoat glass layer 8 that also serves as mechanical protection and moisture resistance protection is deposited and formed on a part of the surface wiring layer 2. The main surface on the back surface side includes external terminal electrodes for connecting to an external motherboard.
【００２０】そして、表面配線層２、ビアホール導体
３、内部配線層４は、所定回路網を構成すべく、互いに
接続されている。また、これらの導体は、Ａｇ系（Ａｇ
単体又はＡｇ−Ｐｄ、Ａｇ−ＰｔなどのＡｇ合金）や、
Ｃｕ系（Ｃｕ単体又はＣｕ合金）を主成分とする導体膜
（導体）が用いられる。The surface wiring layer 2, the via-hole conductor 3 and the internal wiring layer 4 are connected to each other to form a predetermined circuit network. In addition, these conductors are Ag-based (Ag
Simple substance or Ag alloy such as Ag-Pd or Ag-Pt),
A conductor film (conductor) containing a Cu-based (Cu alone or Cu alloy) as a main component is used.
【００２１】回路構成部品５は、積層セラミックコンデ
ンサ、チップ抵抗器、ＳＡＷ素子、インダクタンス素
子、半導体素子など各種電子部品が例示される。The circuit component 5 is exemplified by various electronic components such as a monolithic ceramic capacitor, a chip resistor, a SAW element, an inductance element and a semiconductor element.
【００２２】多層回路基板１０の表面には、キャビティ
９が形成されている。また、キャビティ９内部にはＩＣ
チップなどの回路構成部品１５が搭載され、例えば、ワ
イヤボンディング接合により表面配線層２に接続されて
いる。A cavity 9 is formed on the surface of the multilayer circuit board 10. In addition, an IC is provided inside the cavity 9.
A circuit component 15 such as a chip is mounted and connected to the surface wiring layer 2 by wire bonding, for example.
【００２３】本発明では多層回路基板１０の主面のキャ
ビティ９の開口周囲の稜線部分、即ち、キャビティ９の
内壁面に沿って突出した絶縁突出層１６が周設されてい
る。尚、図においては、絶縁突出層１６は、キャビティ
９の開口周辺の全周において、連続して形成されている
が、途中で分断して断続的に形成してもよい。In the present invention, the insulating projecting layer 16 projecting along the ridge line around the opening of the cavity 9 on the main surface of the multilayer circuit board 10, that is, along the inner wall surface of the cavity 9, is provided. In addition, in the figure, the insulating protruding layer 16 is formed continuously over the entire circumference of the periphery of the opening of the cavity 9, but it may be divided intermittently and formed intermittently.
【００２４】この絶縁突出層１６の材料は、絶縁層１ａ
〜１ｄと実質的に同一材料（固形成分が同一）により、
または上述のオーバーコートガラス層８と同一の材料
（固形成分が同一）により形成されている。The material of the insulating protruding layer 16 is the insulating layer 1a.
~ Substantially the same material as 1d (solid components are the same),
Alternatively, it is formed of the same material (having the same solid component) as the above-mentioned overcoat glass layer 8.
【００２５】ここで、キャビティ９の開口周囲の絶縁突
出層１６は、その高さｔ２が１〜３０μｍの範囲に設定
されている。絶縁突出層６の高さt２が１μｍ未満で
は、積層基板１のキャビティ９の開口の稜線部分での強
度不足により、マザーボードに実装し、たわみ荷重をか
けたとき、キャビティ９の開口周囲の絶縁突出層１６部
分でクラックが発生してしまう。Here, the height t2 of the insulating protrusion layer 16 around the opening of the cavity 9 is set in the range of 1 to 30 μm. If the height t2 of the insulating protrusion layer 6 is less than 1 μm, the insulating protrusion around the opening of the cavity 9 is mounted on the motherboard due to insufficient strength at the ridge portion of the opening of the cavity 9 of the laminated substrate 1 and when a flexible load is applied. A crack is generated in the layer 16 portion.
【００２６】また、高さt２が３０μｍを越えると、絶
縁突出層６が高くなり過ぎ、キャビティ９の開口周囲に
回路構成部品５を半田接合して実装するにあたり、その
表面配線層２上にクリーム半田を印刷する際には、印刷
スクリーンを積層基板１の表面に密着させて印刷できな
くなり、クリーム半田を所定表面配線層２に形成するこ
とができない。When the height t2 exceeds 30 μm, the insulating protruding layer 6 becomes too high, and when mounting the circuit component 5 by soldering around the opening of the cavity 9, the cream is formed on the surface wiring layer 2. When printing the solder, the printing screen cannot be printed by bringing the printing screen into close contact with the surface of the laminated substrate 1, and the cream solder cannot be formed on the predetermined surface wiring layer 2.
【００２７】キャビティ９の開口周囲の絶縁突出層１６
の一辺の幅ｗ2は、この絶縁突出層１６の一辺と並行な
積層基板１の辺の長さに対して、１％〜２０％となって
いる。例えば、多層回路基板１０の辺の長さが２０ｍｍ
の場合、その辺に沿って形成された絶縁突出層１６の幅
ｗ2は、０．２〜４ｍｍの幅である。Insulating protruding layer 16 around the opening of cavity 9
The width w 2 of one side is 1% to 20% with respect to the length of the side of the laminated substrate 1 which is parallel to one side of the insulating protruding layer 16. For example, the side length of the multilayer circuit board 10 is 20 mm
In this case, the width w 2 of the insulating protruding layer 16 formed along the side is 0.2 to 4 mm.
【００２８】ここで、絶縁突出層１６の幅ｗ2が小さく
なると、キャビティ９の周辺に未焼成状態の絶縁突出層
を被着形成する際に、積層ずれ・印刷ずれが生じてしま
う。このため、絶縁突出層１６の幅ｗ2の下限は、基板
の辺の長さに対して１％以上、好ましくは５％以上であ
ることが望ましい。一方、絶縁突出層１６の幅ｗ2が大
きくなると、この絶縁突出層１６を跨ぐように、キャビ
ティ９内の回路構成部品１５と表面配線層２をボンディ
ングワイヤ配線により電気的に接続することが困難にな
るとともに、他の表面配線層２などを形成する面積が小
さくなるため、絶縁突出層１６の幅ｗ2の上限は、基板
の辺の長さに対して２０％以下、好ましくは１０％以下
であることが望ましい。Here, if the width w 2 of the insulating protruding layer 16 becomes small, a stacking deviation and a printing deviation will occur when an unsintered insulating protruding layer is formed around the cavity 9. Therefore, the lower limit of the width w 2 of the insulating protruding layer 16 is preferably 1% or more, and more preferably 5% or more, with respect to the length of the side of the substrate. On the other hand, when the width w 2 of the insulating protruding layer 16 is increased, it is difficult to electrically connect the circuit component 15 in the cavity 9 and the surface wiring layer 2 by bonding wire wiring so as to straddle the insulating protruding layer 16. And the area for forming the other surface wiring layer 2 and the like becomes smaller, the upper limit of the width w 2 of the insulating protruding layer 16 is 20% or less, preferably 10% or less with respect to the side length of the substrate. Is desirable.
【００２９】また、多層回路基板１０の主面の外周稜線
部分、即ち、多層回路基板１０の端面にそって突出した
絶縁突出層６が周設されている。絶縁突出層６の材料
は、絶縁突出層１６と同じであることが望ましい。ま
た、絶縁突出層６は、その厚みｔ 1が１〜３００μｍ、
好ましくは５〜１００μｍに設定されている。Further, the outer peripheral ridge line of the main surface of the multilayer circuit board 10
Part, that is, projected along the end face of the multilayer circuit board 10.
The insulating protruding layer 6 is provided around the periphery. Material of the insulating protruding layer 6
Is preferably the same as the insulating protruding layer 16. Well
Moreover, the insulating protrusion layer 6 has a thickness t. 1Is 1 to 300 μm,
It is preferably set to 5 to 100 μm.
【００３０】絶縁突出層６の高さtが１μｍ未満では、
積層基板１の稜線部分での強度不足により、落下試験
時、この絶縁突出層６にクラックや欠けが発生してしま
う。When the height t of the insulating protruding layer 6 is less than 1 μm,
Due to insufficient strength at the ridge line portion of the laminated substrate 1, cracks and chips are generated in the insulating protruding layer 6 during the drop test.
【００３１】また、高さtが３００μｍを越えると、絶
縁突出層６が高くなり過ぎ、後述の大型多層回路基板１
１から各回路領域１２を分離（分割や切断）接合した際
に、その応力が絶縁突出層６に集中してしまい、絶縁突
出層６にクラックが発生してしまう。また、積層基板1
の表面に回路構成部品５を搭載する際に、マウンタの先
端が衝突するなどの回路実装部品の搭載に支障が発生す
る。また、絶縁突出層６の幅ｗ1は、この絶縁突出層６
が沿う部分の基板の辺の長さに対して、１％〜２０％、
好ましくは５〜１０％であることが望ましい。If the height t exceeds 300 μm, the insulating protruding layer 6 becomes too high, and the large-sized multilayer circuit board 1 described later will be described.
When the respective circuit regions 12 are separated (divided or cut) from 1 and joined, the stress concentrates on the insulating protruding layer 6 and cracks occur in the insulating protruding layer 6. Also, the laminated substrate 1
When the circuit component 5 is mounted on the surface of the device, the mounting of the circuit mounted component may be hindered, such as the tip of the mounter colliding. Further, the width w 1 of the insulating protruding layer 6 is
1% to 20% of the length of the side of the substrate along the
It is preferably 5 to 10%.
【００３２】このような多層回路基板１０は、詳細に
は、以下のような製造方法により形成される。More specifically, the multilayer circuit board 10 as described above is formed by the following manufacturing method.
【００３３】積層基板１となる絶縁材料、例えば、ガラ
ス−セラミック材料から成るグリーンシートを形成す
る。なお、このグリーンシートは、積層基板１となる複
数の基板領域１２からなる大型グリーンシートである。A green sheet made of an insulating material to be the laminated substrate 1, for example, a glass-ceramic material is formed. The green sheet is a large green sheet including a plurality of substrate regions 12 that will be the laminated substrate 1.
【００３４】次に、グリーンシート上の各基板領域１２
毎に、ビアホール導体３となる所定径の貫通孔をパンチ
ングによって形成する。Next, each substrate area 12 on the green sheet
Each time, a through hole having a predetermined diameter to be the via-hole conductor 3 is formed by punching.
【００３５】次に、グリーンシート上の各基板領域１２
毎に、スクリーン印刷により、上述の貫通穴にＡｇ系導
電性ペーストを充填するとともに、内部配線層４となる
導体膜などを形成する。また、さらに、最外層に位置す
るグリーンシート上に、表面配線層２となる導体膜、各
種電極パッドとなる導体膜を形成する。Next, each substrate region 12 on the green sheet
Each time, by screen printing, the above-mentioned through holes are filled with Ag-based conductive paste, and at the same time, a conductor film or the like to be the internal wiring layer 4 is formed. Further, a conductor film to be the surface wiring layer 2 and conductor films to be various electrode pads are formed on the outermost green sheet.
【００３６】次に、導体膜を形成した各層のグリーンシ
ートの所定の位置に、回路構成部品１５を収納するキャ
ビティ９となる貫通孔をパンチングにて形成する。Next, a through hole to be the cavity 9 for accommodating the circuit component 15 is punched at a predetermined position of the green sheet of each layer on which the conductor film is formed.
【００３７】次に、各種導体膜を形成した上述のグリー
ンシートを、積層体１０の積層順に応じて載置する。そ
して、一次プレスを行う。その後、必要に応じて、積層
した未焼成状態の大型仮想回路基板１１の表面に、オー
バーコートのガラス層８となる塗膜をガラス層となる塗
膜を形成する。Next, the above-mentioned green sheets on which various conductor films are formed are placed according to the stacking order of the stack 10. Then, the primary press is performed. Thereafter, if necessary, a coating film serving as the overcoat glass layer 8 and a coating film serving as the glass layer are formed on the surface of the stacked large-sized virtual circuit board 11 in an unbaked state.
【００３８】その後、各回路領域１２のキャビティ９の
開口周囲に絶縁突出層１６となるグリーンシートを配置
し、また、各回路領域を仕切る境界部分に跨がるよう
に、絶縁突出層６となるグリーンシートを載置し、ま
た、二次プレスを行う。この二次プレスは、絶縁突出層
６、１６を構成するグリーンシートを主に圧着するため
である。After that, a green sheet to be the insulating protruding layer 16 is arranged around the opening of the cavity 9 in each circuit region 12, and the insulating protruding layer 6 is formed so as to straddle the boundary part partitioning each circuit region. Place the green sheet and perform secondary pressing. This secondary press is mainly for pressure-bonding the green sheets forming the insulating protruding layers 6 and 16.
【００３９】この絶縁突出層６、１６となるグリーンシ
ートは、全体を平面視した時、各回路領域の中央部分を
露出する窓部が形成された、格子状となっている。そし
て、この格子状の桟に相当する部位が絶縁突出層６、１
６となる。The green sheets to be the insulating protruding layers 6 and 16 have a lattice shape in which a window portion exposing the central portion of each circuit region is formed when the whole is viewed in a plan view. Then, the portions corresponding to the lattice-shaped crosspieces are the insulating protrusion layers 6 and 1.
It becomes 6.
【００４０】次に、大型多層回路基板１１の分離を分割
処理により行う場合には、各回路基板領域１２を仕切る
ように分割溝を形成する。この分割溝は、絶縁突出層６
となる部位を隣接し合う回路領域１２に分断するように
形成する。Next, when the large-sized multi-layer circuit board 11 is separated by a dividing process, a dividing groove is formed so as to partition each circuit board region 12. The dividing groove is formed by the insulating protruding layer 6
The part to be formed is divided into adjacent circuit regions 12.
【００４１】次に、未焼成の大型多層回路基板１１を、
酸化性雰囲気または大気雰囲気で焼成処理する。焼成処
理は脱バインダー過程と焼結過程からなる。この焼成温
度は、ピーク温度８５０〜１０５０℃に達するまでに行
われる。これにより、内部に内部配線層４、ビアホール
導体３が形成され、且つ表面に表面配線層２が形成さ
れ、さらに大型多層回路基板１１が達成されることにな
る。Next, the unfired large-sized multilayer circuit board 11 is
Baking is performed in an oxidizing atmosphere or an air atmosphere. The firing process includes a binder removal process and a sintering process. This firing temperature is performed until the peak temperature reaches 850 to 1050 ° C. As a result, the internal wiring layer 4 and the via-hole conductor 3 are formed inside, and the surface wiring layer 2 is formed on the surface, so that the large-sized multilayer circuit board 11 is achieved.
【００４２】その後、必要に応じて、表面配線層４に接
続する回路構成部品５を接合・実装する。また、キャビ
ティ９内に回路構成部品１５を配置して、ボンディング
ワイヤにより、回路構成部品１５と表面配線導体２とを
接合する。Thereafter, if necessary, the circuit component 5 connected to the surface wiring layer 4 is joined and mounted. Further, the circuit component 15 is arranged in the cavity 9, and the circuit component 15 and the surface wiring conductor 2 are joined by a bonding wire.
【００４３】そして、最後に、上述の分離線７に形成し
た分割溝にそって分割処理を行い、大型多層回路基板１
１から複数の多層回路基板１０を分離する。Finally, a dividing process is carried out along the dividing groove formed in the above-mentioned separating line 7, and the large-sized multilayer circuit board 1
A plurality of multilayer circuit boards 10 are separated from one.
【００４４】また、上述の多層回路基板１０の製造方法
において、絶縁突出層６、１６としては、格子状のグリ
ーンシートを用いて形成したが、その他に、例えば絶縁
層１ａ〜１ｄと実質同一材料、例えば、ガラス、無機物
フィラーとを有する絶縁ペーストを用いて、各グリーン
シートを積層圧着した後に、分離線部分にスクリーン印
刷により、所定幅で絶縁突出層６、１６となる塗膜を形
成し、乾燥処理して形成し、積層体と一体的に焼成処理
しても構わない。In the method of manufacturing the multilayer circuit board 10 described above, the insulating protruding layers 6 and 16 are formed by using a grid-like green sheet. However, other than that, for example, the insulating layers 1a to 1d are made of substantially the same material. , For example, using an insulating paste containing glass and an inorganic filler, after laminating and press-bonding each green sheet, screen coating is formed on the separation line portion to form the insulating protruding layers 6 and 16 with a predetermined width, It may be formed by performing a drying process, and may be fired integrally with the laminate.
【００４５】また、上述のオーバーコートガラス層８を
形成するにあたり、このガラスペーストを用いて、各グ
リーンシートを積層圧着した後に、キャビティ９の開口
周囲にスクリーン印刷により、所定幅で絶縁突出層１６
となる塗膜を形成し、乾燥処理して形成し、積層体と一
体的に焼成処理しても構わない。この時、各グリーンシ
ートを積層圧着した後に、隣接しあう各回路基板領域１
２の分離線７部分にスクリーン印刷により、所定幅で共
通的な絶縁突出層６となる塗膜を形成し、乾燥処理して
形成し、積層体と一体的に焼成処理しても構わない。In forming the above-mentioned overcoat glass layer 8, the green paste is laminated and pressure-bonded using this glass paste, and then the insulating protrusion layer 16 is formed with a predetermined width by screen printing around the opening of the cavity 9.
It is also possible to form a coating film to be formed, dry it and form it, and fire it integrally with the laminate. At this time, after each green sheet is laminated and pressure-bonded, each adjacent circuit board region 1
It is also possible to form a common coating film of the insulating protrusion layer 6 with a predetermined width on the separation line 7 of No. 2 by screen printing, dry it and form it, and fire it integrally with the laminate.
【００４６】さらに、図２では、表裏両主面に、絶縁突
出層６を形成しているが、例えば、表面層側のみに形成
しても構わない。Further, in FIG. 2, the insulating protruding layers 6 are formed on both the front and back main surfaces, but they may be formed only on the surface layer side, for example.
【００４７】尚、多層回路基板１０の裏面側に、端子電
極を形成するためには、裏面側の絶縁突出層６は端子電
極の厚みよりも薄くなるようにしなくてはならない。ま
た本発明は、基板実装面にキャビティを形成した場合に
も適用できる。In order to form the terminal electrode on the back surface side of the multilayer circuit board 10, the insulating protruding layer 6 on the back surface side must be thinner than the thickness of the terminal electrode. The present invention can also be applied to the case where a cavity is formed on the board mounting surface.
【００４８】なお、本発明は上記の実施の形態例に限定
されるものではなく、本発明の要旨を逸脱しない範囲内
での種々の変更や改良等は何ら差し支えない。例えば、
本発明は多層回路基板だけでなく単板にも適用できる。
また、基板材料としてガラスエポキシ基板を用いても良
い。The present invention is not limited to the above-mentioned embodiments, and various modifications and improvements can be made without departing from the scope of the present invention. For example,
The present invention can be applied not only to a multilayer circuit board but also to a single board.
Alternatively, a glass epoxy substrate may be used as the substrate material.
【００４９】[0049]
【実施例】本発明者は、上記方法により、平面形状が１
３．７５ｍｍ×８．０ｍｍで、基板の厚みが０．７５ｍ
ｍである多層回路基板１０を作製した。EXAMPLES The present inventor has made the plane shape 1 by the above method.
3.75 mm x 8.0 mm with a substrate thickness of 0.75 m
A multi-layer circuit board 10 having a thickness of m was produced.
【００５０】絶縁突出層１６の材料、突起量（表面から
の高さ）ｔ2、突起幅ｗ2を変化させて、多層回路基板１
０の抗折強度を比較した。By changing the material of the insulating protruding layer 16, the amount of protrusion (height from the surface) t 2 , and the protrusion width w 2 , the multilayer circuit board 1 is manufactured.
The bending strength of 0 was compared.
【００５１】なお、絶縁突出層６、１６の突起量ｔ2、
突起幅ｗ2はオーバーコートガラス層８と同一の材料を
選択的印刷し、表面粗さ計によって確認した。In addition, the protrusion amount t 2 of the insulating protrusion layers 6 and 16,
The protrusion width w 2 was confirmed by a surface roughness meter by selectively printing the same material as the overcoat glass layer 8.
【００５２】また、多層回路基板１０の抗折強度は、積
層基板の長手方向の両端からそれぞれ基板の長さの１／
４の部分を支点として、基板の中央を押した際に、基板
が割れたときの強度を測定した。評価基準は、抗折強度
が５０Ｎ以上のものを良品、５０Ｎ未満のものを不良品
とした。The bending strength of the multi-layer circuit board 10 is 1 / l of the length of the board from both ends in the longitudinal direction of the board.
When the center of the substrate was pressed with the portion 4 as a fulcrum, the strength when the substrate cracked was measured. As an evaluation standard, a product having a bending strength of 50 N or more was a good product and a product having a bending strength of less than 50 N was a defective product.
【００５３】[0053]
【表１】 [Table 1]
【００５４】実験の結果、絶縁突出層１６の突起量ｔ2
が１μｍ以上、突起幅ｗ2が１％以上である本実施例で
は、抗折強度が５０Ｎ以上となり、良好の結果となっ
た。As a result of the experiment, the protrusion amount t 2 of the insulating protrusion layer 16
Of 1 μm or more and the protrusion width w 2 of 1% or more, the bending strength was 50 N or more, which was a good result.
【００５５】絶縁突出層１６の突起量ｔ2が３０μｍを
越えると、試料番号１４〜１６に示すように、積層基板
１上にクリーム半田塗布性が劣化してしまう。When the protrusion amount t 2 of the insulating protruding layer 16 exceeds 30 μm, the cream solder applicability deteriorates on the laminated substrate 1 as shown in sample numbers 14 to 16.
【００５６】尚、絶縁突出層６は、オーバーコートガラ
ス材料以外に、例えば、絶縁層１ａ〜１ｄと同様のガラ
ス−セラミック材料（スラリーを印刷またはシートを圧
着）しても、試料番号１７のように良好な結果が得られ
た。The insulating protruding layer 6 may be formed of the same glass-ceramic material as the insulating layers 1a to 1d (printing a slurry or press-bonding a sheet) in addition to the overcoat glass material, as in Sample No. 17. Very good results were obtained.
【００５７】これに対し、絶縁突出層１６の突起量ｔ2
が０、０．５μｍである比較の試料番号１〜３では、抗
折強度が５０Ｎ未満となった。On the other hand, the protrusion amount t 2 of the insulating protrusion layer 16
In Comparative Sample Nos. 1 to 3 having a value of 0 and 0.5 μm, the bending strength was less than 50N.
【００５８】[0058]
【発明の効果】本発明によれは、キャビティを有する多
層回路基板において、たわみ荷重がかけても、キャビテ
ィの開口周囲で割れや破壊が発生することがなく基板の
抗折強度が向上する。また、積層基板上に安定して回路
構成部品が搭載できる多層回路基板となる。According to the present invention, in a multilayer circuit board having a cavity, even if a flexural load is applied, cracking or breakage does not occur around the opening of the cavity, and the bending strength of the board is improved. Further, it becomes a multilayer circuit board on which circuit components can be stably mounted on the laminated board.
【図１】本発明に係る多層回路基板の積層基板の外観斜
視図である。FIG. 1 is an external perspective view of a laminated board of a multilayer circuit board according to the present invention.
【図２】（ａ）は多層回路基板の平面状態の模式図であ
り、（ｂ）はその断面状態の模式図である。FIG. 2A is a schematic diagram of a planar state of a multilayer circuit board, and FIG. 2B is a schematic diagram of its cross-sectional state.
【図３】図１の多層回路基板の部分断面図である。FIG. 3 is a partial cross-sectional view of the multilayer circuit board of FIG.
【図４】図１の多層回路基板が抽出される大型多層回路
基板の平面図である。FIG. 4 is a plan view of a large-sized multilayer circuit board from which the multilayer circuit board of FIG. 1 is extracted.
１０ 多層回路基板 １ 基板 ２ 内部配線層 ３ ビアホール導体 ４ 表面配線層 ５、１５ 回路構成部品 ７ 分離線 ８ オーバーコートガラス層 ９ キャビティ １６ 絶縁突出層 ｔ2 突起量 ｗ2 突起幅10 Multilayer Circuit Board 1 Board 2 Internal Wiring Layer 3 Via Hole Conductor 4 Surface Wiring Layers 5, 15 Circuit Components 7 Separation Line 8 Overcoat Glass Layer 9 Cavity 16 Insulation Protrusion Layer t 2 Protrusion Amount w 2 Protrusion Width
Claims (5)
内部に、内部配線層を、前記積層基板の表面に表面配線
層及び回路構成部品を収納したキャビティを夫々形成し
てなる多層回路基板において、 前記積層基板のキャビティの開口周囲に、該積層基板の
表面から突出する絶縁突出層を周設したことを特徴とす
る多層回路基板。1. A multilayer circuit in which an internal wiring layer is formed inside a laminated substrate formed by laminating a plurality of insulating layers, and a surface wiring layer and a cavity for accommodating circuit components are formed on the surface of the laminated substrate. In the substrate, an insulating projecting layer projecting from the surface of the laminated substrate is provided around the opening of the cavity of the laminated substrate.
絶縁材料から構成されていることを特徴とする請求項１
記載の多層回路基板。2. The insulating protrusion layer is made of the same insulating material as that of the insulating layer.
The multilayer circuit board described.
ス層で被覆されているとともに、前記絶縁突出層は、該
オーバーコートガラス層と同一の材料からなることを特
徴とする請求項１記載の多層回路基板。3. The multilayer according to claim 1, wherein the surface wiring layer is covered with an overcoat glass layer, and the insulating protrusion layer is made of the same material as the overcoat glass layer. Circuit board.
能なガラスと無機物フィラとからなるガラス−セラミッ
ク材料で構成されていることを特徴とする請求項１記載
の多層回路基板。4. The multilayer circuit board according to claim 1, wherein the insulating layer is made of a glass-ceramic material composed of glass and an inorganic filler that can be fired at 1100 ° C. or lower.
絶縁突出層は、前記積層基板の主面から１〜３０μｍの
高さで突出していることを特徴とする請求項１記載の多
層回路基板。5. The multilayer circuit board according to claim 1, wherein the insulating protrusion layer protruding along the periphery of the cavity protrudes from the main surface of the laminated substrate at a height of 1 to 30 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001230882A JP2003046253A (en) | 2001-07-31 | 2001-07-31 | Multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001230882A JP2003046253A (en) | 2001-07-31 | 2001-07-31 | Multilayer circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003046253A true JP2003046253A (en) | 2003-02-14 |
Family
ID=19063014
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001230882A Pending JP2003046253A (en) | 2001-07-31 | 2001-07-31 | Multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003046253A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006093570A (en) * | 2004-09-27 | 2006-04-06 | Kyocera Corp | Ceramic green sheet laminate for multi-cavity wiring board, multi-cavity wiring board, package for housing electronic component, electronic equipment and method for manufacturing multi-cavity wiring board |
| CN105789161A (en) * | 2014-12-22 | 2016-07-20 | 恒劲科技股份有限公司 | Packaging structure and manufacturing method therefor |
| JP2023501380A (en) * | 2019-11-08 | 2023-01-18 | レイセオン カンパニー | Method for forming channels in a printed circuit board by stacking slotted layers |
-
2001
- 2001-07-31 JP JP2001230882A patent/JP2003046253A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006093570A (en) * | 2004-09-27 | 2006-04-06 | Kyocera Corp | Ceramic green sheet laminate for multi-cavity wiring board, multi-cavity wiring board, package for housing electronic component, electronic equipment and method for manufacturing multi-cavity wiring board |
| JP4562474B2 (en) * | 2004-09-27 | 2010-10-13 | 京セラ株式会社 | Manufacturing method of multi-cavity wiring board |
| CN105789161A (en) * | 2014-12-22 | 2016-07-20 | 恒劲科技股份有限公司 | Packaging structure and manufacturing method therefor |
| JP2023501380A (en) * | 2019-11-08 | 2023-01-18 | レイセオン カンパニー | Method for forming channels in a printed circuit board by stacking slotted layers |
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