JP4569265B2 - Ceramic multilayer substrate and manufacturing method thereof - Google Patents

Description

  The present invention relates to a ceramic multilayer substrate including a plurality of chip-shaped ceramic multilayer components and a method for manufacturing the same, and more specifically, highly reliable with suppressed variation in characteristic values between the plurality of chip-shaped ceramic multilayer components. The present invention relates to a ceramic multilayer substrate and a manufacturing method thereof.

  Conventional techniques of this type include a multilayer ceramic substrate with built-in electronic components described in Patent Document 1, a multilayer ceramic substrate described in Patent Document 2, and a method for manufacturing the same.

  An electronic component built-in multilayer ceramic substrate described in Patent Document 1 includes a multilayer ceramic substrate, a chip-type electronic component housed in a space formed by a recess or a through hole in the multilayer ceramic substrate, and an interlayer between the multilayer ceramic substrates. Or a conductor for wiring the chip-type electronic component provided in the space. Thus, since the chip-type electronic component is accommodated in the space in the multilayer ceramic substrate, a multilayer ceramic substrate having a desired shape can be obtained without deteriorating the flatness.

  In the case of the method for manufacturing a multilayer ceramic substrate described in Patent Document 2, a functional element such as a capacitor element, an inductor element, or a resistance element is obtained by using a plate-like sintered body plate obtained by firing a ceramic functional element in advance. Then, these functional elements are built in the unsintered composite laminate. The unsintered composite laminate includes a base green layer, a constraining layer containing a hardly sinterable material, and a wiring conductor. When firing this, the base green layer is formed by the action of the constraining layer. Shrinkage in the main surface direction is suppressed. In this technology, a multilayer ceramic substrate is manufactured by a non-shrinking method that suppresses shrinkage in the main surface direction, so that unsintered composite laminates with built-in functional elements are not suitable for problems such as cracks and delamination in the sintered body plate. Can be fired without causing any interfering of components, and mutual diffusion of components does not occur between the functional element and the green layer for the substrate, and the characteristics of the functional element are maintained even after firing.

JP-A-61-288498 JP 2002-84067 A

  However, in the case of the multilayer ceramic substrate described in Patent Document 2 using the non-shrinkage construction method, for example, if a plurality of multilayer ceramic capacitors having the same specifications are incorporated instead of the sintered body plate, depending on the substrate, a plurality of multilayer ceramic substrates may be stacked. Variations in the characteristic values between the ceramic capacitors have increased, and in some cases, cracks have occurred in the multilayer ceramic capacitor.

The present invention has been made to solve the above-described problems, and can suppress variations in characteristic values between chip-like ceramic multilayer components such as a plurality of built-in multilayer ceramic capacitors, and can also provide a plurality of chips. Can prevent cracks in the ceramic laminated parts and reliably connect the connecting conductors in the ceramic laminate to the chip ceramic laminated parts even if the ceramic green sheet is misaligned during lamination or shrinks during firing. it is Ru can be, and its object is to provide a highly reliable ceramic multilayer substrate and a manufacturing method thereof.

  As a result of various investigations regarding the variation in characteristics of a plurality of multilayer ceramic capacitors incorporated in a multilayer ceramic substrate and the cause of cracks in the multilayer ceramic capacitor, the present inventors have obtained the following knowledge.

  That is, as described in Patent Document 1, it is not a big problem when the ceramic green sheet is formed by providing an opening and housing a chip-shaped ceramic multilayer component such as a multilayer ceramic capacitor in the opening. When the chip-shaped ceramic multilayer component is disposed on the surface of the ceramic green sheet without forming an opening in the ceramic green sheet as described in Patent Document 2, the chip-shaped ceramic multilayer component is formed at the time of firing the green sheet multilayer body. Since a large pressure is applied, it has been found that the piezoelectric effect is induced in the chip-shaped ceramic multilayer component by this large pressure, and the characteristic value fluctuates greatly.

  In particular, in the non-shrinkage method, the substrate material does not shrink in the plane direction during firing, and the substrate material shrinks much in the thickness direction due to the viscous flow of the substrate material. However, in reality, the action of the constraining layer is difficult to achieve compared to the surface layer part of the substrate constrained by the constraining layer, and the compression rate (compression force) varies depending on the depth of the substrate. It is considered that the characteristic value varies depending on the built-in depth of the multilayer ceramic capacitor because the piezoelectric effect received by the multilayer ceramic capacitor is different. In other words, it has been found that if a plurality of monolithic ceramic capacitors are arranged at the same depth from the surface of the substrate, variations in the respective characteristic values can be suppressed. This can be said to be common to chip-shaped ceramic multilayer parts using a dielectric ceramic material that exhibits a piezoelectric effect.

  In addition, chip-shaped ceramic multilayer parts such as multilayer ceramic capacitors have a laminated structure in which a plurality of dielectric ceramic layers are laminated, so that they are strong against forces acting in a direction perpendicular to the surface direction. It is weak against forces acting in the surface direction. Therefore, it is considered that cracks are likely to occur when the built-in chip-shaped ceramic multilayer component is arranged perpendicular to the surface direction.

The present invention has been made based on the above knowledge, and the method for producing a ceramic multilayer substrate according to claim 1 is a ceramic sintered body in which a plurality of dielectric ceramic layers are laminated on the surface of a ceramic green sheet. A step of disposing a plurality of chip-shaped ceramic multilayer parts having internal electrodes between the dielectric ceramic layers so that the interface of the dielectric ceramic layers is parallel to the surface of the ceramic green sheet And laminating the ceramic green sheet on which the plurality of chip-shaped ceramic multilayer components are arranged together with other ceramic green sheets to produce a green sheet laminate including the plurality of chip-shaped ceramic multilayer components. When, and a step of firing the green sheet laminate, prepared Engineering of the green sheet laminate A step of forming the first and second connection conductor portions on the upper and lower ceramic green sheets sandwiching the chip-shaped ceramic multilayer component, and the chip-shaped ceramic multilayer component between the upper and lower ceramic green sheets, By crimping these ceramic green sheets, the first connection conductor portion extends in one direction from the interface of the upper and lower ceramic green sheets along the end surface of the chip-shaped ceramic multilayer component, and the second connection conductor portion It extends along the end surface of the chip-shaped ceramic multilayer component from the interface in a direction opposite to the first connection conductor portion, and connects the first and second connection conductor portions to the terminal electrodes of the chip-shaped ceramic multilayer component. And a process .

According to a second aspect of the present invention, there is provided a method for producing a ceramic multilayer substrate comprising: a ceramic sintered body formed by laminating a plurality of dielectric ceramic layers on a surface of a ceramic green sheet; A step of arranging a plurality of chip-shaped ceramic laminated parts having internal electrodes between the layers so that the interface of the dielectric ceramic layer is parallel to the surface of the ceramic green sheet; and the plurality of chip-shaped ceramics Laminating the ceramic green sheet on which the laminated parts are arranged together with other ceramic green sheets to produce a green sheet laminated body incorporating the plurality of chip-shaped ceramic laminated parts, and firing the green sheet laminated body And the step of producing the green sheet laminate includes the chip ceramic product. A step of directly connecting a terminal electrode of the component to a via conductor provided in the ceramic green sheet, and a step of applying pressure to the chip-shaped ceramic multilayer component to connect the chip-shaped ceramic multilayer component to the via conductor. And a step of forming a portion .

According to a third aspect of the present invention, there is provided the method for manufacturing a ceramic multilayer substrate according to the first or second aspect, wherein the chip-shaped ceramic multilayer component has a thickness A and a length in the longitudinal direction. B satisfies the relationship of 2 ≦ (B / A) ≦ 40 .

Moreover, the manufacturing method of the ceramic multilayer substrate of Claim 4 of this invention is the invention of any one of Claims 1-3 in the invention of any one of Claims 1-3. On the at least one main surface of the said green sheet laminated body, A step of disposing a shrinkage suppression layer mainly composed of ceramic that is not sintered at the sintering temperature of the ceramic green sheet; a step of firing both at the sintering temperature of the ceramic green sheet; and the shrinkage suppression. And a step of removing the layer .

Moreover, the manufacturing method of the ceramic multilayer substrate according to claim 5 of the present invention is the invention according to any one of claims 1 to 4, wherein the green sheet laminate is pressurized in the firing step. It is characterized by firing .

Moreover, the manufacturing method of the ceramic multilayer substrate of Claim 6 of this invention is the invention of any one of Claims 1-5, In the production process of the said green sheet laminated body, the said green sheet A shrinkage suppression layer mainly composed of a ceramic material that does not substantially sinter at the sintering temperature of the ceramic green sheet is disposed inside the laminate, and the shrinkage suppression layer is disposed in the firing step of the green sheet laminate. The provided green sheet laminate is fired at the sintering temperature of the ceramic green sheet .

Moreover, the manufacturing method of the ceramic multilayer substrate of Claim 7 of this invention is the invention of any one of Claims 1-6, In the manufacturing process of the said green sheet laminated body, the said green sheet the same interface stack section is intended 請 characterized by placing a plurality of said chip-like ceramic multilayer part of the same species.

Moreover, the manufacturing method of the ceramic multilayer substrate according to claim 8 of the present invention is the method according to any one of claims 1 to 7, wherein the ceramic green sheet is mainly made of a low-temperature sintered ceramic material. A low-temperature sintered ceramic green sheet as a component is used .

Moreover, the ceramic multilayer board according to claim 9 of the present invention comprises a ceramic laminate in which a plurality of ceramic layers are laminated, a plurality provided a chip-on interface of the ceramic laminate of the upper and lower ceramic layers A multilayer ceramic substrate comprising: a ceramic multilayer component, wherein the chip-shaped ceramic multilayer component comprises a ceramic sintered body in which a plurality of dielectric ceramic layers are laminated, and an interlayer between the dielectric ceramic layers. The plurality of chip-shaped ceramic laminated parts are provided at the same interface with the dielectric ceramic layers parallel to the ceramic layers, and the ceramic layers The terminal electrode formed at the end in the direction orthogonal to the electrode is electrically connected to the connection conductor formed in the ceramic laminate, and the contact The conductor includes a first connecting conductor extending in one direction along the terminal electrode of the chip-shaped ceramic multilayer component from the interface, and a second extending from the interface along the terminal electrode in a direction opposite to the first connecting conductor. And a connection conductor .

According to a tenth aspect of the present invention, there is provided a ceramic multilayer substrate in which a plurality of chip-shaped ceramics are provided at an interface between a ceramic laminate in which a plurality of ceramic layers are laminated and upper and lower ceramic layers in the ceramic laminate. a ceramic multilayer substrate comprising a laminate device, and the chip-like ceramic multilayer parts, a ceramic sintered body in which a plurality of dielectric ceramic layers are laminated between the layers of and the body of the dielectric ceramic layers have a formed internal electrodes, the plurality of chip-like ceramic multilayer parts, each dielectric ceramic layer provided on the same said surface with parallel to the ceramic layer, and, and each of the ceramic layers The terminal electrodes formed at the ends in the orthogonal direction are electrically connected directly to the via conductors formed in the ceramic laminate. Connecting portions between the terminal electrodes of the via conductor is characterized in that said terminal electrodes are formed as a connection step portion bites from the upper surface of the via conductor.

Further, in the ceramic multilayer substrate according to claim 11 of the present invention, in the invention according to claim 9 or claim 10, the chip-shaped ceramic multilayer component has a thickness A and a length B in the longitudinal direction. The relationship of 2 ≦ (B / A) ≦ 40 is satisfied.

Moreover, the ceramic multilayer substrate according to claim 12 of the present invention is the invention according to any one of claims 9 to 11, a plurality of field surface of the ceramic laminate portion, a plurality of chips It is characterized in that a multilayer ceramic laminated part is incorporated.

According to the invention described in this onset bright, it is possible to suppress the variation of the characteristic value between the chip-shaped ceramic laminated parts such as a plurality of laminated ceramic capacitors built, a plurality of chip-like ceramic multilayer part it is possible to prevent cracks, moreover Ru can be reliably connect the connecting conductor and the chip-shaped ceramic multilayer part of the ceramic laminated body even when shrinkage during misalignment or baking at the time of stacking the ceramic green sheets It is possible to provide a highly reliable ceramic multilayer substrate and a method for manufacturing the same.

  Hereinafter, the present invention will be described based on the embodiment shown in FIGS. 1A and 1B are views showing an embodiment of the ceramic multilayer substrate of the present invention, respectively, FIG. 1A is a sectional view showing the whole, and FIG. 1B is a main part of FIG. FIG. 2 and FIG. 3 are process diagrams showing the main part of the manufacturing process of the ceramic multilayer substrate shown in FIG. 1, and FIGS. 4 (a) and 4 (b) are the ceramic multilayer substrates of the present invention. It is a figure which expands and shows the principal part of other embodiment, (a) is the sectional drawing, (b) is sectional drawing which shows the process at the time of incorporating the chip-shaped ceramic multilayer component shown in (a), A figure 5 is an enlarged cross-sectional view showing the main part of still another embodiment of the ceramic multilayer substrate of the present invention, and FIG. 6 is an enlarged cross-sectional view showing the main part of still another embodiment of the ceramic multilayer substrate of the present invention. FIG. 7 is a cross-sectional view showing the main part of the manufacturing process of one embodiment of the present invention, and FIG. 8 shows the manufacturing of another embodiment of the present invention. Cross-sectional view showing the main part of the extent, FIG. 9 is a sectional view showing still an essential part of a manufacturing process of another embodiment of the present invention.

First Embodiment A ceramic multilayer substrate 10 according to the present embodiment includes, for example, a ceramic laminate 11 in which a plurality of ceramic layers 11A are laminated, as shown in FIG. A plurality of chip-shaped ceramic multilayer components 12 provided at the interface between the upper and lower ceramic layers 11A, 11A, and the plurality of chip-shaped ceramic multilayer components 12 are arranged at the same interface.

  As shown in FIG. 1A, an internal conductor pattern 13 is formed inside the ceramic laminate 11. The internal conductor pattern 13 is a via that connects the in-plane conductor 13A formed in a predetermined pattern on the surface of the ceramic layer 11A and the upper and lower in-plane conductors 13A formed through the ceramic layer 11A in a predetermined pattern. It consists of a conductor 13B. Surface electrodes 14 and 14 are respectively formed on the upper and lower surfaces of the ceramic laminate 11, and the upper and lower surface electrodes 14 and 14 are electrically connected to each other through the internal conductor pattern 13. For example, a surface mount component (not shown) such as an active element such as a semiconductor element or a gallium arsenide semiconductor element or a passive element such as a capacitor, inductor, or resistor can be mounted on the upper surface electrode 14. Further, the lower surface electrode 14 can be used as a terminal electrode when the ceramic multilayer substrate 10 is mounted on a mounting substrate such as a mother board.

  For example, as shown in FIG. 1B, the chip-shaped ceramic multilayer component 12 includes an element body made of a ceramic sintered body and external terminal electrodes 12A and 12A formed at both ends of the element body. And it is connected to the in-plane conductor 13A via the external terminal electrodes 12A and 12A at both ends. A connecting portion 13C of the in-plane conductor 13A with the external terminal electrode 12A bites into the lower ceramic layer 11A together with the chip-shaped ceramic multilayer component 12 and has a substantially L-shaped cross section. As shown in the figure, the chip-shaped ceramic multilayer component 12 is interposed between a dielectric ceramic laminate in which a plurality of dielectric ceramic layers 12B are laminated, and upper and lower dielectric ceramic layers 12B and 12B, and left and right A plurality of internal electrodes 12C extending from the external terminal electrodes 12A, 12A to the opposing external terminal electrodes 12A, 12A, respectively, and a capacitor is formed by the upper and lower internal electrodes 12C, 12C and the dielectric ceramic layer 12B therebetween. Is formed.

A plurality of chip-like ceramic multilayer part 12 from each other in the same species, i.e. the material of the dielectric ceramic layer, the thickness of the layer, but the number of stacked layers is substantially the same, as shown in FIG. 1 (a), a predetermined The upper and lower ceramic layers 11 </ b> A and 11 </ b> A are arranged at the same depth from the upper surface of the ceramic laminated body 11 together at one interface. Since a plurality of chip-shaped ceramic multilayer parts 12 are arranged at the same interface in this way, even if a large pressure or shrinkage force acts on each chip-shaped ceramic multilayer part 12 during firing, these pressures are not applied to all chips. Since it acts with the substantially same magnitude | size with respect to the ceramic-like ceramic laminated component 12, the variation in the characteristic value between several chip-shaped ceramic laminated components 12 can be suppressed.

  Further, as shown in FIG. 1B, each of the plurality of chip-shaped ceramic laminated parts 12 has a dielectric ceramic layer 12B and an internal electrode 12C arranged in parallel to the interface of the ceramic layer 11A. . Since the dielectric ceramic layer 12B is parallel to the ceramic layer 11A, even if pressure or contraction force in a direction perpendicular to the interface of the ceramic layer 11A acts, these pressures cause the chip-shaped ceramic multilayer component 12 to cleave. Since it acts perpendicularly to the direction, it is possible to prevent the chip-shaped ceramic multilayer component 12 from being cracked.

  Further, when the thickness of the chip-shaped ceramic multilayer component 12 is defined as A and the length in the longitudinal direction thereof is defined as B, the thickness A and the length B preferably satisfy the relationship of 2 ≦ (B / A) ≦ 40. If the B / A is less than 2, the thickness of the chip-shaped ceramic multilayer component 12 is relatively large and easily receives the piezoelectric effect. Therefore, the characteristic value tends to vary, and if the B / A exceeds 40, the chip shape The thickness of the ceramic laminated component 12 is reduced, the mechanical strength is weakened, and the ceramic laminated component 12 is easily cracked by the pressure during pressurization. The thickness of the chip-like ceramic multilayer component is the thickness of the dielectric ceramic layer in the lamination direction.

Thus, the material of the ceramic laminate 11 is not particularly limited, but it is preferable to use a low temperature co-fired ceramic (LTCC) material. The low-temperature sintered ceramic material is a ceramic material that can be sintered at a temperature of 1050 ° C. or less and can be simultaneously fired with silver, copper, or the like having a small specific resistance. Specifically, as the low-temperature sintered ceramic, a glass composite LTCC material obtained by mixing borosilicate glass with ceramic powder such as alumina or forsterite, ZnO-MgO-Al ₂ O ₃ -SiO ₂ crystal Non-glass using crystallized glass-based LTCC material using a crystallized glass, BaO—Al ₂ O ₃ —SiO ₂ ceramic powder, Al ₂ O ₃ —CaO—SiO ₂ —MgO—B ₂ O ₃ ceramic powder, etc. System LTCC materials and the like. By using a low-temperature sintered ceramic material as the material of the ceramic laminate 11, a low-melting-point metal having a low resistance and a low melting point such as Ag or Cu can be used as the internal conductor pattern 13 and the surface electrode 14. 11 and the internal conductor pattern 13 can be simultaneously fired at a low temperature of 1050 ° C. or lower.

  The material of the chip-shaped ceramic laminated component 12 is not particularly limited as long as it uses a dielectric ceramic material. For example, ceramic sintering made of a dielectric ceramic material such as barium titanate, which is fired at 1200 ° C. or higher. The body is the body. Examples of the chip-shaped ceramic multilayer component 12 include a multilayer ceramic capacitor. The chip-shaped ceramic multilayer component 12 is not limited to a multilayer ceramic capacitor as long as it is formed of a dielectric ceramic material, and may be, for example, a multilayer inductor utilizing the properties of a magnetic material.

  Next, a method for manufacturing the ceramic multilayer substrate 10 will be described with reference to FIGS. In this embodiment, the case where the ceramic multilayer substrate 10 is produced using a non-shrinkage method will be described. The non-shrinkage construction method refers to a construction method in which the dimension in the plane direction of the multilayer substrate does not substantially change before and after firing the ceramic multilayer substrate.

  In the present embodiment, as a chip-shaped ceramic multilayer component 112 having a ceramic sintered body as a base body, a chip-shaped ceramic multilayer component satisfying the relationship of a thickness A and a length B in the longitudinal direction of 2 ≦ B / A ≦ 40. Prepare. Then, a predetermined number of ceramic green sheets 111A shown in FIGS. 2 and 3 are produced using, for example, a slurry containing a low-temperature sintered ceramic material. After that, by forming a via hole by laser processing or punching processing, and pushing a conductive paste kneaded with metal powder, thermosetting resin and organic solvent mainly composed of Ag powder or Cu powder into the via hole A via conductor portion 113B for the via conductor is formed. Then, the conductive paste is printed on each ceramic green sheet 111A in a predetermined pattern by screen printing and dried to form the in-plane conductor portion 113A. The in-plane conductor portion 113A and the via conductor portion 113B form an inner conductor pattern portion 113.

  The chip-shaped ceramic multilayer component at the time of firing is denoted by reference numeral “112”, and the chip-shaped ceramic multilayer component after the temperature lowering after firing is denoted by reference numeral “12”.

  On the upper surface of the ceramic green sheet 111A on which the plurality of chip-shaped ceramic multilayer parts 112 are arranged, an organic adhesive is applied or sprayed on the in-plane conductor portion 113A side using a spray or the like to form an organic adhesive layer (see FIG. 2), the pair of external terminal electrodes 112A and 112A of the chip-shaped ceramic multilayer component 112 are aligned with the in-plane conductors 113A and 113A on the ceramic green sheet 111A, as shown in FIG. By this alignment, the dielectric ceramic layer (not shown) of the chip-shaped ceramic multilayer component 112 becomes parallel to the surface of the ceramic green sheet 111A. In this state, the chip-shaped ceramic multilayer component 112 is mounted on the ceramic green sheet 111A, and the chip-shaped ceramic multilayer component 112 is bonded and fixed onto the in-plane conductor 113A via the organic adhesive layer. In addition, as an organic adhesive agent, the mixture etc. which added the synthetic rubber, the synthetic resin, and the plasticizer can be used. The thickness of the organic adhesive layer is preferably 3 μm or less in the case of coating and 1 μm or less in the case of spraying.

Thereafter, as shown in FIG. 2, the ceramic green sheets 111A having the in-plane conductor portions 113A and the via conductor portions 113B are laminated in a predetermined order, and the ceramic green sheets 111A having the uppermost surface electrode portions 114 are laminated. The green sheet laminated body 111 shown in 3 is obtained. Then, the shrinkage suppression layers 115 are disposed on the upper and lower surfaces of the green sheet laminate 111 as shown in FIG. 2, and the green sheet laminate 111 is thermocompression bonded at a predetermined temperature and pressure via the upper and lower shrinkage suppression layers 115. As a result, the pressure-bonded body 110 shown in FIG. 3 is obtained. As the shrinkage suppression layer 115, a hardly sinterable powder that does not sinter at the sintering temperature of the green sheet laminate 111 (for example, a ceramic powder having a high sintering temperature such as Al ₂ O ₃ ), specifically, Al ₂ A slurry formed from a slurry containing O ₃ as a main component and an organic binder as a sub component as shown in FIG. The surface electrode 114 formed on the lower surface of the green sheet laminate 111 is provided on the lower shrinkage suppression layer 115.

  In all the chip-shaped ceramic multilayer components 112, the dielectric ceramic layers are arranged perpendicular to the pressing direction, so that the interface of the dielectric ceramic layers of each chip-shaped ceramic multilayer component 112 may be cleaved. And no cracks occur. Furthermore, since the chip-shaped ceramic multilayer component 112 is used as the chip-shaped ceramic multilayer component 112, the thickness A and the length B in the longitudinal direction satisfy the relationship of 2 ≦ B / A ≦ 40. The component 112 is less susceptible to the piezoelectric effect and will not crack.

  After obtaining the pressure-bonded body 110, the pressure-bonded body 110 is fired at, for example, 870 ° C. in an air atmosphere to obtain the ceramic multilayer substrate 10 of the present embodiment. By this firing, the green sheet laminate 111 is sintered, and the ceramic laminate 11 having a plurality of chip-like ceramic laminate parts 12 built in at the same interface is obtained between the upper and lower shrinkage suppression layers 115. During firing, the shrinkage in the surface direction of the green sheet laminate 111 is suppressed by the upper and lower shrinkage suppression layers 115, 115. However, the green sheet laminate 111 is compressed in the vertical direction by the viscous flow of the low-temperature sintered ceramic material. A large compressive force acts on the plurality of chip-shaped ceramic laminated parts 112 from the vertical direction. However, since the plurality of chip-shaped ceramic multilayer parts 112 are arranged at the same depth from the upper surface of the green sheet multilayer body 111, substantially the same compressive force acts on the plurality of chip-shaped ceramic multilayer parts 112, Variations in each characteristic value can be suppressed and prevented.

  The firing temperature is preferably a temperature at which the low-temperature sintered ceramic material is sintered, for example, in the range of 800 to 1050 ° C. If the firing temperature is less than 800 ° C., the ceramic component of the green sheet laminate 111 may not be sufficiently sintered, and if it exceeds 1050 ° C., the metal particles in the internal conductor pattern portion 113 may melt and diffuse into the ceramic layer 11A. In addition, the characteristic value may vary due to mutual diffusion of the respective materials between the built-in chip-shaped ceramic multilayer component 12 and the ceramic layer 11A.

  After firing, the upper and lower shrinkage suppression layers 115 are removed by blasting or ultrasonic cleaning to obtain the ceramic multilayer substrate 10. A final product can be obtained by mounting a predetermined surface mounting component (not shown) on the surface electrode 14 of the ceramic multilayer substrate 10 by a technique such as soldering. In the present embodiment, the external terminal electrode 112A of the ceramic sintered body that becomes the chip-shaped ceramic multilayer component 12 is coated with a conductive paste and dried even if the conductive paste is applied and baked. It may be the one before baking.

  As described above, according to the present embodiment, a plurality of the ceramic green sheets 111A are arranged on the surface so that the interface of the dielectric ceramic layer 112B of the chip-shaped ceramic multilayer component 112 is parallel to the surface of the ceramic green sheets 111A. The chip-shaped ceramic multilayer component 112 is disposed, and the ceramic green sheet 111A on which the chip-shaped ceramic multilayer component 112 is disposed is laminated together with the other ceramic green sheets 111A, and a plurality of chip-shaped ceramic multilayer components 112 are incorporated. After producing the green sheet laminate 111, the green sheet laminate 111 is fired, so that the following effects can be obtained.

  That is, when the green sheet laminate 111 is fired, substantially the same compressive force is applied to the plurality of chip-like ceramic laminate parts 112, and consequently substantially the same piezoelectric effect is exhibited. Variation in characteristic values between the ceramic laminate parts 112 can be suppressed. Further, since the dielectric ceramic layer of the chip-shaped ceramic multilayer component 112 is arranged in parallel to the surface direction of the green sheet multilayer body 111, there is no possibility of causing cracks in the chip-shaped ceramic multilayer component 112.

  In addition, according to the present embodiment, the chip-shaped ceramic multilayer component 12 has a thickness A and a length B in the longitudinal direction satisfying a relationship of 2 ≦ (B / A) ≦ 40. When the green sheet laminated body 111 is fired, it is difficult to receive the piezoelectric effect due to the applied pressure or compressive force, and the chip-shaped ceramic laminated component 112 can be prevented from cracking.

  In addition, according to the present embodiment, the shrinkage suppression layers 115 whose main component is a ceramic material that is not substantially sintered at the sintering temperature of the ceramic green sheet 111A are disposed on the upper and lower surfaces of the green sheet laminate 111. After firing both 111 and 115 at the sintering temperature of the ceramic green sheet 111A, in order to remove the shrinkage suppression layer 115, the shrinkage in the surface direction of the green sheet laminate 111 is suppressed, and between the ceramic layers 11A and 11A and between the ceramic layers. No cracks are generated between 11A and the chip-shaped ceramic multilayer component 12.

  Further, according to the present embodiment, since the low-temperature sintered ceramic green sheet mainly composed of the low-temperature sintered ceramic material is used as the ceramic green sheet 111A, the internal conductor pattern 13 and the surface electrode 14 are made of a low material such as Ag or Cu. A resistor and an inexpensive metal can be used, which can contribute to a reduction in manufacturing cost.

Second Embodiment As shown in FIG. 4, the ceramic multilayer substrate according to the present embodiment is the same as the above embodiment except that the connection structure between the external terminal electrode 12A and the in-plane conductor 13A of the chip-shaped ceramic multilayer component 12 is different from the above embodiment. The configuration is the same as in the embodiment. Therefore, in the following, the present embodiment will be described with the same reference numerals assigned to the same or corresponding parts as the above embodiment.

  In the present embodiment, the external terminal electrode 12 </ b> A and the in-plane conductor 13 </ b> A of the chip-shaped ceramic multilayer component 12 are connected via the connection conductor 16. As shown in FIG. 4A, the connection conductor 16 includes a first connection conductor 16A connected to the lower half of the external terminal electrode 12A and a second connection conductor connected to the upper half of the external terminal electrode 12A. 16B. As shown in the figure, the first connecting conductor 16A is connected to the lower ceramic layer 11A from the in-plane conductor 13A provided at the interface between the upper and lower ceramic layers 11A, 11A on which the chip-shaped ceramic multilayer component 12 is disposed. It extends downward along the interface with the end surface of the terminal electrode 12A, reaches the lower surface of the external terminal electrode 12A, and the cross-sectional shape of the side surface is formed in an L shape. As shown in the figure, the second connection conductor 16B includes an upper surface ceramic layer 11A and an external terminal from the in-plane conductor 13A provided at the interface between the upper and lower ceramic layers 11A and 11A on which the chip-shaped ceramic multilayer component 12 is disposed. It extends upward along the interface with the end surface of the electrode 12 and reaches the upper surface of the external terminal electrode 12A, and the cross-sectional shape of the side surface is formed in an inverted L shape. The widths of the first and second connection conductors 16 </ b> A and 16 </ b> B are preferably formed to have dimensions corresponding to at least the width of the chip-shaped ceramic multilayer component 12.

  Accordingly, the first and second connection conductors 16A and 16B continuously cover the upper surface end, the end surface, and the lower surface end of the chip-shaped ceramic multilayer component 12, and have a cross section so that the external terminal electrode 12A can be grasped from both the upper and lower surfaces. Is formed as a connecting conductor 16 having an angular C shape, and is electrically connected to three surfaces of the external terminal electrode 12A, preferably five surfaces including both side surfaces. Since the first and second connection conductors 16A and 16B are each formed wider than the line width of the in-plane conductor 13A, even if there is a positional deviation in the width direction of the in-plane conductor 13A from the in-plane conductor 13A. The in-plane conductor 13A is securely connected, and the in-plane conductor 13A and the external terminal electrode 12A are securely connected.

  In order to form the connection conductor 16, as shown in FIG. 4B, the in-plane conductor portions 113A, 113A and the first, first, and second ceramic green sheets 111A, 111A sandwiching the chip-shaped ceramic multilayer component 112 are preliminarily formed. The second connection conductor portions 116A and 116B are formed by a screen printing method. The lower ceramic green sheet 111A is integrally formed with the in-plane conductor portion 113A and the first connecting conductor portion 116A, and the upper ceramic green sheet 111A is integrally formed with the in-plane conductor portion 113A and the second connecting conductor portion 116B. Form. Then, as shown in the figure, the external terminal electrode 112A of the chip-shaped ceramic multilayer component 112 is mounted in alignment with the first connection conductor portion 116A of the lower ceramic green sheet 111A. Next, the second connecting conductor portion 116B of the upper ceramic green sheet 111A is aligned with the external terminal electrode 112A of the chip-shaped ceramic multilayer component 112, and the upper ceramic green sheet 111A is laminated on the lower ceramic green sheet 111A. The chip-shaped ceramic multilayer component 112 is incorporated. After that, a green sheet laminate is produced in the same manner as in the above embodiment, and the ceramic multilayer substrate is produced by pressing and firing the green sheet laminate via the shrinkage suppression layer.

  According to the present embodiment, the in-plane conductor portions 113A and 113A including the first and second connection conductor portions 116A and 116B are formed on the upper and lower ceramic green sheets 111A and 111A, respectively, and between these ceramic green sheets 111A and 111A. The chip-shaped ceramic multilayer component 112 is disposed on the ceramic green sheets 111A and 111A and the first connecting conductor portion 116A is moved downward from the interface between the upper and lower ceramic green sheets 111A and 111A. The second connecting conductor portion 116B extends along the end surface of the chip-shaped ceramic laminated component 112 from the interface in the direction opposite to the first connecting conductor portion 116A. Two connecting conductors 116A and 116B are formed into chip-shaped ceramics. In order to connect to the external terminal electrode 112A of the layer component 112, disconnection between the external terminal electrode 12A of the chip-shaped ceramic multilayer component 12 and the in-plane conductor 13A due to the positional deviation when laminating the ceramic green sheets 111A or shrinkage during firing is performed. This can be reliably prevented by the first and second connection conductors 16, and the reliability of the connection structure between the chip-shaped ceramic multilayer component 12 and the in-plane conductor 13A, and thus the internal conductor pattern 13, can be improved.

Third Embodiment A ceramic multilayer substrate according to the present embodiment is configured in the same manner as in the above embodiment except that the external terminal electrode 12A of the chip-shaped ceramic multilayer component 12 is connected to the via conductor 13B as shown in FIG. ing. Therefore, in the following, the present embodiment will be described with the same reference numerals assigned to the same or corresponding parts as the above embodiment.

  In the present embodiment, the pair of external terminal electrodes 12A, 12A of the chip-shaped ceramic multilayer component 12 are directly connected to the via conductors 13B, 13B as shown in FIG. Step portions 13D and 13D are formed on the upper end surfaces of the pair of via conductors 13B and 13B, respectively, and external terminal electrodes 12A and 12A are connected to the step portions 13D and 13D. The step portion 13D is formed such that half of the upper end surface of the via conductor 13B is cut out, and the cross-sectional shape is L-shaped. Therefore, the external terminal electrodes 12A and 12A of the chip-shaped ceramic multilayer component 12 are connected to the via conductors through the two surfaces of the vertical wall surface and the bottom surface of the step portions 13D and 13D in which the substantially lower half of each end portion faces each other. 13B and 13B.

  The connection structure can be formed when the green sheet laminate is formed. That is, when a chip-shaped ceramic multilayer component is directly connected to a via conductor portion provided on a ceramic green sheet and then pressure is applied to the chip-shaped ceramic multilayer component, half of the upper end surface of the via conductor portion is compressed and deformed to form a chip shape. A connecting step with the ceramic laminated part is formed. Therefore, the via conductor portion is not cut at the time of stretching unlike the in-plane conductor portion, and the chip-shaped ceramic multilayer component and the via conductor portion can be reliably connected.

  According to this embodiment, since the chip-shaped ceramic multilayer component 12 is directly connected to the via conductor 13B, the chip-shaped ceramic multilayer component 12 is disconnected even if there is a slight misalignment between the external terminal electrode 12A of the chip-shaped ceramic multilayer component 12 and the via conductor 13B. The two 12A and 13B can be reliably connected without any problems.

Fourth Embodiment A ceramic multilayer substrate of the present embodiment is configured in the same manner as the ceramic multilayer substrate 10 shown in FIG. 1 except that a shrinkage suppression layer 15A is interposed between the ceramic layers 11A as shown in FIG. Has been. Therefore, in the following, the present embodiment will be described with the same reference numerals assigned to the same or corresponding parts as the above embodiment.

  In this embodiment, when producing a green sheet laminate, for example, a ceramic green sheet and a shrinkage suppression layer are stacked to produce a composite sheet. When a chip-shaped ceramic multilayer component is incorporated, an in-plane conductor and a via conductor are formed on the ceramic green sheet side of a single composite sheet, and the chip-shaped ceramic multilayer component is mounted on the ceramic green sheet. The ceramic laminated parts are joined and fixed on a ceramic green sheet. Next, ceramic green sheets of other composite sheets are laminated toward the chip-shaped ceramic laminated component side. Thereafter, a composite sheet containing chip-shaped ceramic multilayer parts and another composite sheet are laminated to produce a green sheet laminate and fired. When the green sheet laminate is fired, the glass component of the ceramic green sheet diffuses into the shrinkage suppression layer, and the ceramic materials of the shrinkage suppression layer are combined and integrated, and as shown in FIG. A shrinkage suppression layer 15A is formed.

  According to the present embodiment, since the green sheet laminate is fired by interposing a plurality of shrinkage suppression layers in the green sheet laminate, each ceramic layer is evenly distributed from the surface to the center of the green sheet laminate during firing. The shrinkage in the surface direction can be suppressed, cracks inside the substrate can be prevented, and warping of the substrate can be prevented.

Example 1
In this embodiment, as shown in FIG. 7, a plurality of chip-shaped ceramic multilayer components 112 are built in the interface between the upper and lower ceramic green sheets 111A and 111A to produce a ceramic multilayer substrate. The variation of values was verified.

[Production of ceramic multilayer substrate]
In order to fabricate a ceramic multilayer substrate, first, a slurry containing a low-temperature sintered ceramic material (Al ₂ O ₃ is used as a filler and borosilicate glass is used as a sintering aid) is applied on a carrier film. As shown, a plurality of 200 mm □ ceramic green sheets 111A having a thickness after firing of 50 μm were prepared. A via hole (not shown) was formed by laser processing on one ceramic green sheet 111A, and a conductive paste mainly composed of Ag powder was filled in the via hole to form a via conductor portion (not shown). . The same conductive paste was screen printed on the ceramic green sheet 111A to form the in-plane conductor portion 113A with a predetermined pattern. The ceramic green sheet 111A has a size capable of producing 400 10 mm □ sub-substrates.

  Next, an organic adhesive is applied on a predetermined ceramic green sheet 111A using a spray to form an organic adhesive layer on the in-plane conductor portion 113A, and then prepared in advance as a chip-shaped ceramic laminated component using a mounter. The laminated multilayer ceramic capacitor 112 was mounted on the ceramic green sheet 111A, and was bonded and fixed to the in-plane conductor portion 113A. When the ceramic green sheets 111A are divided into 10 mm □ sub-boards, 10 multilayer ceramic capacitors 112 are arranged in a total of 4000 pieces per sub-board. At this time, the dielectric ceramic layer of the multilayer ceramic capacitor 112 was arranged so as to be parallel to the surface of the ceramic green sheet 111A. This multilayer ceramic capacitor 112 is made of a ceramic sintered body (size: 0.6 mm × 0.3 mm × 0.3 mm, internal electrode: Pd, capacity standard: 80 pF) fired at 1300 ° C., and Ag is applied to both ends thereof. An external terminal electrode portion is formed by applying and baking a conductive paste as a main component. The external terminal electrode is not plated.

Thereafter, ten ceramic green sheets 111A were laminated to produce a green sheet laminate 111. At this time, the ceramic green sheet 111A on which the multilayer ceramic capacitor 112 was mounted was disposed 100 μm (thickness after firing) from the upper surface of the green sheet multilayer body 111, that is, the third layer from the upper surface. A shrinkage suppression layer 115 containing Al ₂ O ₃ as a main component was laminated on the upper and lower sides of the green sheet laminate 111 and temporarily bonded. The pressure during temporary pressure bonding is preferably 10 MPa or more. If this pressure is less than 10 MPa, the upper and lower ceramic green sheets are not sufficiently pressed together and there is a risk of delamination.

  After the temporary pressure bonding, a predetermined pressure was applied to perform the main pressure bonding to produce a pressure bonded body 110 shown in FIG. The pressure during the main pressure bonding is preferably 20 MPa or more and 250 MPa or less. If the pressure during the main pressure bonding is less than 20 MPa, the pressure bonding is insufficient, and there is a risk of delamination during firing. If the pressure exceeds 250 MPa, the multilayer ceramic capacitor 112 may be damaged or the internal conductor pattern 113 may be disconnected. There is. Next, after firing the pressure-bonded body 110 in an air atmosphere at 870 ° C. and removing the shrinkage suppression layer 115, the obtained sintered body is divided into sub-substrates by dicing to obtain a ceramic multilayer substrate of this example. It was. The thickness of this ceramic multilayer substrate was 0.5 mm.

Comparative Example 1
In this comparative example, two monolithic ceramic capacitors were built in the layers of 50 μm, 100 μm, 150 μm, 200 μm, and 250 μm from the surface of the ceramic multilayer substrate, and 10 (= 2 × 5 layers) per child substrate. Except for the above, a ceramic multilayer substrate was produced in the same manner as in Example 1.

[Evaluation of ceramic multilayer substrate]
Using the LCR meter, the capacitance values of the multilayer ceramic capacitors 12 incorporated in the ceramic multilayer substrates of Example 1 and Comparative Example 1 were measured at a frequency of 1 MHz, and the variation in the capacitance values based on the measurement results. The results are shown in Table 1.

  According to the results shown in Table 1, in the case of the ceramic multilayer substrate of Example 1, the variation in capacitance value between the multilayer ceramic capacitors was 4.0%. On the other hand, in the case of the ceramic multilayer substrate of Comparative Example 1, the variation in the capacitance value between the multilayer ceramic capacitors was 5.1%. From this result, it was found that variation in capacitance values among the multilayer ceramic capacitors can be suppressed by aligning the depths of the multilayer ceramic capacitors from the surface of the ceramic multilayer substrate. In other words, it has been found that the stress applied to the multilayer ceramic capacitor when the ceramic multilayer substrate contracts varies depending on the depth from the surface.

Example 2
In this example, the ceramic multilayer substrate produced in Example 1 was prepared as the ceramic multilayer substrate of this example.

Comparative Example 2
In this comparative example, the ceramic directions were the same as in Example 1 except that the surface directions of the dielectric ceramic layers of the plurality of multilayer ceramic capacitors were not specified and each surface direction was random and incorporated in the ceramic laminate. A multilayer substrate was produced.

  Then, the capacitance value of each multilayer ceramic capacitor incorporated in each of the ceramic multilayer substrates of Example 2 and Comparative Example 2 is measured in the same manner as in Example 1, and the variation in the capacitance value is calculated based on this measurement result. The results are shown in Table 2.

  According to the results shown in Table 2, in the case of the ceramic multilayer substrate of Example 2, the variation in capacitance value between the multilayer ceramic capacitors was 4.0%. On the other hand, in the case of the ceramic multilayer substrate of Comparative Example 2, the variation in capacitance value between the multilayer ceramic capacitors was 4.7%. From this result, the multilayer ceramic capacitors are arranged at the same depth from the surface of the ceramic multilayer substrate, and the dielectric ceramic layers of the multilayer ceramic capacitor are arranged in parallel to the surface direction of the ceramic multilayer body. It was found that variation in the capacitance value between capacitors can be suppressed. In other words, even if a plurality of multilayer ceramic capacitors are arranged at the same depth from the surface of the ceramic multilayer substrate, the direction of the surface direction of the dielectric ceramic layer of each multilayer ceramic capacitor is the surface direction of the ceramic multilayer body. It was found that the variation in the capacitance value between the multilayer ceramic capacitors would be large if they were not parallel to each other.

Example 3
In this example, as shown in FIG. 8, a ceramic multilayer substrate was produced in the same manner as in Example 1 except that multilayer ceramic capacitors were arranged at two interfaces at the same distance from the upper and lower surfaces of the ceramic multilayer substrate.

  In this embodiment, as shown in FIG. 8, multilayer ceramic capacitors 112 are respectively formed on the ceramic green sheet 111A located at a depth of 100 μm from the lower surface and on the ceramic green sheet 111A located at a depth of 100 μm from the upper surface. A green sheet laminate 111 was produced by arranging the same number as in Example 1, and a ceramic multilayer substrate was produced using the green sheet laminate 111 together with the shrinkage suppression layer 115 in the same manner as in Example 1. Then, the capacitance value of each multilayer ceramic capacitor was measured in the same manner as in Example 1, and the variation in the capacitance value was calculated based on the measurement result. The result is shown in Table 3. As Reference Example 1, the ceramic multilayer substrate produced in Example 1 was used.

  According to the results shown in Table 3, since the multilayer ceramic capacitors are arranged at the same depth from the upper and lower surfaces of the ceramic multilayer substrate, all the multilayer ceramic capacitors exhibit the same variation in capacitance value. It turns out that it is almost the same as one. From this result, even if the multilayer ceramic capacitors are built in two layers, if the respective multilayer ceramic capacitors are arranged at the same depth from the upper and lower surfaces of the ceramic multilayer substrate, it is possible to suppress variation in the respective capacitance values. I understood.

Example 4
In this example, the ceramic multilayer substrate produced in Example 1 was prepared as the ceramic multilayer substrate of this example. And it was investigated by X-ray flaw detection method whether the multilayer ceramic capacitor in this ceramic multilayer substrate had cracked, and the result was shown in Table 4.

Comparative Example 3
In this comparative example, the ceramic multilayer substrate is formed in the same manner as in Example 1 except that the multilayer ceramic capacitor is arranged on the ceramic green sheet so that the dielectric ceramic layer of the multilayer ceramic capacitor is perpendicular to the surface of the ceramic green sheet. Was made. Whether or not cracks have occurred in the multilayer ceramic capacitor in the ceramic multilayer substrate was examined by X-ray flaw detection, and the results are shown in Table 4.

  According to the results shown in Table 4, no cracks were observed in the multilayer ceramic capacitor in the ceramic multilayer substrate of Example 4. On the other hand, cracks were observed in 25 out of 4000 multilayer ceramic capacitors of the multilayer ceramic capacitor of Comparative Example 3. From this result, it was found that the multilayer ceramic capacitor is resistant to stress acting in a direction perpendicular to the dielectric ceramic layer, but weak to stress acting in parallel with the dielectric ceramic layer. Therefore, it is understood that the multilayer ceramic capacitor can prevent the occurrence of cracks due to the stress applied when the green sheet laminate is pressed and fired by arranging the dielectric ceramic layer in parallel with the ceramic layer of the ceramic multilayer substrate. It was.

Example 5
In this example, a ceramic multilayer substrate was produced in the same manner as in Example 1 except that the pressure-bonded body 110 was fired while being pressed as shown in FIG. That is, as shown in the figure, the porous ceramic setter 200 is arranged above and below the pressure-bonding body 110, and these three members are stacked. Obtained a ceramic multilayer substrate in the same manner as in Example 1. The pressure when performing pressure firing is preferably 0.1 MPa or more. In addition, by using the porous ceramic setter 200, degreasing during firing can be performed reliably.

  According to the present embodiment, planarization of the ceramic multilayer substrate can be promoted by applying pressure during firing. Further, in this embodiment, the case where the pressure-bonding body 110 is provided in a single stage and fired has been described, but a similar pressure-bonding body 110 may be laminated and fired over a plurality of stages.

Example 6
In this example, Cu is used as the internal conductor pattern, and as the multilayer ceramic capacitor, the external terminal electrode is Cu, the size is 1.6 mm × 0.8 mm × 0.3 mm, the internal electrode is Ni, the firing temperature is 1200 ° C., the capacity A pressure-bonded body was prepared in the same manner as in Example 1 except that a multilayer ceramic capacitor having a value of 0.1 μF was used, and was fired under three conditions of 1000 ° C., 1050 ° C., and 1080 ° C. With respect to the ceramic multilayer substrate obtained at each firing temperature, a DC voltage of 25 V was applied to the external terminal electrode, and the reliability was evaluated in an environment at a temperature of 75 ° C. and a relative humidity of 95%. Indicated.

  According to the results shown in Table 5, the ceramic multilayer substrate fired at 1050 ° C. or higher had a decrease in the insulation resistance of the multilayer ceramic capacitor over time, but the insulation of the multilayer ceramic capacitor of the ceramic multilayer substrate fired at 1000 ° C. The resistance was found to be stable over time. From this result, it was found that the ceramic multilayer substrate is preferably fired at 1000 ° C. or lower. Even when baked at 1050 ° C., the insulation resistance only slightly decreased with time, and it was found that there was no practical problem.

Example 7
In this embodiment, a through hole corresponding to the size of the multilayer ceramic capacitor is provided in the ceramic green sheet by punching, and the multilayer ceramic capacitor is accommodated in the through hole, and the multilayer ceramic capacitor is built in the same depth as in the first embodiment. A ceramic multilayer substrate was produced in the same manner as in Example 1 except that the above was performed.

  Then, the capacitance value of each multilayer ceramic capacitor in the ceramic multilayer substrate was measured at 1 MHz using an LCR meter, and the variation in the capacitance value was calculated based on this measurement result. The results are shown in Table 6. Further, as Reference Example 2, variation in the capacitance value of the multilayer ceramic capacitor of Example 1 is shown.

  According to the results shown in Table 6, it was found that in the ceramic multilayer substrate of Example 6, the variation in the capacitance value of the multilayer ceramic capacitor was suppressed more than that in Reference Example 2. From this result, it was found that the stress applied to the multilayer ceramic capacitor when the ceramic multilayer substrate is manufactured is reduced by housing the multilayer ceramic capacitor in the through hole.

  In addition, this invention is not restrict | limited to each said embodiment at all, and unless it contradicts the meaning of this invention, it is contained in this invention.

  INDUSTRIAL APPLICABILITY The present invention can be suitably used for a ceramic multilayer substrate used for electronic devices and the manufacturing method thereof.

(A), (b) is a figure which shows one Embodiment of the ceramic multilayer substrate of this invention, respectively, (a) is sectional drawing which shows the whole, (b) is a cross section which expands and shows the principal part of (a). FIG. It is process drawing which shows the principal part of the manufacturing process of the ceramic multilayer substrate shown in FIG. It is a figure which shows the post process of the manufacturing process of the ceramic multilayer substrate shown in FIG. (A), (b) is the figure which expands and shows the principal part of other embodiment of the ceramic multilayer substrate of this invention, respectively, (a) is the sectional drawing, (b) is chip shape shown to (a) It is sectional drawing which shows the process at the time of incorporating a ceramic laminated component. It is sectional drawing which expands and shows the principal part of other embodiment of the ceramic multilayer substrate of this invention. It is sectional drawing which expands and shows the principal part of other embodiment of the ceramic multilayer substrate of this invention. It is sectional drawing which shows the principal part of the manufacturing process of one Example of this invention. It is sectional drawing which shows the principal part of the manufacturing process of the other Example of this invention. It is sectional drawing which shows the principal part of the manufacturing process of the further another Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Ceramic multilayer substrate 11 Ceramic laminated body 11A Ceramic layer 12, 112 Chip-shaped ceramic laminated component 12A, 112A External terminal electrode 12B Dielectric ceramic layer 13 Internal conductor pattern 13A In-plane conductor 13B Via conductor 13D Step part (connection step part)
15, 15A Shrinkage suppression layer 16 Connection conductor 16A First connection conductor 16B Second connection conductor 111 Green sheet laminate 111A Ceramic green sheet 113 Internal conductor pattern portion 113A In-plane conductor portion 113B Via conductor portion 116A First connection conductor portion 116B First 2 connecting conductor

Claims (12)

A ceramic sintered body formed by laminating a plurality of dielectric ceramic layers on the surface of a ceramic green sheet is used as a base, and a chip-shaped ceramic multilayer component having internal electrodes between the dielectric ceramic layers is formed as the dielectric ceramic. A step of arranging a plurality of layers so that the interface of the layers is parallel to the surface of the ceramic green sheet;
Laminating the ceramic green sheet in which the plurality of chip-shaped ceramic multilayer components are arranged together with other ceramic green sheets, and producing a green sheet laminate including the plurality of chip-shaped ceramic multilayer components;
And firing the green sheet laminate.
The production process of the green sheet laminate is as follows:
Forming first and second connection conductor portions on the upper and lower ceramic green sheets sandwiching the chip-shaped ceramic multilayer component; and
By disposing the chip-shaped ceramic multilayer component between the upper and lower ceramic green sheets and press-bonding these ceramic green sheets, the first connecting conductor portion is moved in one direction from the interface between the upper and lower ceramic green sheets. The second connecting conductor portion extends along the end surface of the chip-shaped ceramic multilayer component and extends along the end surface of the chip-shaped ceramic multilayer component in the direction opposite to the first connecting conductor portion from the interface. And a step of connecting the second connection conductor portion to the terminal electrode of the chip-shaped ceramic multilayer component . A ceramic ceramic sintered body formed by laminating a plurality of dielectric ceramic layers on the surface of a ceramic green sheet is used as a base, and a chip-shaped ceramic multilayer component having internal electrodes between the dielectric ceramic layers is formed as the dielectric ceramic. A step of arranging a plurality of layers so that the interface of the layers is parallel to the surface of the ceramic green sheet;
Laminating the ceramic green sheet on which the plurality of chip-shaped ceramic multilayer components are arranged together with other ceramic green sheets, and producing a green sheet laminate including the plurality of chip-shaped ceramic multilayer components;
And firing the green sheet laminate.
The production process of the green sheet laminate is as follows:
Directly connecting the terminal electrode of the chip-shaped ceramic multilayer component to the via conductor provided in the ceramic green sheet;
And a step of applying a pressure to the chip-shaped ceramic multilayer component to form a connection step portion with the chip-shaped ceramic multilayer component in the via conductor portion . 3. The ceramic according to claim 1, wherein the chip-shaped ceramic multilayer component has a thickness A and a length B in the longitudinal direction satisfy a relationship of 2 ≦ (B / A) ≦ 40. A method for producing a multilayer substrate. A step of disposing a shrinkage suppression layer mainly composed of ceramic that is not substantially sintered at the sintering temperature of the ceramic green sheet on at least one main surface of the green sheet laminate;
Firing both of these at the sintering temperature of the ceramic green sheet,
Removing the shrinkage suppression layer;
The method for producing a ceramic multilayer substrate according to any one of claims 1 to 3, wherein the ceramic multilayer substrate is provided. The method for producing a ceramic multilayer substrate according to any one of claims 1 to 4, wherein in the firing step, the green sheet laminate is fired while being pressurized. In the green sheet laminate manufacturing step, a shrinkage suppression layer mainly composed of a ceramic material that does not substantially sinter at the sintering temperature of the ceramic green sheet is disposed inside the green sheet laminate,
The firing step of the green sheet laminate, any one of claims 1 to 5, characterized in that firing the green sheet laminate provided with the shrinkage inhibiting layer at the sintering temperature of the ceramic green sheet A method for producing a ceramic multilayer substrate as described in 1. above. 7. The manufacturing process of the green sheet laminate, wherein a plurality of the same type of chip-shaped ceramic laminate parts are arranged at the same interface inside the green sheet laminate . 2. A method for producing a ceramic multilayer substrate according to item 1 . The method for producing a ceramic multilayer substrate according to any one of claims 1 to 7 , wherein a low-temperature sintered ceramic green sheet mainly composed of a low-temperature sintered ceramic material is used as the ceramic green sheet. . A ceramic multilayer substrate comprising: a ceramic laminate formed by laminating a plurality of ceramic layers; and a plurality of chip-like ceramic laminate components provided at an interface between upper and lower ceramic layers in the ceramic laminate,
The chip-shaped ceramic multilayer component includes a ceramic sintered body formed by laminating a plurality of dielectric ceramic layers, and an internal electrode formed between the dielectric ceramic layers.
The plurality of chip-shaped ceramic multilayer parts are provided at the same interface with the dielectric ceramic layers parallel to the ceramic layers, and are formed at the ends in the direction orthogonal to the ceramic layers. The terminal electrode is electrically connected to the connection conductor formed in the ceramic laminate,
The connection conductor extends from the interface in one direction along the terminal electrode of the chip-shaped ceramic multilayer component, and extends from the interface along the terminal electrode in a direction opposite to the first connection conductor. A second connecting conductor
A ceramic multilayer substrate characterized by that. A ceramic laminate in which a plurality of ceramic layers are laminated, a ceramic multilayer substrate having a chip-like ceramic multilayer part provided plurality, the the interface of the ceramic laminate of the upper and lower ceramic layers,
The chip-shaped ceramic laminated components have a internal electrodes in which a plurality of dielectric ceramic layers are formed between layers of the ceramic sintered body obtained by laminating the body and the dielectric ceramic layers,
The plurality of chip-shaped ceramic multilayer parts are provided at the same interface with the dielectric ceramic layers parallel to the ceramic layers, and are formed at the ends in the direction orthogonal to the ceramic layers. The terminal electrode is electrically connected directly to the via conductor formed in the ceramic laminate,
The ceramic multilayer substrate , wherein the connection portion of the via conductor with the terminal electrode is formed as a connection step portion in which the terminal electrode is cut from the upper surface of the via conductor . 11. The ceramic according to claim 9, wherein the chip-shaped ceramic laminated component has a thickness A and a longitudinal length B satisfying a relationship of 2 ≦ (B / A) ≦ 40. Multilayer board. It said multiple field surface of the ceramic laminate portion, a plurality of ceramic multi-layer substrate according to any one of claims 9 to 11, characterized in that the chip-shaped ceramic laminate device is incorporated.

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