JP2003037022A - Laminated electronic component - Google Patents

Laminated electronic component

Info

Publication number
JP2003037022A
JP2003037022A JP2001222749A JP2001222749A JP2003037022A JP 2003037022 A JP2003037022 A JP 2003037022A JP 2001222749 A JP2001222749 A JP 2001222749A JP 2001222749 A JP2001222749 A JP 2001222749A JP 2003037022 A JP2003037022 A JP 2003037022A
Authority
JP
Japan
Prior art keywords
layer
laminated
dielectric
electronic component
magnetic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001222749A
Other languages
Japanese (ja)
Other versions
JP4612970B2 (en
Inventor
Yukihiro Noro
幸広 野呂
Yukio Isowaki
幸夫 磯脇
Yoshiaki Naruo
良明 成尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soshin Electric Co Ltd
Original Assignee
Soshin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soshin Electric Co Ltd filed Critical Soshin Electric Co Ltd
Priority to JP2001222749A priority Critical patent/JP4612970B2/en
Publication of JP2003037022A publication Critical patent/JP2003037022A/en
Application granted granted Critical
Publication of JP4612970B2 publication Critical patent/JP4612970B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Coils Or Transformers For Communication (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Filters And Equalizers (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent bending, delamination, and occurrence of cracks in a product without using a sandwich structure in a laminated electronic component in which material layers of different kinds are bonded and integrally sintered. SOLUTION: A dielectric layer incorporating a conductor layer and a magnet layer incorporating a conductor layer are laminated, and a layer that is made of the same material as the dielectric layer or the magnet layer but does not incorporate a conductor layer is laminated on one surface or both surfaces of the laminate so that the dielectric layer and the magnet layer are alternately bonded. Furthermore, a bonding layer is laminated between the dielectric layer and the magnet layer, and a layer that is made of the same material as that of the bonding layer but does not incorporate a conductor layer further is bonded on the outer surface of the magnet layer. Furthermore, a glass is contained in any of the layers made of a dielectric material.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明が属する技術分野】本発明は、磁性体あるいは誘
電体などの絶縁体と、導体あるいは抵抗体などの異種材
料層からなる積層電子部品に係わり、特に積層複合イン
ダクタと積層複合キャパシタを積層したLCフィルタ
や、さらには上層にチップ部品搭載層および、その下層
に配線層を積層した混成集積回路基板を含む、一体燒結
された積層電子部品に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated electronic component including an insulator such as a magnetic substance or a dielectric substance and a different material layer such as a conductor or a resistor, and particularly, a laminated composite inductor and a laminated composite capacitor. The present invention relates to an integrally sintered laminated electronic component including an LC filter and a hybrid integrated circuit board in which a chip component mounting layer is laminated on the upper layer and a wiring layer is laminated on the lower layer.

【0002】[0002]

【従来の技術】近年、電子機器の小型化の要求に伴い、
それを構成する電子部品の複合化、軽薄短小化が進めら
れている。たとえば誘電率の大きいコンデンサ層と、誘
電率の小さい配線層を積層したものや、磁性体層に形成
したインダクタと誘電体層に形成したコンデンサ層を一
体的に燒結したチップ形状のLCフィルタなどが用いら
れている。
2. Description of the Related Art In recent years, with the demand for miniaturization of electronic devices,
The electronic components that compose it are becoming more complex, lighter, thinner and smaller. For example, a capacitor layer having a high dielectric constant and a wiring layer having a low dielectric constant are laminated, and a chip-shaped LC filter in which an inductor formed in a magnetic layer and a capacitor layer formed in a dielectric layer are integrally sintered is used. It is used.

【0003】このようなLCフィルタは、以下のように
形成されている。すなわち、任意数のコイル導体を印刷
した磁性体グリーンシートを、ビアホール接続するよう
積層したインダクタ層と、任意数のコンデンサ電極を印
刷した誘電体グリーンシートを積層したコンデンサ層
を、重ねあわせて加圧して圧着させ、個片に切断後に焼
成して一体燒結させ、外面に端子電極を焼きつけてチッ
プ形状のLCフィルタを形成する。 このとき、コイル
導体およびコンデンサ電極は、導電性の良い銀ペースト
を用いることが好ましいため銀の融点以下で焼成する磁
性体グリーンシートと誘電体グリーンシートが用いられ
る。
Such an LC filter is formed as follows. That is, an inductor layer in which a magnetic green sheet with an arbitrary number of coil conductors printed is connected to form a via hole connection, and a capacitor layer with a dielectric green sheet in which an arbitrary number of capacitor electrodes are printed are stacked and pressed. Then, they are pressure-bonded, cut into individual pieces, baked and integrally sintered, and terminal electrodes are baked on the outer surface to form a chip-shaped LC filter. At this time, since it is preferable to use a silver paste having good conductivity for the coil conductor and the capacitor electrode, a magnetic green sheet and a dielectric green sheet which are fired at a melting point of silver or less are used.

【0004】しかしながら、第一に、磁性体層と誘電体
層の燒結収縮率と、熱膨張率を近似させることは困難な
ため、燒結後の製品に図7に示すようなクラック7や、
デラミネーション8や、反りが発生し、第二に、各材料
層と接合層やダミー層の界面において反応層が形成され
る場合に、この反応層部分の焼結収縮率と熱膨張率が変
化して、クラックやデラミネーションや反りが発生した
りしていた。対策として図8に示すように磁性体層2と
誘電体層1の中間に両者の平均的な燒結収縮率および熱
膨張率を有する接合層4を介在させる構造や、図5に示
すように、磁性体層2を誘電体層1で挟んだサンドイッ
チ構造などが用いられていた。
However, first, since it is difficult to approximate the rate of thermal expansion and the rate of thermal contraction between the magnetic layer and the dielectric layer, cracks 7 as shown in FIG.
When delamination 8 or warpage occurs, and secondly, when a reaction layer is formed at the interface between each material layer and the bonding layer or the dummy layer, the sintering shrinkage rate and the thermal expansion rate of this reaction layer portion change. Then, cracks, delamination, and warpage occurred. As a countermeasure, as shown in FIG. 8, a structure in which a bonding layer 4 having an average sintered shrinkage ratio and a thermal expansion coefficient between the magnetic layer 2 and the dielectric layer 1 is interposed, or as shown in FIG. A sandwich structure in which the magnetic layer 2 is sandwiched between the dielectric layers 1 has been used.

【0005】図5に示す構造では、図9の断面図に示す
ように上下の誘電体層のコンデンサ電極9を接続させる
ために、コンデンサの数が少ない構成の製品は側面の外
部電極(図示せず)を設けて中継することもできるが、
コンデンサの数が多い構成の製品は、中間の磁性体層2
にビア11を設けて中継させる必要があり、そのため磁
性体層の各層にスルーホールの打ち抜きと、該スルーホ
ールへの銀ペーストの刷り込みが必要であった。さら
に、中間の磁性体層2はビアの数に比例して各層の実効
面積が減少してコイル電極の配置が制限されるので、各
層の面積を広げるか、または実効面積が減少した分は積
層数を増やして製品の厚みを厚くせざるを得ないため、
形状が大きくなると共にコストアップとなっていた。
In the structure shown in FIG. 5, in order to connect the capacitor electrodes 9 of the upper and lower dielectric layers as shown in the sectional view of FIG. It is also possible to provide a relay)
Products with a large number of capacitors have an intermediate magnetic layer 2
Therefore, it is necessary to provide vias 11 for relaying, and therefore it is necessary to punch through holes in each layer of the magnetic material layer and imprint silver paste into the through holes. Further, in the intermediate magnetic layer 2, the effective area of each layer is reduced in proportion to the number of vias and the arrangement of the coil electrodes is limited. Therefore, the area of each layer is widened or the reduced effective area is laminated. Because we have to increase the number and increase the thickness of the product,
The size was large and the cost was high.

【0006】[0006]

【発明が解決しようとする課題】本発明の目的は、異種
材料層を接合させ一体燒結させた積層電子部品におい
て、製品の反りや、デラミネーション、およびクラック
の発生を押さえ、かつ前述したような、サンドイッチ構
造の場合に、側面での外部電極による接続または上下層
の接続をなくしてコスト低減を図るものである。
SUMMARY OF THE INVENTION An object of the present invention is to suppress the occurrence of product warpage, delamination, and cracks in a laminated electronic component in which different material layers are joined and integrally sintered, and as described above. In the case of the sandwich structure, the cost is reduced by eliminating the connection by the external electrodes or the connection of the upper and lower layers on the side surface.

【0007】[0007]

【課題を解決するための手段】本発明は、異種材料層か
らなる積層電子部品において、導体層を内蔵する誘電体
層と、導体層を内蔵する磁性体層を積層し、積層体上下
面の少なくとも1面に、前記誘電体層あるいは磁性体と
同一材料よりなる、導体層を内蔵しないダミー層を積層
して燒成し、誘電体層と磁性体層を交互に接合させる。
According to the present invention, in a laminated electronic component made of different material layers, a dielectric layer containing a conductor layer and a magnetic layer containing a conductor layer are laminated, and the upper and lower surfaces of the laminate are laminated. At least one surface is laminated with a dummy layer made of the same material as the dielectric layer or the magnetic material and not containing a conductor layer and fired to bond the dielectric layers and the magnetic layers alternately.

【0008】図1の本発明による説明用の積層電子部品
の側面図に示すように、導体層を内蔵する誘電体層1
と、導体層を内蔵する磁性体層2を積層し、さらに前記
誘電体層と同一材料からなる導体層を内蔵しないダミー
層3を、前記磁性体層の下面に積層し燒結させる。 さ
らに、誘電体層1および磁性体層2の界面の両層に反応
層が形成される場合には、図2に示すように上面に磁性
体層2と同一材料よりなる、導体層を内蔵しないダミー
層3を誘電体層の上部に配置し誘電体層と磁性体層を交
互に接合させる。
As shown in the side view of the illustrative laminated electronic component according to the invention in FIG. 1, a dielectric layer 1 containing a conductor layer.
Then, a magnetic layer 2 containing a conductor layer is laminated, and a dummy layer 3 made of the same material as the dielectric layer and not containing a conductor layer is laminated on the lower surface of the magnetic layer and sintered. Further, when the reaction layers are formed on both layers of the interface between the dielectric layer 1 and the magnetic layer 2, as shown in FIG. 2, the conductor layer made of the same material as the magnetic layer 2 is not built in on the upper surface. The dummy layer 3 is disposed on the dielectric layer and the dielectric layers and the magnetic layers are alternately joined.

【0009】燒結時において、導体層を内蔵する誘電体
層と、導体層を内蔵する磁性体層の接合面にできる反応
層の熱収縮挙動の差、あるいは熱膨張係数の差に起因す
る応力は、積層体上下面の少なくとも1面にダミー層を
設けることにより反応層を形成させ、前記反応層の応力
と互いに平衡させることにより、反り、デラミネーショ
ン、およびクラックの発生を防止する。
At the time of sintering, the stress due to the difference in the thermal contraction behavior or the difference in the coefficient of thermal expansion between the reaction layer formed at the joint surface between the dielectric layer containing the conductor layer and the magnetic layer containing the conductor layer is By providing a dummy layer on at least one of the upper and lower surfaces of the laminate to form a reaction layer and balance the stress of the reaction layer with each other, warpage, delamination, and crack generation are prevented.

【0010】また本発明は、異種材料層からなる積層電
子部品において、導体層を内蔵する誘電体層と導体層を
内蔵する磁性体層との中間に接合層を介して積層し、さ
らに積層体上下面の少なくとも1面に、接合層と同一材
料で導体層を内蔵しないダミー層を接合してなることを
特徴とする。
Further, according to the present invention, in a laminated electronic component made of different material layers, a dielectric layer containing a conductor layer and a magnetic layer containing a conductor layer are laminated in the middle with a bonding layer, and a laminate is further formed. It is characterized in that a dummy layer made of the same material as the bonding layer and having no conductor layer is bonded to at least one of the upper and lower surfaces.

【0011】焼成収縮挙動の差、熱膨張係数の差が大き
い異種材料どうしの接合には、図3あるいは図4に示す
ように、導体層を内蔵する誘電体層1と、導体層を内蔵
する磁性体層2の間に、両者の熱収縮挙動、あるいは熱
膨張係数の平均的な値を有する接合層4を介して積層
し、さらに前記接合層と同一材料からなる、導体層を内
蔵しないダミー層3を積層体の片面あるいは上下両面に
接合する。この積層体の上面ダミー層の表面にチップ部
品の搭載パターンを形成することができ、また、下面ダ
ミー層の表面に端子電極を形成しても良い。
As shown in FIG. 3 or FIG. 4, a dielectric layer 1 containing a conductor layer and a conductor layer are built in for joining different materials having large differences in firing shrinkage behavior and thermal expansion coefficients. A dummy which is laminated between magnetic layers 2 via a bonding layer 4 having an average value of thermal contraction behavior or thermal expansion coefficient of both, and which is made of the same material as the bonding layer and does not include a conductor layer. The layer 3 is bonded to one side or both upper and lower sides of the laminate. A mounting pattern of chip components can be formed on the surface of the upper dummy layer of this laminated body, and a terminal electrode may be formed on the surface of the lower dummy layer.

【0012】図3によれば、接合層4と磁性体層2の界
面に反応層が形成された場合には磁性体層2下面に接合
層4と同一材料のダミー層を形成する。また、図4によ
れば、さらに誘電体層1と接合層4の界面に反応層が形
成された場合には誘電体層1上面に接合層4と同一材料
のダミー層を形成する。異種材料間の焼成収縮挙動ある
いは熱膨張係数の差による応力を緩和し、さらに積層体
の外面ダミー層との反応層で前記応力と平衡させること
ができ、反り、デラミネーション、クラックの発生を押
さえることができる。
According to FIG. 3, when a reaction layer is formed at the interface between the bonding layer 4 and the magnetic layer 2, a dummy layer made of the same material as the bonding layer 4 is formed on the lower surface of the magnetic layer 2. Further, according to FIG. 4, when a reaction layer is further formed at the interface between the dielectric layer 1 and the bonding layer 4, a dummy layer of the same material as the bonding layer 4 is formed on the upper surface of the dielectric layer 1. Stress due to difference in firing shrinkage behavior or thermal expansion coefficient between dissimilar materials can be relaxed, and the stress can be balanced in the reaction layer with the outer dummy layer of the laminated body, suppressing warpage, delamination and crack generation. be able to.

【0013】また本発明は、前記の積層電子部品におい
て、誘電体層および接合層および誘電体層と同一材料で
導体層を内蔵しないダミー層にガラスを含有することを
特徴とする。
Further, the present invention is characterized in that, in the above-mentioned laminated electronic component, glass is contained in a dummy layer which is the same material as the dielectric layer, the bonding layer and the dielectric layer and does not contain a conductor layer.

【0014】前記の積層電子部品において、誘電体層お
よび接合層および誘電体層と同一材料で導体層を内蔵し
ないダミー層にガラスを含有させることにより、燒結温
度を下げることができ、銀の融点以下の低温焼成が可能
となる。
In the above-mentioned laminated electronic component, the sintering temperature can be lowered and the melting point of silver can be lowered by containing glass in the dummy layer which is made of the same material as the dielectric layer, the bonding layer and the dielectric layer and does not contain the conductor layer. The following low temperature firing becomes possible.

【0015】[0015]

【発明の実施の形態】異種材料層からなる積層電子部品
において、導体層を内蔵する誘電体層と、導体層を内蔵
する磁性体層を積層し、積層体の片面あるいは両面に、
前記誘電体層あるいは磁性体と同一材料で導体層を内蔵
しない層を積層し、誘電体層と磁性体層を交互に接合さ
せる。
BEST MODE FOR CARRYING OUT THE INVENTION In a laminated electronic component composed of different material layers, a dielectric layer containing a conductor layer and a magnetic layer containing a conductor layer are laminated, and one side or both sides of the laminate are
Layers made of the same material as the dielectric layer or the magnetic material and not containing a conductor layer are laminated, and the dielectric layers and the magnetic layers are alternately joined.

【0016】また、前記誘電体層と磁性体層との中間に
接合層を介して積層し、さらに積層体上下面の少なくと
も1面に、接合層と同一材料で導体層を内蔵しないダミ
ー層を、誘電体層と磁性体層が交互になるよう積層し焼
成して燒結させる。さらに、誘電体層および接合層にガ
ラスを含有させる。
In addition, a dummy layer, which is made of the same material as the bonding layer and does not contain a conductor layer, is laminated on at least one of the upper and lower surfaces of the laminated body in the middle of the dielectric layer and the magnetic layer via the bonding layer. , The dielectric layers and the magnetic layers are alternately laminated, fired and sintered. Further, glass is contained in the dielectric layer and the bonding layer.

【0017】[0017]

【実施例1】磁性体層としてFe2O3 48mol
%、NiO 6mol%、CuO 10mol%、Zn
O 36mol%からなるNi−Cu−Znフェライ
ト、誘電体層としてBaO 12mol%、TiO2
55mol%、ZnO 33mol%からなるチタン酸
系複合酸化物誘電体材料にホウ珪酸亜鉛ガラスを3wt
%添加した材料にそれぞれバインダー、可塑材、溶剤を
加えて混練しスリップを用意した。
Example 1 Fe2O3 48 mol as a magnetic layer
%, NiO 6 mol%, CuO 10 mol%, Zn
Ni-Cu-Zn ferrite composed of O 36 mol%, BaO 12 mol% as a dielectric layer, TiO2
3 wt% of zinc borosilicate glass is added to the titanic acid-based composite oxide dielectric material consisting of 55 mol% and ZnO 33 mol%
%, A binder, a plasticizer and a solvent were added to each of the added materials and kneaded to prepare slips.

【0018】次に、それぞれのスリップをドクターブレ
ード法で、厚さ100μmのグリーンシートに成形し
た。つぎに得られたグリーンシートのそれぞれを、必要
に応じてビア形成用のスルーホールと共に10cm角の
シートに打ち抜き、LCフィルタを構成するべく、誘電
体シートには複数のコンデンサ電極を、磁性体シートに
は複数のコイル形成パターンに銀ペーストを用いて印刷
し多数個取りのシートを得た。
Next, each slip was formed into a green sheet having a thickness of 100 μm by the doctor blade method. Next, each of the obtained green sheets is punched out into a 10 cm square sheet together with a through hole for forming a via if necessary, so that a plurality of capacitor electrodes are provided on the dielectric sheet and a magnetic sheet to form an LC filter. A plurality of coil forming patterns were printed with silver paste to obtain a multi-cavity sheet.

【0019】ついで、図1の構造に示すダミー層3に前
記誘電体グリーンシートを1枚、磁性体層2にコイルを
形成するように積層された磁性体グリーンシートを18
枚、誘電体層1にコンデンサを形成するように積層され
た誘電体グリーンシートを14枚、順に積層し圧着積層
体を得た。次に燒結後製品が5mm角になるよう収縮率
を見込んで切断、脱脂後900℃で3時間焼成し製品化
した。同時に、上記のダミー層を配設しない従来品を同
数作成した。
Then, one of the dielectric green sheets is formed on the dummy layer 3 shown in the structure of FIG. 1, and the magnetic green sheet 18 is laminated on the magnetic layer 2 so as to form a coil.
14 sheets of dielectric green sheets laminated so as to form a capacitor on the dielectric layer 1 were laminated in this order to obtain a pressure-bonded laminated body. Next, after sintering, the product was cut and cut to allow for a shrinkage rate of 5 mm square, degreased and baked at 900 ° C. for 3 hours to obtain a product. At the same time, the same number of conventional products without the above-mentioned dummy layer were prepared.

【0020】前記の本発明による製品と従来構造品のそ
れぞれ256個について、デラミネーションもしくはク
ラックが発生した個片を不良と見做した不良率と、図6
に示す反り量を画像顕微鏡により測定した平均値を表1
に示す。
For each of the 256 products of the present invention and the conventional structure described above, the defect rate in which the individual pieces in which delamination or cracks were generated were considered defective, and FIG.
The average value of the warp amount shown in Table 1 was measured by an image microscope.
Shown in.

【表1】 [Table 1]

【0021】前記磁性体層、誘電体層に用いた材料の7
00℃、800℃、900℃および900℃にて3時間
燒結させた試料の焼成収縮率・熱膨張率について表2に
示す。磁性体層、誘電体層の焼成収縮率差・熱膨張率差
は十分小さいことが分かる。
7 of materials used for the magnetic layer and the dielectric layer
Table 2 shows the firing shrinkage rate and the thermal expansion rate of the samples sintered at 00 ° C, 800 ° C, 900 ° C and 900 ° C for 3 hours. It can be seen that the difference in firing shrinkage and the difference in thermal expansion between the magnetic layer and the dielectric layer are sufficiently small.

【表2】 [Table 2]

【0022】表1の比較結果から本発明の効果は明らか
であり、焼成収縮率・熱膨張率を近似させても解決でき
なかったデラミネーション・クラック・反りの発生を抑
制していることが分かる。
From the comparison results in Table 1, the effect of the present invention is clear, and it can be seen that the occurrence of delamination, cracks, and warpage, which could not be solved even by approximating the firing shrinkage ratio and the thermal expansion coefficient, is suppressed. .

【0023】なお、本発明に係わる積層電子部品は前記
の実施例に限定するものではなく、その趣旨の範囲で種
々の材料で実現することができる。磁性体は実施例に述
べたNi−Cu−Znフェライトに限らず、Ni−Cu
系、Cu−Zn系、Mg−Cu−Zn系などの低温燒結
フェライトを使用しても良い。誘電体は実施例に述べた
BaO−ZnO−TiO2系チタン酸系複合酸化物に限
らず、酸化チタン系、チタン酸系複合酸化物、ジルコン
酸系複合酸化物、あるいはこれらの混合物を使用するこ
とができる。また誘電体中に燒結助剤を添加しても良
い。具体的には酸化チタン系として、NiO、CuO、
Mn3O4を含むTiO2などが、チタン酸系複合酸化
物としてはBaTiO3、SrTiO3、CaTiO
3、MgTiO3、ZnTiO3などが、ジルコン酸系
複合酸化物としてはBaZrO3、SrZrO3、Ca
ZrO3、MgZrO3などが挙げられる。燒結助剤と
してCuO、Bi2O3、V2O5、PbOやこれらの
混合物が挙げられる。
The laminated electronic component according to the present invention is not limited to the above-mentioned embodiment, and can be realized by various materials within the scope of the spirit thereof. The magnetic material is not limited to the Ni-Cu-Zn ferrite described in the examples, but may be Ni-Cu.
A low temperature sintered ferrite such as a system, Cu-Zn system, or Mg-Cu-Zn system may be used. The dielectric is not limited to the BaO-ZnO-TiO2-based titanate-based composite oxide described in the examples, but titanium oxide-based, titanate-based composite oxide, zirconate-based composite oxide, or a mixture thereof may be used. You can Also, a sintering aid may be added to the dielectric. Specifically, as titanium oxide type, NiO, CuO,
TiO2 containing Mn3O4, etc., but BaTiO3, SrTiO3, CaTiO as titanic acid-based composite oxides.
3, MgTiO3, ZnTiO3, and the like, but as the zirconic acid-based complex oxide, BaZrO3, SrZrO3, Ca.
Examples thereof include ZrO3 and MgZrO3. Examples of the sintering aid include CuO, Bi2O3, V2O5, PbO and a mixture thereof.

【0024】[0024]

【実施例2】磁性体層としてFe2O3 48mol
%、NiO 6mol%、CuO 10mol%、Zn
O 36mol%からなるNi−Cu−Znフェライ
ト、誘電体層としてBaO 16mol%、TiO2
67mol%、Nd2O3 14mol%、Bi2O3
3mol%からなるチタン酸系複合酸化物誘電体材料
にホウ珪酸亜鉛ガラスを3wt%添加した材料、接合層
としてBaO 12mol%、TiO2 55mol
%、ZnO 33mol%からなるチタン酸系複合酸化
物誘電体材料にホウ珪酸亜鉛ガラスを3wt%添加した
材料にそれぞれバインダー、可塑材、溶剤を加えて混練
しスリップを用意した。
Example 2 Fe2O3 48 mol as a magnetic layer
%, NiO 6 mol%, CuO 10 mol%, Zn
Ni-Cu-Zn ferrite composed of O 36 mol%, BaO 16 mol% as a dielectric layer, and TiO2
67 mol%, Nd2O3 14 mol%, Bi2O3
A material obtained by adding 3 wt% of zinc borosilicate glass to a titanate-based composite oxide dielectric material consisting of 3 mol%, BaO 12 mol% and TiO 2 55 mol as a bonding layer.
%, ZnO 33 mol% titanic acid-based composite oxide dielectric material to which 3 wt% of zinc borosilicate glass was added, a binder, a plasticizer and a solvent were added and kneaded to prepare a slip.

【0025】次に、それぞれのスリップをドクターブレ
ード法で、厚さ100μmのグリーンシートに成形し
た。つぎに得られたグリーンシートのそれぞれを、必要
に応じてビア形成用のスルーホールと共に10cm角の
シートに打ち抜き、LCフィルタを構成するべく、誘電
体シートには複数のコンデンサ電極を、磁性体シートに
は複数のコイル形成パターンに銀ペーストを用いて印刷
し多数個取りのシートを得た。
Next, each slip was formed into a green sheet having a thickness of 100 μm by the doctor blade method. Next, each of the obtained green sheets is punched out into a 10 cm square sheet together with a through hole for forming a via if necessary, so that a plurality of capacitor electrodes are provided on the dielectric sheet and a magnetic sheet to form an LC filter. A plurality of coil forming patterns were printed with silver paste to obtain a multi-cavity sheet.

【0026】ついで、図3の構造に示すダミー層3に前
記接合層グリーンシートを1枚、磁性体層2にコイルを
形成するように積層された磁性体グリーンシートを18
枚、接合層4に前記接合層グリーンシートを1枚、誘電
体層1にコンデンサを形成するように積層された誘電体
グリーンシートを14枚、順に積層し圧着積層体を得
た。次に燒結後製品が5mm角になるよう収縮率を見込
んで切断、脱脂後900℃で3時間焼成し製品化した。
同時に、比較例として図8に示す、ダミー層を配設しな
い従来品を同数作成した。
Next, one magnetic layer green sheet is formed on the dummy layer 3 shown in the structure of FIG. 3, and one magnetic layer green sheet is laminated on the magnetic layer 2 so as to form a coil.
One sheet, the above-mentioned joining layer green sheet on the joining layer 4, and 14 sheets of the dielectric green sheet laminated on the dielectric layer 1 so as to form a capacitor were sequentially laminated to obtain a pressure-bonded laminate. Next, after sintering, the product was cut and cut to allow for a shrinkage rate of 5 mm square, degreased and baked at 900 ° C. for 3 hours to obtain a product.
At the same time, as a comparative example, the same number of conventional products shown in FIG.

【0027】前記の本発明による製品と従来構造品のそ
れぞれ256個について、デラミネーションもしくはク
ラックが発生した個片を不良と見做した不良率と、図6
に示す反り量を画像顕微鏡により測定した平均値を表3
に示す。
For each of the above-mentioned 256 products of the present invention and the conventional structure, the defect rate in which the individual pieces in which delamination or cracks occurred were regarded as defective, and FIG.
The average value of the warp amount shown in Table 3 is measured by an image microscope and the average value is shown in Table 3.
Shown in.

【表3】 [Table 3]

【0028】前記磁性体層、誘電体層、接合層に用いた
材料の700℃、800℃、900℃および900℃に
て3時間燒結させた試料の焼成収縮率・熱膨張率につい
て表4に示す。磁性体層/接合層間、誘電体層/接合層間
の焼成収縮率の差・熱膨張率の差は十分小さいことが分
かる。
Table 4 shows firing shrinkage and thermal expansion coefficients of the materials used for the magnetic layer, the dielectric layer and the bonding layer, which were sintered at 700 ° C., 800 ° C., 900 ° C. and 900 ° C. for 3 hours. Show. It can be seen that the differences in firing shrinkage and thermal expansion between the magnetic layer / junction layer and the dielectric layer / junction layer are sufficiently small.

【表4】 [Table 4]

【0029】表3の検査結果から本発明の効果は明らか
であり、接合層を用いて焼成収縮率・熱膨張率を連続的
に変化させても解決できなかったデラミ・クラック・反
りの発生を抑制していることが分かる.
From the inspection results in Table 3, the effect of the present invention is clear, and the occurrence of delamination, cracks, and warping, which could not be solved even by continuously changing the firing shrinkage rate and the thermal expansion rate by using the bonding layer, occurred. You can see that it is suppressing.

【0030】[0030]

【発明の効果】異種材料層を接合させ一体燒結させた積
層電子部品において、製品に反りや、デラミネーション
や、クラックの発生を押さえ、かつ、サンドイッチ構成
を取らないことで、コンデンサの数の多い構成の製品で
も、上下層のコンデンサの接続のため、外部電極による
中継や中間層にスルーホールの打ち抜きと、該スルーホ
ールへの銀ペーストの刷り込み工程が不要となり、実効
面積の減少をなくした小型で低コストの積層電子部品が
提供できる。
EFFECTS OF THE INVENTION In a laminated electronic component in which different material layers are joined and integrally sintered, warpage, delamination and cracks are prevented from being produced in the product, and a sandwich structure is not used, resulting in a large number of capacitors. Even in the product with the configuration, since the capacitors in the upper and lower layers are connected, there is no need for relaying by external electrodes, punching through holes in the intermediate layer, and the step of imprinting silver paste into the through holes, thus eliminating the reduction in effective area. It is possible to provide a small-sized and low-cost laminated electronic component.

【0031】[0031]

【図面の簡単な説明】[Brief description of drawings]

【図1】請求項1の積層電子部品の構造説明図を示す。FIG. 1 is a structural explanatory view of a laminated electronic component according to claim 1.

【図2】請求項1の積層電子部品の構造説明図を示す。FIG. 2 is a structural explanatory view of the laminated electronic component of claim 1.

【図3】請求項2の積層電子部品の構造説明図を示す。FIG. 3 is a structural explanatory view of the laminated electronic component of claim 2;

【図4】請求項2の積層電子部品の構造説明図を示す。FIG. 4 is a structural explanatory view of the laminated electronic component of claim 2;

【図5】従来の積層電子部品の構造説明図を示す。FIG. 5 is a structural explanatory view of a conventional laminated electronic component.

【図6】反り量の計測例を示す。FIG. 6 shows an example of measuring the amount of warpage.

【図7】従来の積層電子部品の不良モードを示す。FIG. 7 shows a failure mode of a conventional laminated electronic component.

【図8】従来の積層電子部品の構造説明図を示す。FIG. 8 is a structural explanatory view of a conventional laminated electronic component.

【図9】従来の積層電子部品の構造断面図を示す。FIG. 9 is a structural cross-sectional view of a conventional laminated electronic component.

【符号の説明】[Explanation of symbols]

1 誘電体層 2 磁性体層 3 ダミー層 4 接合層 5 積層電子部品 6 反り量 7 クラック 8 デラミネーション 9 コンデンサ電極 10 コイル電極 11 ビア 1 Dielectric layer 2 Magnetic layer 3 Dummy layer 4 Bonding layer 5 Multi-layer electronic components 6 Warp amount 7 crack 8 delamination 9 Capacitor electrode 10 coil electrode 11 beer

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E070 CB01 CB13 5E082 AA01 AB03 CC02 DD07 5J024 AA01 CA09 DA01 DA29    ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5E070 CB01 CB13                 5E082 AA01 AB03 CC02 DD07                 5J024 AA01 CA09 DA01 DA29

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 異種材料層からなる積層電子部品におい
て、導体層を内蔵する誘電体層と、導体層を内蔵する磁
性体層を積層し、積層体上下面の少なくとも1面に、前
記誘電体層あるいは磁性体と同一材料で導体層を内蔵し
ないダミー層を接合し、誘電体層と磁性体層が交互に接
合してなることを特徴とする積層電子部品。
1. In a laminated electronic component made of different material layers, a dielectric layer containing a conductor layer and a magnetic layer containing a conductor layer are laminated, and the dielectric is formed on at least one of the upper and lower surfaces of the laminate. A laminated electronic component, wherein a dummy layer made of the same material as a layer or a magnetic body and not containing a conductor layer is joined, and a dielectric layer and a magnetic layer are alternately joined.
【請求項2】 異種材料層からなる積層電子部品におい
て、導体層を内蔵する誘電体層と導体層を内蔵する磁性
体層との中間に接合層を介して積層し、さらに積層体上
下面の少なくとも1面に、接合層と同一材料で導体層を
内蔵しないダミー層を接合してなることを特徴とする積
層電子部品。
2. In a laminated electronic component made of different material layers, a dielectric layer containing a conductor layer and a magnetic layer containing a conductor layer are laminated with a bonding layer in between, and the upper and lower surfaces of the laminate are laminated. A laminated electronic component comprising a dummy layer, which is made of the same material as that of the bonding layer and does not include a conductor layer, bonded to at least one surface.
【請求項3】 請求項1または2のいずれかに記載の積
層電子部品において、誘電体層および接合層にガラスを
含有することを特徴とする積層電子部品。
3. The laminated electronic component according to claim 1, wherein the dielectric layer and the bonding layer contain glass.
JP2001222749A 2001-07-24 2001-07-24 Laminated electronic components Expired - Fee Related JP4612970B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001222749A JP4612970B2 (en) 2001-07-24 2001-07-24 Laminated electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001222749A JP4612970B2 (en) 2001-07-24 2001-07-24 Laminated electronic components

Publications (2)

Publication Number Publication Date
JP2003037022A true JP2003037022A (en) 2003-02-07
JP4612970B2 JP4612970B2 (en) 2011-01-12

Family

ID=19056180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001222749A Expired - Fee Related JP4612970B2 (en) 2001-07-24 2001-07-24 Laminated electronic components

Country Status (1)

Country Link
JP (1) JP4612970B2 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005203723A (en) * 2003-10-24 2005-07-28 Kyocera Corp Glass ceramic substrate and method for manufacturing the same
JP2006041081A (en) * 2004-07-26 2006-02-09 Mitsubishi Materials Corp Composite common mode choke coil and manufacturing method therefor
WO2006085624A1 (en) * 2005-02-10 2006-08-17 Soshin Electric Co., Ltd. Electronic component
JP2006245258A (en) * 2005-03-03 2006-09-14 Tdk Corp Compound laminated electronic component
WO2009081504A1 (en) * 2007-12-25 2009-07-02 Nec Corporation Differential-common mode resonant filters
WO2010038890A1 (en) 2008-09-30 2010-04-08 双信電機株式会社 Composite electronic component
JP2010226038A (en) * 2009-03-25 2010-10-07 Tdk Corp Ceramic electronic component
US7898362B2 (en) 2005-02-16 2011-03-01 Soshin Electric Co., Ltd. Passband filter
JP2012028456A (en) * 2010-07-21 2012-02-09 Murata Mfg Co Ltd Method of manufacturing ceramic electronic component, ceramic electronic component and wiring board

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0555532U (en) * 1991-12-24 1993-07-23 太陽誘電株式会社 Multilayer LC filter
JP2000021640A (en) * 1998-06-29 2000-01-21 Sumitomo Metal Ind Ltd Noise filter and its manufacture
JP2000151325A (en) * 1998-11-13 2000-05-30 Sumitomo Metal Ind Ltd Stacked chip-type noise filter and its manufacture

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04311018A (en) * 1991-04-09 1992-11-02 Murata Mfg Co Ltd Lc composite part
JPH06275465A (en) * 1993-03-18 1994-09-30 Murata Mfg Co Ltd Multilayer lc composite part
JPH11329852A (en) * 1998-03-13 1999-11-30 Matsushita Electric Ind Co Ltd Composite component and manufacture thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0555532U (en) * 1991-12-24 1993-07-23 太陽誘電株式会社 Multilayer LC filter
JP2000021640A (en) * 1998-06-29 2000-01-21 Sumitomo Metal Ind Ltd Noise filter and its manufacture
JP2000151325A (en) * 1998-11-13 2000-05-30 Sumitomo Metal Ind Ltd Stacked chip-type noise filter and its manufacture

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005203723A (en) * 2003-10-24 2005-07-28 Kyocera Corp Glass ceramic substrate and method for manufacturing the same
JP4619026B2 (en) * 2003-10-24 2011-01-26 京セラ株式会社 Glass ceramic substrate and manufacturing method thereof
JP2006041081A (en) * 2004-07-26 2006-02-09 Mitsubishi Materials Corp Composite common mode choke coil and manufacturing method therefor
US7764143B2 (en) 2005-02-10 2010-07-27 Soshin Electric Co., Ltd. Electronic component including a magnetic layer and a dielectric layer
JPWO2006085625A1 (en) * 2005-02-10 2008-06-26 双信電機株式会社 Electronic components
JPWO2006085624A1 (en) * 2005-02-10 2008-06-26 双信電機株式会社 Electronic components
US7737803B2 (en) 2005-02-10 2010-06-15 Soshin Electric Co., Ltd. Electric part including a dielectric portion and a magnetic portion
WO2006085625A1 (en) * 2005-02-10 2006-08-17 Soshin Electric Co., Ltd. Electronic part
WO2006085624A1 (en) * 2005-02-10 2006-08-17 Soshin Electric Co., Ltd. Electronic component
US7898362B2 (en) 2005-02-16 2011-03-01 Soshin Electric Co., Ltd. Passband filter
JP2006245258A (en) * 2005-03-03 2006-09-14 Tdk Corp Compound laminated electronic component
JP2011508465A (en) * 2007-12-25 2011-03-10 日本電気株式会社 Differential common mode resonance filter
WO2009081504A1 (en) * 2007-12-25 2009-07-02 Nec Corporation Differential-common mode resonant filters
US8576027B2 (en) 2007-12-25 2013-11-05 Nec Corporation Differential-common mode resonant filters
WO2010038890A1 (en) 2008-09-30 2010-04-08 双信電機株式会社 Composite electronic component
US8563871B2 (en) 2008-09-30 2013-10-22 Soshin Electric Co., Ltd. Composite electronic parts
JP5386496B2 (en) * 2008-09-30 2014-01-15 双信電機株式会社 Composite electronic components
JP2010226038A (en) * 2009-03-25 2010-10-07 Tdk Corp Ceramic electronic component
JP2012028456A (en) * 2010-07-21 2012-02-09 Murata Mfg Co Ltd Method of manufacturing ceramic electronic component, ceramic electronic component and wiring board
US8819932B2 (en) 2010-07-21 2014-09-02 Murata Manufacturing Co., Ltd. Method of manufacturing a ceramic electronic component

Also Published As

Publication number Publication date
JP4612970B2 (en) 2011-01-12

Similar Documents

Publication Publication Date Title
JP3322199B2 (en) Multilayer ceramic substrate and method of manufacturing the same
US7243424B2 (en) Production method for a multilayer ceramic substrate
JP7193918B2 (en) Multilayer ceramic capacitor and manufacturing method thereof
JP2020053577A (en) Electronic component
JP3928665B2 (en) Chip-type electronic component built-in multilayer substrate and method for manufacturing the same
EP1074524A1 (en) Glass-ceramic composition, circuit substrate using the same and manufacture method thereof
JP2011035145A (en) Multilayer electronic component
JP4612970B2 (en) Laminated electronic components
JP3513787B2 (en) LC composite parts
US20030062111A1 (en) Method of manufacturing glass ceramic multilayer substrate
JP2007053328A (en) Multilayer substrate having chip type electronic component built therein and its manufacturing method
JP2000208943A (en) Multilayer wiring board with built-in passive component and manufacture thereof
JPH10135073A (en) Composite ceramic electronic part and its manufacture
JP4765330B2 (en) MULTILAYER WIRING BOARD HAVING MULTILAYER ELECTRONIC COMPONENT AND METHOD FOR PRODUCING MULTILAYER WIRING BOARD
JP2001244140A (en) Ceramic laminate and manufacturing method thereof, electronic component and electronic device
JP6029491B2 (en) Manufacturing method of multilayer ceramic electronic component
JP3934841B2 (en) Multilayer board
JP2021103730A (en) Ceramic electronic component and mounting board
JP4569265B2 (en) Ceramic multilayer substrate and manufacturing method thereof
JP2005203629A (en) Electronic component
CN217562410U (en) Multilayer ceramic capacitor
JP2005142331A (en) Composite common mode choke coil
EP1589799A1 (en) Multi-layer ceramic substrate and method for manufacture thereof
JP3898653B2 (en) Manufacturing method of glass ceramic multilayer wiring board
JP2003026472A (en) Method for producing multilayer ceramic electronic parts, multilayer ceramic electronic parts and raw composite multilayer body for producing multilayer ceramic electronic parts

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080707

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080707

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20080707

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100521

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100525

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100726

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100928

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20101018

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131022

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4612970

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees