JP2003046230A - 構造体及びこの構造体を用いた実装方法 - Google Patents

構造体及びこの構造体を用いた実装方法

Info

Publication number
JP2003046230A
JP2003046230A JP2001235353A JP2001235353A JP2003046230A JP 2003046230 A JP2003046230 A JP 2003046230A JP 2001235353 A JP2001235353 A JP 2001235353A JP 2001235353 A JP2001235353 A JP 2001235353A JP 2003046230 A JP2003046230 A JP 2003046230A
Authority
JP
Japan
Prior art keywords
solder
mounting method
spacer
metal
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001235353A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003046230A5 (enrdf_load_stackoverflow
Inventor
Satoshi Ohama
聡 大浜
Kiyohito Endou
貴代仁 遠藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Optech Co Ltd
Original Assignee
Seiko Instruments Inc
Optech Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc, Optech Co Ltd filed Critical Seiko Instruments Inc
Priority to JP2001235353A priority Critical patent/JP2003046230A/ja
Publication of JP2003046230A publication Critical patent/JP2003046230A/ja
Publication of JP2003046230A5 publication Critical patent/JP2003046230A5/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
JP2001235353A 2001-08-02 2001-08-02 構造体及びこの構造体を用いた実装方法 Pending JP2003046230A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001235353A JP2003046230A (ja) 2001-08-02 2001-08-02 構造体及びこの構造体を用いた実装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001235353A JP2003046230A (ja) 2001-08-02 2001-08-02 構造体及びこの構造体を用いた実装方法

Publications (2)

Publication Number Publication Date
JP2003046230A true JP2003046230A (ja) 2003-02-14
JP2003046230A5 JP2003046230A5 (enrdf_load_stackoverflow) 2005-07-07

Family

ID=19066811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001235353A Pending JP2003046230A (ja) 2001-08-02 2001-08-02 構造体及びこの構造体を用いた実装方法

Country Status (1)

Country Link
JP (1) JP2003046230A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006173460A (ja) * 2004-12-17 2006-06-29 Renesas Technology Corp 半導体装置の製造方法
US8446739B2 (en) 2008-12-24 2013-05-21 Kyocera Corporation Circuit device and electronic device
CN111757611A (zh) * 2020-06-05 2020-10-09 深圳市隆利科技股份有限公司 一种应用于miniLED的安装结构及其制作方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006173460A (ja) * 2004-12-17 2006-06-29 Renesas Technology Corp 半導体装置の製造方法
US8446739B2 (en) 2008-12-24 2013-05-21 Kyocera Corporation Circuit device and electronic device
CN111757611A (zh) * 2020-06-05 2020-10-09 深圳市隆利科技股份有限公司 一种应用于miniLED的安装结构及其制作方法

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