JP2002530729A5 - - Google Patents

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Publication number
JP2002530729A5
JP2002530729A5 JP2000582814A JP2000582814A JP2002530729A5 JP 2002530729 A5 JP2002530729 A5 JP 2002530729A5 JP 2000582814 A JP2000582814 A JP 2000582814A JP 2000582814 A JP2000582814 A JP 2000582814A JP 2002530729 A5 JP2002530729 A5 JP 2002530729A5
Authority
JP
Japan
Prior art keywords
address
instruction
return
signal
call
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000582814A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002530729A (ja
Filing date
Publication date
Priority claimed from US09/191,777 external-priority patent/US6154865A/en
Application filed filed Critical
Publication of JP2002530729A publication Critical patent/JP2002530729A/ja
Publication of JP2002530729A5 publication Critical patent/JP2002530729A5/ja
Pending legal-status Critical Current

Links

JP2000582814A 1998-11-13 1999-10-25 集積回路テスタを制御する命令処理パターン発生器 Pending JP2002530729A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/191,777 US6154865A (en) 1998-11-13 1998-11-13 Instruction processing pattern generator controlling an integrated circuit tester
US09/191,777 1998-11-13
PCT/US1999/024051 WO2000029863A1 (en) 1998-11-13 1999-10-25 Instruction processing pattern generator controlling an integrated circuit tester

Publications (2)

Publication Number Publication Date
JP2002530729A JP2002530729A (ja) 2002-09-17
JP2002530729A5 true JP2002530729A5 (https=) 2006-12-21

Family

ID=22706896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000582814A Pending JP2002530729A (ja) 1998-11-13 1999-10-25 集積回路テスタを制御する命令処理パターン発生器

Country Status (5)

Country Link
US (1) US6154865A (https=)
EP (1) EP1129363A4 (https=)
JP (1) JP2002530729A (https=)
KR (1) KR100634992B1 (https=)
WO (1) WO2000029863A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030099139A1 (en) * 2001-08-24 2003-05-29 Abrosimov Igor Anatolievich Memory test apparatus and method of testing
US7941640B1 (en) * 2006-08-25 2011-05-10 Marvell International Ltd. Secure processors having encoded instructions
US9134377B2 (en) * 2013-03-14 2015-09-15 Teradyne, Inc. Method and apparatus for device testing using multiple processing paths
US10139449B2 (en) 2016-01-26 2018-11-27 Teradyne, Inc. Automatic test system with focused test hardware
KR102308990B1 (ko) * 2021-07-20 2021-10-06 (주) 에이블리 반도체 테스트 패턴 발생 장치 및 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5161749A (en) * 1974-11-26 1976-05-28 Fujitsu Ltd Deetashorisochino shoriringuseigyohoshiki
US4041462A (en) * 1976-04-30 1977-08-09 International Business Machines Corporation Data processing system featuring subroutine linkage operations using hardware controlled stacks
US4371949A (en) * 1977-05-31 1983-02-01 Burroughs Corporation Time-shared, multi-phase memory accessing system having automatically updatable error logging means
US4173782A (en) * 1978-01-03 1979-11-06 International Business Machines Corporation Return and link mechanism
US4313200A (en) * 1978-08-28 1982-01-26 Takeda Riken Kogyo Kabushikikaisha Logic test system permitting test pattern changes without dummy cycles
US4493045A (en) * 1981-10-19 1985-01-08 Fairchild Camera & Instrument Corp. Test vector indexing method and apparatus
JPH0641966B2 (ja) * 1984-02-15 1994-06-01 株式会社アドバンテスト パタ−ン発生装置
US5023828A (en) * 1988-07-20 1991-06-11 Digital Equipment Corporation Microinstruction addressing in high-speed CPU
US5321701A (en) * 1990-12-06 1994-06-14 Teradyne, Inc. Method and apparatus for a minimal memory in-circuit digital tester
JP2602997B2 (ja) * 1991-01-18 1997-04-23 株式会社東芝 パターン発生器

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