JP2002525912A - トリガされたクロック信号の発生器 - Google Patents

トリガされたクロック信号の発生器

Info

Publication number
JP2002525912A
JP2002525912A JP2000570933A JP2000570933A JP2002525912A JP 2002525912 A JP2002525912 A JP 2002525912A JP 2000570933 A JP2000570933 A JP 2000570933A JP 2000570933 A JP2000570933 A JP 2000570933A JP 2002525912 A JP2002525912 A JP 2002525912A
Authority
JP
Japan
Prior art keywords
clock signal
trigger
signal
delay
tap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000570933A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002525912A5 (enExample
Inventor
ディントマン・ブライアン・ジェイ
Original Assignee
クリーダンス システムズ コーポレイション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クリーダンス システムズ コーポレイション filed Critical クリーダンス システムズ コーポレイション
Publication of JP2002525912A publication Critical patent/JP2002525912A/ja
Publication of JP2002525912A5 publication Critical patent/JP2002525912A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3016—Delay or race condition test, e.g. race hazard test
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP2000570933A 1998-09-16 1999-09-14 トリガされたクロック信号の発生器 Pending JP2002525912A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/154,329 US6084930A (en) 1998-09-16 1998-09-16 Triggered clock signal generator
US09/154,329 1998-09-16
PCT/US1999/021010 WO2000016515A1 (en) 1998-09-16 1999-09-14 Triggered clock signal generator

Publications (2)

Publication Number Publication Date
JP2002525912A true JP2002525912A (ja) 2002-08-13
JP2002525912A5 JP2002525912A5 (enExample) 2006-10-19

Family

ID=22550918

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000570933A Pending JP2002525912A (ja) 1998-09-16 1999-09-14 トリガされたクロック信号の発生器

Country Status (5)

Country Link
US (1) US6084930A (enExample)
EP (1) EP1114538A1 (enExample)
JP (1) JP2002525912A (enExample)
KR (1) KR100759908B1 (enExample)
WO (1) WO2000016515A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008123075A (ja) * 2006-11-09 2008-05-29 Meidensha Corp タイマ起動回路
JP2014238670A (ja) * 2013-06-06 2014-12-18 富士通株式会社 半導体回路装置、及び、電子装置

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6785873B1 (en) * 1997-05-02 2004-08-31 Axis Systems, Inc. Emulation system with multiple asynchronous clocks
JP4286375B2 (ja) * 1999-04-02 2009-06-24 株式会社アドバンテスト 遅延クロック生成装置および遅延時間測定装置
US6775339B1 (en) * 1999-08-27 2004-08-10 Silicon Graphics, Inc. Circuit design for high-speed digital communication
US6647027B1 (en) * 1999-11-10 2003-11-11 Lsi Logic Corporation Method and apparatus for multi-channel data delay equalization
US7031420B1 (en) 1999-12-30 2006-04-18 Silicon Graphics, Inc. System and method for adaptively deskewing parallel data signals relative to a clock
US6880137B1 (en) * 2001-08-03 2005-04-12 Inovys Dynamically reconfigurable precision signal delay test system for automatic test equipment
US7152176B2 (en) * 2003-11-19 2006-12-19 Broadcom Corporation Dynamic resynchronization of clocked interfaces
US7454675B1 (en) 2004-10-22 2008-11-18 Xilinx, Inc. Testing of a programmable device
US20060132340A1 (en) * 2004-12-22 2006-06-22 Lin Chun W Apparatus and method for time-to-digital conversion and jitter-measuring apparatus using the same
US7385543B2 (en) * 2006-06-19 2008-06-10 Agilent Technologies, Inc. Systems and methods for asynchronous triggering of an arbitrary waveform generator
KR200451705Y1 (ko) * 2008-05-26 2011-01-06 (주)스마일안전 안전모용 햇빛가리개
KR101222625B1 (ko) * 2011-07-20 2013-01-16 이성 주식회사 신호 샘플링 장치 및 방법
JP2013231918A (ja) * 2012-05-01 2013-11-14 Samsung R&D Institute Japan Co Ltd フレームメモリの制御回路、表示装置及びフレームメモリの制御方法
CN111817701B (zh) * 2020-06-24 2023-01-10 苏州浪潮智能科技有限公司 相位自纠正电路
KR102873843B1 (ko) * 2022-04-15 2025-10-22 삼성전자주식회사 스큐 제어 기능을 갖는 팬-아웃 버퍼, 작동 방법, 및 이를 포함하는 프로브 카드
CN114924180B (zh) * 2022-05-18 2025-10-03 深圳市一博科技股份有限公司 一种在pcie夹具中生成参考时钟的电路
CN115189795B (zh) * 2022-06-22 2024-04-05 国电投核力电科(无锡)技术有限公司 一种粒子加速器用同步定时触发脉冲发生方法及系统

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3928813A (en) * 1974-09-26 1975-12-23 Hewlett Packard Co Device for synthesizing frequencies which are rational multiples of a fundamental frequency
US5764710A (en) * 1995-12-15 1998-06-09 Pericom Semiconductor Corp. Meta-stable-resistant front-end to a synchronizer with asynchronous clear and asynchronous second-stage clock selector
US5712883A (en) * 1996-01-03 1998-01-27 Credence Systems Corporation Clock signal distribution system
JP3636397B2 (ja) * 1996-04-04 2005-04-06 富士通株式会社 ジッタ抑圧回路
US5790609A (en) * 1996-11-04 1998-08-04 Texas Instruments Incorporated Apparatus for cleanly switching between various clock sources in a data processing system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008123075A (ja) * 2006-11-09 2008-05-29 Meidensha Corp タイマ起動回路
JP2014238670A (ja) * 2013-06-06 2014-12-18 富士通株式会社 半導体回路装置、及び、電子装置

Also Published As

Publication number Publication date
WO2000016515A1 (en) 2000-03-23
EP1114538A1 (en) 2001-07-11
KR20010071991A (ko) 2001-07-31
US6084930A (en) 2000-07-04
KR100759908B1 (ko) 2007-09-18

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