JP2002523854A - 集積回路のビルトイン自己試験方法及びその装置 - Google Patents

集積回路のビルトイン自己試験方法及びその装置

Info

Publication number
JP2002523854A
JP2002523854A JP2000566851A JP2000566851A JP2002523854A JP 2002523854 A JP2002523854 A JP 2002523854A JP 2000566851 A JP2000566851 A JP 2000566851A JP 2000566851 A JP2000566851 A JP 2000566851A JP 2002523854 A JP2002523854 A JP 2002523854A
Authority
JP
Japan
Prior art keywords
memory
test signal
semiconductor device
input circuit
row
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000566851A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002523854A5 (id
Inventor
ルペジアン・イェルバント・デビット
マーランジアン・ハラント
グーカシャン・ホーファンネス
クラウス・ローレンス
Original Assignee
クリーダンス システムズ コーポレイション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クリーダンス システムズ コーポレイション filed Critical クリーダンス システムズ コーポレイション
Publication of JP2002523854A publication Critical patent/JP2002523854A/ja
Publication of JP2002523854A5 publication Critical patent/JP2002523854A5/ja
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Dram (AREA)
JP2000566851A 1998-08-21 1998-08-21 集積回路のビルトイン自己試験方法及びその装置 Pending JP2002523854A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1998/017298 WO2000011674A1 (en) 1998-08-21 1998-08-21 Method and apparatus for built-in self test of integrated circuits

Publications (2)

Publication Number Publication Date
JP2002523854A true JP2002523854A (ja) 2002-07-30
JP2002523854A5 JP2002523854A5 (id) 2006-01-05

Family

ID=22267708

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000566851A Pending JP2002523854A (ja) 1998-08-21 1998-08-21 集積回路のビルトイン自己試験方法及びその装置

Country Status (4)

Country Link
EP (1) EP1105876A4 (id)
JP (1) JP2002523854A (id)
KR (1) KR100589532B1 (id)
WO (1) WO2000011674A1 (id)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006252702A (ja) * 2005-03-11 2006-09-21 Nec Electronics Corp 半導体集積回路装置及びその検査方法
JP2008065862A (ja) * 2006-09-04 2008-03-21 System Fabrication Technologies Inc 半導体記憶装置
JP2010033564A (ja) * 2008-07-25 2010-02-12 Internatl Business Mach Corp <Ibm> キャッシュ・ディレクトリ内の実ページ番号ビットのテスト方法、装置、およびコンピュータ記録可能な媒体

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6550034B1 (en) 2000-02-17 2003-04-15 Hewlett Packard Development Company, L.P. Built-in self test for content addressable memory
US6658610B1 (en) * 2000-09-25 2003-12-02 International Business Machines Corporation Compilable address magnitude comparator for memory array self-testing
KR101232195B1 (ko) * 2011-02-25 2013-02-12 연세대학교 산학협력단 반도체 메모리 장치 테스트 방법 및 테스트 장치

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4817093A (en) * 1987-06-18 1989-03-28 International Business Machines Corporation Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
US5258986A (en) * 1990-09-19 1993-11-02 Vlsi Technology, Inc. Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories
JPH0770240B2 (ja) * 1990-12-27 1995-07-31 株式会社東芝 半導体集積回路
JP3269117B2 (ja) * 1992-05-26 2002-03-25 安藤電気株式会社 半導体メモリ用試験パターン発生器
KR0141432B1 (ko) * 1993-10-01 1998-07-15 기다오까 다까시 반도체 기억장치
US5617531A (en) * 1993-11-02 1997-04-01 Motorola, Inc. Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor
US5659551A (en) * 1995-05-31 1997-08-19 International Business Machines Corporation Programmable computer system element with built-in self test method and apparatus for repair during power-on
US5661732A (en) * 1995-05-31 1997-08-26 International Business Machines Corporation Programmable ABIST microprocessor for testing arrays with two logical views
US5615159A (en) * 1995-11-28 1997-03-25 Micron Quantum Devices, Inc. Memory system with non-volatile data storage unit and method of initializing same
US5805789A (en) * 1995-12-14 1998-09-08 International Business Machines Corporation Programmable computer system element with built-in self test method and apparatus for repair during power-on

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006252702A (ja) * 2005-03-11 2006-09-21 Nec Electronics Corp 半導体集積回路装置及びその検査方法
JP2008065862A (ja) * 2006-09-04 2008-03-21 System Fabrication Technologies Inc 半導体記憶装置
JP2010033564A (ja) * 2008-07-25 2010-02-12 Internatl Business Mach Corp <Ibm> キャッシュ・ディレクトリ内の実ページ番号ビットのテスト方法、装置、およびコンピュータ記録可能な媒体

Also Published As

Publication number Publication date
WO2000011674A1 (en) 2000-03-02
KR100589532B1 (ko) 2006-06-13
EP1105876A1 (en) 2001-06-13
EP1105876A4 (en) 2003-09-17
KR20010052985A (ko) 2001-06-25

Similar Documents

Publication Publication Date Title
US5974579A (en) Efficient built-in self test for embedded memories with differing address spaces
US6560740B1 (en) Apparatus and method for programmable built-in self-test and self-repair of embedded memory
US6085346A (en) Method and apparatus for built-in self test of integrated circuits
US6011748A (en) Method and apparatus for built-in self test of integrated circuits providing for separate row and column addresses
US5173906A (en) Built-in self test for integrated circuits
KR970004074B1 (ko) 메모리 장치 및 이를 포함한 집적 회로
EP1377981B1 (en) Method and system to optimize test cost and disable defects for scan and bist memories
US6643807B1 (en) Array-built-in-self-test (ABIST) for efficient, fast, bitmapping of large embedded arrays in manufacturing test
EP0716421B1 (en) A method for testing an array of Random Access Memories (RAMs)
JP3588246B2 (ja) プロセッサ・ベースの組込み自己検査マクロ及び集積回路チップ
KR0174340B1 (ko) 매립 논리 회로 검사 시스템 및 그 검사 방법과 집적 회로 칩
US5568437A (en) Built-in self test for integrated circuits having read/write memory
KR100714240B1 (ko) 반도체 집적회로 및 기록매체
US7284166B2 (en) Programmable multi-mode built-in self-test and self-repair structure for embedded memory arrays
Treuer et al. Built-in self-diagnosis for repairable embedded RAMs
US5930814A (en) Computer system and method for synthesizing a filter circuit for filtering out addresses greater than a maximum address
US5983009A (en) Automatic generation of user definable memory BIST circuitry
US5442640A (en) Test and diagnosis of associated output logic for products having embedded arrays
US8046648B1 (en) Method and apparatus for controlling operating modes of an electronic device
US6907385B2 (en) Memory defect redress analysis treating method, and memory testing apparatus performing the method
JP2002523854A (ja) 集積回路のビルトイン自己試験方法及びその装置
Hunter et al. The PowerPC 603 microprocessor: An array built-in self test mechanism
KR940002904B1 (ko) 데이타 처리 시스템 및 이 시스템에 있어서의 다수 메모리 어레이 테스팅 방법
JP4176944B2 (ja) 半導体集積回路及び記録媒体
JPH1040700A (ja) 組み込み型自己テスト機能付き半導体チップ

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050721

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050721

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20060712

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080331

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080508

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20081014