JP2002523854A - Integrated circuit self-test method and apparatus - Google Patents

Abstract

(57) Abstract: A BIST function is provided in which both the row address (50) and the column address (40) of the memory (90) to be tested are independently selected. The present invention provides flexibility in selecting the addresses to be tested, improves the transition time between rows, and further determines which memory addresses were good or bad in the test. Enable.

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION The present invention relates to semiconductor integrated circuits, and more particularly to embedded memories,
In particular, it relates to a test circuit incorporated in an integrated circuit (IC) that enables testing of read / write memory effectiveness.

As integrated circuits achieve ever higher levels of integration, it has become common to find several embedded memory blocks of different sizes within a logic block of the integrated circuit. Representative examples of embedded memories are data and instruction cache memories with associated tags and available data cache memories, incorporated into most modern microprocessors. These memories are called "built-in". Because they are not directly accessible from the I / O pins of the integrated circuit chip. Rather, the embedded memory is separated from the I / O pins by logic blocks during normal operation of the circuit. Thus, testing of these embedded memories is complicated because any access to these embedded memories during normal operation of the chip will be affected and changed by the associated logic.

[0003] Integrated circuits are widely used because they provide a high degree of functionality per cost. To achieve the necessary savings in modern integrated circuit manufacturing, it is necessary to minimize both the cost of the raw circuit and the cost of testing it. In many cases, the cost of device testing is comparable to the cost of manufacturing raw dies in a manufacturing plant. The cost of a operable die is roughly proportional to the inverse of the die area. Therefore, to minimize die cost, die area must be minimized. The cost of the test is almost proportional to the product of the test time and the cost of the test equipment. Therefore, in order to minimize test costs, it is desirable to both minimize the test time and minimize the complexity of the test equipment as much as possible.

[0004] Testing of the memory is generally accomplished by adding a measurement vector to the memory and reading the returned result to ensure proper memory operation. However, testing embedded memory via peripheral logic may require more measurement vectors than the available memory available to the automated test equipment used to test the device. In any case, it is very time consuming. Furthermore, it is undesirable that the development of programs to perform such tests requires a great deal of time for skilled test engineering and adds overhead costs.

Another possible processing method for testing embedded memories is to connect the control, address and data lines of the memory to external pads of the integrated circuit.
A multiplexer block is implemented in the integrated circuit to connect the embedded memory to external pads for testing, or to connect it to an internal bus for standard circuit operation. Disadvantages of this processing method are that the additional bus lines and pads increase the size of the semiconductor die, and the additional pads increase the required pin count of the tester. In general, the cost of a tester is roughly proportional to the number of pins. Due to the tendency of modern ICs to have wide memory and promote large capacity, the number of additional buses and pads required can often exceed 100, which leads to extraordinary cost burden.

[0006] In order to avoid excessive costs and at the same time provide adequate fault coverage, progress has been made to the built-in self-test (BIST) of integrated circuits. This process relies on incorporation of circuitry into an integrated circuit to test the memory with a limited number of pins and report the results to off-chip electronics. One example of the BIST method is a commonly used Joint Measurement Action Group (JTAG).
) Standard. A special measurement mode that overrides the normal operation of the circuit is invoked to enable BIST.

[0007] BIST is intended to minimize test time and die area occupied by BIST circuitry while providing full fault coverage. In one example,
It is desirable to make the diagnostic information available for the detected fault. These requirements are inconsistent, as adding diagnostic functionality increases the size of the BIST. Various schemes have been developed that optimize one factor and sacrifice the other.

[0008] One way to reduce the dedicated area for the data bus on the chip is to use serial data-inline and serial data-outline. Each buffer is loaded serially and they are used for parallel processing during writing and reading and during comparing the result read from memory with the stored data. The disadvantage of this processing method is that the maximum practical frequency is reduced by the data word width (eg 32 bits), and the memory is tested at a much lower frequency than the execution frequency. Therefore,
Faults which only appear at normal speed operation, such as capacitive coupling faults and transition faults, are not detected. Another consequence is that the time required to test the memory is increased by the time required to load the buffer serially. This may increase the test time by a factor approximately equal to the width of the memory word.

Another processing method adds a multiplexer to the memory input / output lines so that data read from the memory is reloaded into adjacent bits while the memory is in the test mode during a subsequent write period. It is to be. Thus, data from bit 1 is valid for writing to bit 2, data from bit 2 is valid for writing to bit 3, and so on. The first bit receives new data, and the data output from the last bit is transferred again to the finite state machine BIST controller for comparison. In the operating mode, the multiplexer connects the memory data lines to the chip data bus. Since the data is always available for writing when the read operation is completed, the memory is tested at any speed, thereby improving the quality and accuracy of the test process.

There are several ways to implement this scheme. In one possible example, all memories are used for testing purposes, such as the output of the last bit of a word in a first memory being fed to the input of the first bit of a word in a second memory. Try to have one valid very wide memory. Other examples include adding a series of control lines so that each memory is operated separately. This allows each memory to be tested sequentially. If the embedded memory has various different depths, the second method must be used because the first method requires that the memory depth be the same.

[0011] These processing methods have several disadvantages. For example, while the above example offers the advantage of utilizing a small area, it is nevertheless relatively slow. Furthermore, in the event of a failure, all that is recognized is the word address of the location of the failure. No information is available about which bit failed. This is because the word is configured to operate like a serial shift register without internal identifiability. In fact, if the first proposed method of linking words in parallel is used, even a faulty memory cannot be located. For a simple good or bad test, it is sufficient to confirm that a failure has occurred. However, if redundancy is used to correct the error, or if the cause of the error has to be analyzed, no critical information is available. In fact, if a word has a capacitive coupling error that causes an even number of transitions or bits to read one other than the intended data, even the error is masked.

Another processing method is to generate a data pattern and an address sequence centrally and then transfer them to embedded memory. This processing method is faster than the serial test processing method described above, especially when several embedded memories are tested in parallel. The disadvantage of this processing method is that the data path width has historically been 8
Providing extra data buses and address buses consumes a great deal of space on the chip, as the size of the bits has increased to the more common 32 or 64 bit sizes. The test signals are transferred to the embedded memory in parallel, while the buses during operation are often independent, for example, in the case of data cache and instruction cache, so that test and normal operation are performed. It may not be possible to use the same bus. This means that testing requires an extra bus, plus one multiplexer per data and address line.

[0013] Using a separate pattern generator for each array to be tested and transferring only simple coded instructions from the controller to the pattern generator,
It has been proposed to reduce bus area by instructing the pattern generator to perform any of a set of pre-prepared tests stored in the pattern generator. This processing method saves the bus footprint at the expense of the area required to create a separate pattern generator and test multiple memories.

Although parallel testing of embedded memories is desirable from a speed standpoint, heterogeneous embedded memories within an integrated circuit (eg, data cache RAM and associated tag cache RAM) are often not the same size. When two memories of different sizes are tested by being written with the same data pattern, the data in the smaller memory does not hinder the writing process to that memory when the address space of the smaller memory is exceeded In some cases, the lower address space is overwritten by data that fills the remaining space in the larger memory. This situation can easily result in inaccurate test results for smaller memories.

One processing method proposed to solve this problem is to use the state of the higher-order address to inhibit the writing of the signal to the smaller memory. This is effective in special cases of 3. For example, if one memory is smaller in the row direction and the size of the row address space of the smaller memory is a multiple of the binary number of the larger array (eg, 2 ^k ), then ORing the high order row addresses of use provides a simple means of generating the required inhibit signal. However, in the more general case where the smaller array is any size that is not a multiple of the binary of the larger array, a quantity comparator is required, which hinders the larger address space. Use an unacceptably large chip area.

In some memories, there is a significant difference between row and column addresses. For example, a DRAM reads an entire row at a time. Therefore, the access time for an address transition between column addresses in the same row is usually much faster than the access time for an address transition involving the selection of a different row. Similarly, some non-volatile memories have the ability to write to a page at the same time that the page is located along the same row. Because of this capability, the timing of a transition along a row is quite different from the timing of a transition from one row to another.

Despite the differences that occur in row and column timing, it is common practice for memory BIST to treat address space as a whole with no distinction between row and column addresses. . Therefore,
If the address is generated locally, a single counter is used for address generation. This is due to the implicit assumption that the embedded memory is an SRAM that is often designed to show little difference between row and column address transitions in both read and write modes. S
Although RAM is perhaps the most common type of embedded memory, the use of non-volatile memory and DRAM as embedded memory is becoming more common.

Thus, there is a need for a technique that changes the row and column addresses in a controlled manner so that, for example, each time a transition occurs in the row address space, the entire column address space can be accessed. Exists. Further, since not all embedded memories have the same row and column configuration, each memory incorporated on the integrated circuit may be tested according to different patterns of row and column addresses if necessary. There is a need for a technique to make this possible.

[0019] SUMMARY OF THE INVENTION The invention provides a method and apparatus for independently controlling the addressing of the rows and columns of the semiconductor memory by the BIST circuit. The present invention also allows the use of different row and column patterns during testing to accommodate memories having different size and configuration address spaces.

In one embodiment of the present invention, a semiconductor device has a memory having an address matrix and a BIST circuit used when testing the memory, and the BIST circuit has an input circuit. Can be coupled to a memory and independently select a row or column address of the memory to provide a test signal to a selected row or column.

In another embodiment, the present invention provides a method for testing a semiconductor device having a plurality of memories, each having an address matrix, using a BIST circuit, the method comprising: Selecting a first address of a first memory by individually selecting a first row and a first column; and selecting a second address of a second address.
Selecting a second address of the second memory by individually selecting the row and the second column of the second memory, and applying a test signal to the two addresses.

These embodiments provide flexibility in the choice of addresses to be tested, provide improved inter-column transition times, and which memory addresses are better for measurements. Provide the ability to decide what to do.

The present invention also prevents overwriting of data sent to memory addresses when multiple memories are tested simultaneously and one memory has a smaller address space than the other. For example, in order to prevent overwriting, the present invention makes it possible to prohibit the further application of the test signal to the memory to which the test signal was applied for all addresses, or to select the last signal. To be able to continue adding to the last address given. By preventing unwanted overwriting, the present invention provides improved diagnostics.

The present invention also provides that when multiple memories are tested simultaneously, the test signals are delayed to apply the test signals to the memories at substantially the same time. This allows for improved testing of memories located at different distances from the BIST circuit.

A further understanding of the nature and advantages of the present invention will be made with reference to the remainder of the specification and the accompanying drawings.

Description of the Preferred Embodiment FIG. 1 illustrates an overall block diagram of a preferred embodiment of the BIST circuit of the present invention. For example, a circuit for a BIST function such as that shown in FIG. 1 is generated by a logic synthesizer that receives input data written in a high-level design language that describes the function to be performed. In FIG. 1, these lines, which are actually buses, are indicated by diagonal lines crossing them. For example, line 86 between decoder 85 and local timing deskew circuit 70. The main controller 10 is shown on the left side of the dotted line in this figure. In this figure, the blocks appearing to the right of the dotted line are distributed and arranged in groups one by one with respect to the embedded memories to be tested (for example, memories 90 and 91). Two such logical function groups are illustrated as 100 and 101 in FIG. The blocks distributed for the BIST function include a row address generator 40, a column address generator 50, address filters 49 and 59, a data decoder 85, and a data comparator 8.
0 and the local timing deskew circuit 70. Note that only one of the lines extending from the main controller to the distributed blocks is the bus encoded data line 12. As set forth in related US patent application Ser. No. 08 / 697,969, entitled "Built-In Self-Test Method and Apparatus for Integrated Circuits," assigned to the assignee of the present application and incorporated herein by reference. In addition, even for the bus, the number of lines on the bus is shown to be less than or equal to log2 (number of patterns) for the encoding circuit to properly minimize the width of the encoded data bus. The small number of lines required for transfer is an example of the effect of the present invention. This device requires only one more line than a device that does not distinguish between row and column addresses.

The main controller shown in FIG. 2 coordinates and synchronizes tests performed on individual memories. Row address clock 13, column address clock 14, address initialization signal 15, address reset signal 16, increment / decrement signal 1
7 controls generation of addresses for the memory. This controller requires two address counters, rather than a single counter which would otherwise be needed, but the counters are small. In many cases, the number of bits of the combined two counters is the same as the number of bits of the single counter used in the case of no distinction. Therefore, the total chip area used by the counter of the present invention is the same as the chip area of the single counter of the indistinguishable processing method.

Referring again to FIG. 1, decoder 85 decodes the pattern information and provides data to the memory under test. This data is decoded and asserted to the data bus 8
It is sent to 6. This signal and address are sent to the local timing deskew circuit 7
Synchronized by 0. Data bus 81, address bus 84, and control line 83
The above signals operate the memory by reading and writing two data states from all memory locations while changing the address sequence.

The data comparator 80 compares the corresponding input data with the data read from the memory under the control of the read enable bus 19 and the diagnostic / shift signal 18 to report a good / bad result. . If the information was valuable, adding two more lines would allow the data comparator to report the address location of any failed bits back to the controller. This information can be combined with information about which pattern or data polarity was used and reported to an external tester for further analysis or redundant correction or other actions.

FIG. 3 shows a logic diagram of a preferred embodiment of the pseudo-random column address generator 40. The pseudo-random column address generator is based on a synchronous shift register with linear feedback. The feedback is defined by a primitive polynomial, the degree of the polynomial depends on the number of addresses to be generated. Polynomials are well known in the art and are described, for example, in Bardell et al., "Built-in Tests for VLSI:
Pseudo-random techniques. In operation, the address reset signal 16 first resets all outputs of all flip-flops in the register to "0". Addresses of zero (all zeros) that are not otherwise generated by the pseudo-random generator except at reset are thus output on address bus 46. The address generator 40 is then seeded by using the address initialization signal 15 to set the A _c0 flip-flop 43 to “1”. The A _c0 flip-flop 43 was selected for seeding purposes only, and any other flip-flop may be selected to seed the generator, as appropriate. Clocking the shift register with the address clock 14 means that once all 0s are placed on the address bus 46 in pseudo-random order.
, And thereafter, if there is no interrupt, the generation is repeated in the same order.

The flip-flops 43 and 44 together with the increment / decrement signal 17
Each address is sequenced in increments (eg, all start from 0) or in decrement order (eg, all start from 1) by selecting either the data output or the data capture output from. A multiplexer 45 is used to determine whether or not. The feedback network 47 is flip-
Connected to the appropriate outputs of flops 43 and 44 to form the desired primitive polynomial.
A polynomial feedback loop passing through an exclusive OR (XOR) gate 41 allows the generation of a pseudo-random sequence of "0" and "1" shifted through a shift register. The output of the multiplexer 45 forms the line of the address bus 46.

In this function, as in the main controller, the number of latches of the counter depends on the number of addresses to be generated, but does not depend on whether the addresses are divided into row addresses and column addresses. Thus, the chip area dedicated to address generation is clearly not affected by having separate row and column address generators.

A difficulty that arises when different types of memory, for example, non-volatile memory and SRAM, are incorporated on the same integrated circuit is that different memories have different sized address spaces. Writing to a larger address space may cause data tampering in memory with a smaller address space. This is because multiple addresses are aliased to the same address.

The present invention makes it possible to prohibit writing to an aliased address on a memory having a small address space. One way to do this is to freeze (freeze) each address signal and each data signal when an address boundary is exceeded in the signal of the last valid address. These signals are quiesced until another valid address (eg, an address in the memory address space) is asserted. This means that when the address generator provides an address outside the address space of a smaller memory, the last valid address location is read and written with the appropriate data for that location, while in larger memories This means that other data is read and written from other address locations.

Address filters 49 and 59 generate a signal indicating when either the row address space or the column address space of the memory has been exceeded. This function is only needed for memories on ICs that have less memory space than other memories to be tested at the same time. Thus, this block may be omitted from the logical group associated with memory having a space equivalent to the address space of the largest memory on the chip to be tested. Also, if a pseudo-random processing method for address generation is employed, each address may alternate several times into and out of the space reserved for the smaller memory. The present invention can effectively compensate for this situation.

The address filter 50 is, for example, entitled “Efficient Filtering of Different Address Spaces in Built-in Self-Test for Embedded Memory”, and is a related US patent assigned to the assignee of the present application and incorporated herein by reference. Application No. 08/697,
No. 968. Dividing the address space makes it possible to simplify the filtering problem and save layout space.

Local timing deskew circuit 70 provides waveform shaping and edge placement for input signals to respective embedded memory arrays 90 and 91. Each signal on the address bus 84, the control line 83 and the decoded data bus 81 is used to write to and read from all memory locations in both polarities while changing the address sequence, thereby enabling the integrated memory 90 to be read. And 9
Run 1 The deskew circuit 70 has no timing issues associated with accessing different embedded memory arrays 90 and 91 which are separated by distances that may cause timing issues of, for example, 1 cm or more. To ensure.

[0038] Aliasing can be prevented by controlling the read / write signal using the result of the address filtering function. The processing method is entitled "Efficient Built-In Self-Test for Embedded Memory with Different Address Spaces" and is related to U.S. patent application Ser. As described in the above document, the method includes using an output of an address counter in the main controller to generate a signal for interrupting a write function to a smaller address space.

FIG. 4 shows a simplified circuit diagram of the local timing deskew circuit 70. As in normal practice in VLSI design, deskew circuit 70 employs simultaneously clocked latches 72 and 73 to provide a deskew function. Another logic element, AND gate 71, inhibits writing of test data to invalid address locations. As long as the address stop signal 52 is high, the output of the AND gate 71, which is basically the clock signal 20, is continuously supplied to the built-in memory under test by the control signal 83, the address signal 84 and the data signal 81.
Continue to propagate. However, when either the address stop signal 48 or 58 becomes low, the output of the AND gate 71 always becomes low by notifying an address other than the address space area of the smaller embedded memory 91, and the output of the data line And the outputs of the latches 72, 73 and 74 connected to the address line are stopped. Only the control signal 83 is allowed to propagate through the latch 75.
Therefore, reading and writing is restricted to the last valid address before the address space of the smaller memory is exceeded, and thus data is rewritten many times to the location of the last valid address. The number of gates in this circuit does not depend on address segmentation.

FIG. 2 illustrates that this embodiment uses separate counters 21 and 22 for row addresses and column addresses, respectively. In the main controller, the two counters are controlled by a state signal 29. Either or the other or both can continue to operate once depending on either the fast row or fast column or the desired random address sequence. The outputs of the two counters of the main controller determine the operation of the row and column address clocks 13 and 14, respectively.

The above description is illustrative and not restrictive. Many variations of the present invention,
Upon review of the disclosure of this application, it will become apparent to one of ordinary skill in the art. For example, many address spaces and data patterns are used, which result in different formulas and diagrams. Further, the same logic function may implement several methods. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims along with their full scope of equivalents.

[Brief description of the drawings]

FIG. 1 is a block diagram of wiring connection of an entire BIST circuit and a BIST function designed in accordance with the teachings of the present invention.

FIG. 2 is a block diagram of a main controller related to the teachings of the present invention.

FIG. 3 is a logic diagram of a local address generator designed according to the teachings of the present invention.

FIG. 4 is a logic diagram illustrating one example of a local timing deskew circuit designed in connection with the teachings of the present invention.

[Procedural Amendment] Submission of translation of Article 34 Amendment of the Patent Cooperation Treaty

[Submission date] February 28, 2000 (2000.2.28)

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Description of the Preferred Embodiment FIG. 1 illustrates an overall block diagram of a preferred embodiment of the BIST circuit of the present invention. For example, a circuit for a BIST function such as that shown in FIG. 1 is generated by a logic synthesizer that receives input data written in a high-level design language that describes the function to be performed. In FIG. 1, these lines, which are actually buses, are indicated by diagonal lines crossing them. For example, line 86 between decoder 85 and local timing deskew circuit 70. The main controller 10 is shown on the left side of the dotted line in this figure. In this figure, the blocks appearing to the right of the dotted line are distributed and arranged in groups one by one with respect to the embedded memories to be tested (for example, memories 90 and 91). Two such logical function groups are illustrated as 100 and 101 in FIG. The blocks distributed for the BIST function include a row address generator 40, a column address generator 50, address filters 49 and 59, a data decoder 85, and a data comparator 8.
0 and the local timing deskew circuit 70. Note that only one of the lines extending from the main controller to the distributed blocks is the bus encoded data line 12. No. 08 / 697,969, entitled "Built-In Self-Test Method and Apparatus for Integrated Circuits," assigned to the assignee of the present application and now abandoned and incorporated herein by reference. As before, even for the bus, the number of lines on the bus is shown to be less than or equal to log 2 (number of patterns) for the encoding circuit to properly minimize the width of the encoded data bus. The small number of lines required for transfer is an example of the effect of the present invention. This device requires only one more line than a device that does not distinguish between row and column addresses.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) G06F 11/22 350 G06F 11/22 360A 5B048 360 12/16 330B 5L106 12/16 330 G11C 17/00 D 5M024 G11C 11/401 11/34 371A 11/413 341D 16/02 601Z 17/00 G01R 31/28 BV (72) Inventor Marrandian Hallant Republic of Armenia, Yerevan 75037, Barberyan Street 36, Apartment 20 (72 ) Inventor Goukashan Hofanness, Republic of Armenia, Yerevan 375014, Fumanoff Street A, 6 (72) Inventor Claus Lawrence United States of America, California 95112, San Jose, N. Second Street 777 F-term (reference) 2G132 AA08 AB01 AG01 AG05 AK29 5B003 AC01 AE04 5B015 HH01 HH03 JJ00 KB91 RR03 RR06 5B018 GA03 HA01 JA21 MA03 NA01 NA06 QA13 5B025 AD16 AE09 5B048 AA20 CC11 DD08A25A DDA BB30 BB40 MM01 MM05 PP01 PP02

Claims (20)

[Claims] 1. A semiconductor device incorporating a memory having a plurality of addressable memory cells arranged in a matrix and a built-in self-test circuit for use in a memory test, wherein the built-in self-test circuit comprises: An input circuit connected to the memory, wherein the input circuit independently selects a row of memory cells and a column of memory cells in the memory, and further provides a test signal to the selected row and the selected column. A semiconductor device having what can be done. 2. The input circuit has a row address generator for selecting the row, and a column address generator for selecting the column, and the input circuit outputs a test signal to the selected row and the selected row. 2. The semiconductor device according to claim 1, wherein the address is provided to an address defined by a combination of columns. 3. The semiconductor device according to claim 2, wherein said row address generator pseudo-randomly selects said row, and said column address generator pseudo-randomly selects said column. . 4. The input circuit is coupled to a first memory and a second memory of the device, and the input circuit has means for adjusting a timing of the test signal, 2. The semiconductor device according to claim 1, wherein the second memory receives the test signal at substantially the same time. 5. The distributed arrangement wherein said input circuit is coupled to a plurality of memories of said device, said input circuit comprises a plurality of distributed arrangements, each distributed arrangement is coupled to a respective memory, 2. The semiconductor device according to claim 1, wherein each of said circuits processes a test signal in association with a respective memory. 6. The at least one distributed circuit includes a timing circuit for changing a timing of a test signal to a first memory, wherein the test signal is transmitted to the first memory and the second memory substantially simultaneously. 6. The semiconductor device according to claim 5, wherein the semiconductor device is added. 7. The device according to claim 1, wherein the device has a first memory and a second memory.
Has a smaller address space as compared to the second memory, the input circuit has a controller, and the input circuit is used for all memory cells to be tested in the first memory. The semiconductor device of claim 1, wherein the controller prohibits the input circuit from providing a signal to the first memory as soon as a test signal is provided. 8. The device according to claim 1, wherein said device has a first memory and a second memory.
Has a smaller address space as compared to the second memory, the input circuit has a controller, and the input circuit is configured for every memory cell to be tested in the first memory. 2. The semiconductor device according to claim 1, wherein if the test signal is provided by the controller, the controller stops the test signal of the selected memory cell and the last selected memory cell of the first memory. 9. The device according to claim 1, wherein said device has a first memory and a second memory.
Has a smaller address space than the second memory, the input circuit has a controller, and the memory cell to be selected is not in the smaller address space of the first memory; 2. The semiconductor device according to claim 1, wherein the controller inhibits the input circuit from providing a signal to the first memory. 10. The device has a first memory and a second memory, the first memory has a smaller address space than the second memory, and the input circuit has a controller. And the current memory cell to be selected is the first memory cell.
2. The method of claim 1, wherein the controller quiesces the test signal of the selected memory cell and the preselected memory cell of the first memory when not within the smaller address space of the first memory. Semiconductor device. 11. A first memory having a plurality of first memory cells arranged in a matrix matrix, and a second memory having a plurality of second memory cells arranged in a matrix matrix. The plurality of second memory cells being larger than the plurality of first memory cells; and a first memory for applying a first selected test signal to a first selected memory cell of the first memory. A second processor coupled to the first memory; and a second processor for applying a second selected test signal to a second selected memory cell of the second memory. A first memory and a second memory, wherein the first and second selected memory cells are pseudo-randomly determined using an independent selection of rows and columns, coupled to a second memory; Main controller to be connected Te, semiconductor devices having one said main controller to said first and second controls processor said first and second memory receives substantially simultaneously the test signal. 12. The first processor has a first data comparator that compares the first selected test signal with a first output signal from the first selected memory cell, and 12. The data processor of claim 11, wherein the second processor includes a second data comparator for comparing the second selected test signal with a second output signal from the second selected memory cell. A semiconductor device according to claim 1. 13. A method for testing a semiconductor device including a plurality of memories each having a plurality of memory cells arranged in a matrix, wherein the first row indicates the first memory cells of the first memory. Selecting the first memory cells by selecting the first and second columns, wherein the selection of the rows and columns is independent of each other, and the second memory cells of the second memory are shown. Selecting the second memory cell by selecting a second row and a second column, wherein the row and column selections are independent of each other; A test method comprising the steps of: applying a test signal to one memory cell; and applying a second test signal to the second memory cell. 14. The method according to claim 13, wherein both steps of applying the test signal occur substantially simultaneously. 15. The method for testing a semiconductor device according to claim 14, further comprising a step of adjusting a timing of a step of applying the first test signal. 16. The method according to claim 13, wherein the selecting step is performed pseudo-randomly. 17. The method of claim 1, wherein the first memory has a smaller address space as compared to the second memory, the method further comprising selecting all memory cells in the first memory to be tested. 14. The method according to claim 13, further comprising a step of prohibiting the selection of the first memory after the step. 18. The method according to claim 18, wherein the first memory has a smaller address space as compared to the second memory, wherein the method further comprises selecting all memory cells in the first memory to be tested. 14. The method of testing a semiconductor device according to claim 13, further comprising the step of stopping a selected memory cell in the first memory by a memory cell in the first memory selected after the first memory cell. 19. The method of claim 1, wherein the first memory has a smaller address space as compared to the second memory, and the method further comprises: selecting a memory cell to be selected in the address space of the first memory. 14. The method according to claim 13, further comprising a step of prohibiting the selection of the first memory when there is no memory. 20. The method according to claim 19, wherein the first memory has a smaller address space as compared to the second memory, the method further comprising: selecting a current memory cell to be selected from the address space of the first memory. 14. The semiconductor of claim 13, further comprising the step of quiescing a selected memory cell in the first memory with a preselected memory cell of the first memory if not. Device testing method.