KR100589532B1 - Method and apparatus for built-in self test of integrated circuits - Google Patents

Abstract

It provides a BIST function that can independently select the column address 50 and the row address 40 of the memory 90 to be tested. The present invention provides flexibility in selecting addresses to test, improves transition time between columns, and allows determining which memory addresses pass or fail a test.

BIST function, local timing adjustment circuit, address generator, address filter, data comparator, pseudo random technique

Description

Built-in self test method and device for integrated circuits {METHOD AND APPARATUS FOR BUILT-IN SELF TEST OF INTEGRATED CIRCUITS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits and, more particularly, to test circuits embedded in integrated circuits (ICs) capable of efficiently testing internal memories, particularly read / write memories.

As the level of integration of integrated circuits becomes higher and higher, it is common to find several memory blocks of varying sizes embedded in logic blocks of an integrated circuit. Typical examples of onboard memory are data and instruction cache memories and tag and valid data cache memories in combination with these and incorporated into most microprocessors these days. The memories are said to be "embedded" because they are not directly accessible from the input and output pins of the integrated circuit chip. Instead, the internal memory is isolated from the input and output pins by the logic block during normal operation of the circuit. Thus, testing of the internal memory is complicated because the combined logic blocks mediate all accesses during normal operation of the chip.

Integrated circuits are widely used because of their high cost-performance ratio. In order to achieve the economics required for modern integrated circuit manufacturing, there is a need to minimize the cost of raw circuits as well as test costs. In many cases, the cost of testing a device is comparable to the cost of manufacturing a raw die in a manufacturing plant. The cost of a functional die is approximately proportional to the inverse of the exponential function of the die area. Thus, there is a need to reduce die area in order to minimize die costs. The cost of the test is almost proportional to the product of the test time and the cost of the test equipment. Therefore, it is desirable to minimize both the test time and the complexity of the test equipment in order to reduce test costs.

In general, memory testing is performed by applying test vectors to memory and reloading the results to ensure proper memory operation. However, testing the internal memory through peripheral logic blocks may require more test vectors than the allowable memory available in the automatic test equipment used to test the device, and in some cases would be very time consuming. It may be. Also, the development of a program that performs such tests is undesirable because it requires a lot of skilled test engineering time and additional costs.

Another possible approach to the onboard memory test is to connect the control, address and data lines of the memory to an external pad of the integrated circuit. Multiplexer blocks are embedded in the integrated circuit to connect the internal memory to an additional pad for testing or an internal bus for standard circuit operation. The disadvantage of this approach is that additional bus lines and pads increase the size of the semiconductor die and the additional pads increase the number of pins required for the test. In general, the cost of the tester is generally proportional to the number of pins. As the trend of today's ICs increasingly aims at large, wide memory, the number of additional buses and pads required can often exceed a hundred, which represents a huge price burden.

In order to properly avoid errors while avoiding excessive costs, there has been a move towards the built-in self test (BIST) of integrated circuits. This approach relies on circuitry embedded in integrated circuits that tests memory and informs off-chip electronics of the results through a limited number of pins. One example of a BIST method is the commonly used Joint Test Action Group (JTAG) standard. Special test modes that disable the normal operation of the circuit are implemented to enable the BIST.

BIST aims to fully compensate for errors while minimizing test time and die area occupied by BIST circuit components. In some applications, it is also desirable to use diagnostic information for detected errors. Additional diagnostic capabilities conflict with the above requirements because they increase the size of the BIST. Various attempts have been made to optimize one factor at the expense of others.

One way to reduce the area of the chip dedicated to the data bus is to use serial data input lines and serial data output lines. The buffers are loaded in series and then used for parallel operation while comparing the results of reading, writing and reading from memory with the stored data. The disadvantage of this approach is that the maximum operating frequency is reduced to the width of the data word (eg 32 bits), so that the memory is tested at a much lower frequency than the operating frequency. Therefore, errors that appear only during normal speed operation, ie capacitive coupling faults and transition faults, are not detected. Another result is that the time required to load the buffers in series increases the time required for memory testing. This can increase test time by a factor approximately equal to the width of the memory words.

Another approach is to add a multiplexer to the input and output lines of the memory so that the memory is in test mode and reloads the data read from the memory into adjacent bits during subsequent writes. Thus, data from bit 1 can be written to bit 2 and data from bit 2 can be written to bit 3. The first bit receives new data and the data output from the last bit is sent back to a finite state machine BIST controller for comparison. In the operating mode, the multiplexer connects the memory data line to the chip data bus. Since the data can always be written at the end of the read operation, the memory can be tested at operating speed, which improves the accuracy and quality of the test procedure.

Various ways of realizing this concept are possible. One feasible method is that the output of the last bit of the word in the first memory is input to the first bit of the word in the second memory in order to effectively make all the memory into one very large purpose memory. Another possible implementation is to add a series of control lines so that each of the memories can be enabled separately. This allows each memory to be tested in succession. In the case where the depths of the built-in memories are different, the first method must use the second method because the memory depth requires the same.

This approach has some drawbacks. For example, this approach is advantageous for utilizing small areas, but is relatively slow in spite of this. In addition, when an error occurs, the only thing known is the word address where the error occurred. The word is configured to operate as a serial shift register which cannot be internally observed, so that information about a bit in which an error occurs cannot be obtained. In the case of using the first method of actually connecting words in parallel, even an errored memory cannot be confirmed. In a simple pass or error test, it is sufficient to confirm the occurrence of the error. However, important information cannot be obtained when using redundancy to correct errors or analyzing the cause of the errors. In fact, even if the word contains an even number of transitional or capacitive coupling errors that cause the bits to be read in contrary to the intended data, even the presence of the error is concealed.

An alternative approach is to generate data patterns and address sequences centrally and transfer them to internal memory. This approach is faster than the serial test approach above, especially when testing some of the internal memory in parallel. The disadvantage of this approach is that sending extra data and address buses consumes a significant amount of chip area because the data path width increases from 8 bits to 32 bits or 64 bits, which is becoming more and more common. While the bus is often operating in isolation (eg for data and instruction caches), the test bus is sent in parallel to internal memory, so the same bus cannot be used during test and normal operation. This means that the test requires multiplexers per data and address line with additional buses.

There is a proposal to reduce the bus area by using a separate pattern generator for each array to be tested and by instructing the controller to send only a simple coding command to the pattern generator to indicate which of the pre-prepared and stored test sets to execute. . This approach reduces the transfer area at the expense of the area needed to create separate pattern generators for testing multiple memories.

Parallel testing of internal memory is desirable in terms of speed, but different internal memory (eg, data cache RAM and associated tag cache RAM) in integrated circuits are often not the same size. When two memory of different sizes are tested by recording the same data pattern, the data of the small memory is subordinate to the data to be filled in the remaining space of the large memory unless the writing process is prohibited in the small memory when the address space is exceeded. Overwriting starts in the address space. This situation results in inaccurate test results for small memories.

One approach proposed to solve the above problem is to prohibit write signals to small memories using the state of the upper address, which is efficient in some specific cases. For example, if a memory is smaller in the row direction and the size of the column address space of the smaller memory is a binary multiple of the larger array (ie 2 ^k ), the higher memory that is not used in the small memory It provides a simple means of ORing the column addresses to generate the necessary forbidden signal. However, in the more general case where a small array is any size rather than a binary multiple of a large array, a magnitude comparator that becomes very complex for a large address space and consequently consumes a large chip area that exceeds the allowable limit. comparator).

In some types of memory, there is a significant difference between column and row addresses. For example, DRAM senses all the heat at once. Thus, the access time for address transitions between row addresses within the same column is much faster than the access time for address transitions requiring the selection of different columns. Similarly, some nonvolatile memories have the ability to write one page at a time, where the pages lie along the same column. Because of this capability, the time when transitioning along one row may be significantly different from the recording time when transitioning from one row to another.

Despite the time differences that can occur in columns and rows, it is common for memory BIST to process the address space as a whole, regardless of the differences that occur between rows and columns. Therefore, when generating addresses locally, a single counter is used to generate the address. This is because there is an implicit assumption that internal memory is an SRAM designed to show little difference between column and row address transitions in both read and write modes. SRAM is probably the most common form of internal memory, but the use of nonvolatile memory and DRAM as internal memory is becoming common.

Thus, for example, there is a need for a technique that can change column and row addresses in a controlled manner such that the entire row address is accessed whenever there is a transition in the column address space. In addition, because not all internal memories may have the same configuration of columns and rows, a technique is needed to test each of the internal memories of an integrated circuit according to a different pattern of columns and row addresses if necessary.

The present invention provides a method and apparatus for independently controlling the addressing of columns and rows of a semiconductor memory with a BIST circuit. The present invention also allows for the use of different patterns of rows and columns, taking into account memory having different size or configuration address spaces during testing.

In one embodiment of the present invention, the semiconductor device includes a memory having an address matrix and a memory test BIST circuit, wherein the BIST circuit includes an input circuit connected to the memory to independent a column address or a row address of the memory. Can be selected and the test signal provided to the selected column or row.

In another embodiment, a method of testing a semiconductor device using a BIST circuit is provided, the device including a plurality of memories having an address matrix, the method comprising a first column of a first address and Selecting the first address in the first memory by independently selecting the first row, selecting the second address in the second memory by independently selecting the second column and the second row of the second address, and the second Applying a test signal to the two addresses.

The above embodiments provide flexibility in selecting the address to be tested, improved transition time between columns, and the ability to determine which memory address passes the test and fails.

The present invention also provides a method for preventing overwrite of data sent to a memory address when a plurality of memories are simultaneously tested and one memory has a smaller address space than another memory. For example, in order to prevent overwriting, the present invention no longer applies the test signal to the memory to which the test signal is applied to all addresses, or continuously applies the final signal to the selected last address. By preventing undesirable duplication, the present invention provides an improved diagnostic method.

The present invention also delays the test signal to apply the test signal to the memory substantially simultaneously when testing a plurality of memories at the same time. This may improve the testing of memory placed at different distances from the BIST circuit.

Further understanding of the features and advantages of the invention may be realized by the remainder of the specification and the description of the accompanying drawings.

1 is a block diagram illustrating an overall BIST functional circuit and a BIST functional path connection in accordance with the present invention.

2 is a block diagram of a master controller according to the present invention.

3 is a logic diagram of a local address generator in accordance with the present invention.

4 is an example logic diagram for a local timing adjustment circuit in accordance with the present invention.

1 is an overall block diagram of a preferred embodiment of a BIST circuit in accordance with the present invention. The circuit for BIST functions as shown in FIG. 1 can be generated by a logic synthesizer that receives input in an advanced design language that describes the executed function. In Fig. 1, the lines that are actually buses are shown in diagonal lines in the lines, for example the line 86 between the decoder 85 and the local timing de-skewing circuit 70. )to be. The master controller 10 is shown to the left of the dashed line in the figure. The blocks appearing to the right of the dashed line in the figure are divided into one group per internal memory (e.g., memory 90,91) to be tested. Two groups of such logic functions are shown in FIG. 1 as reference numerals 100 and 101. The blocks separated by the BIST function are the column address generator 50 and the row address generator 40, the address filters 49 and 59, the data decoder 85, the data comparator 85 and the local timing adjustment circuit 70. Note that only one of the lines from the main controller to the division block is the bus, i. The bus, as shown in the related application SN 08 / 697,969, assigned to the assignee of the present application and hereafter incorporated by reference, which is now entitled "Method And Apparatus For Built-In Self Test of Integrated Circuits" The number of lines of the bus can also be shown to be less than or equal to log2 (the number of patterns) for the encoding circuit that minimizes the width of the encoded data bus appropriately. The small number of lines needed for transmission is an example of the efficiency of the present invention. This method requires only one more line than does not distinguish between column and row addresses.

The master controller, shown in Figure 2, coordinates and synchronizes tests performed in individual memories. The column and row address clocks 13 and 14, the address initialization signal 15 and the increase / decrease signal 17 control the address generation of the memory. The counter is smaller, although it requires two counters, rather than a single counter, where the controller does not differentiate. In most cases, the number of bits coupled to the two counters is the same as the number of bits of a single counter used when not distinguishing. Therefore, the total chip area used by the counters in the present invention is similar to the chip area of a single counter when not distinguishing.

Referring again to FIG. 1, the decoder 85 decrypts the pattern information and provides data to the memory under test. The data is decrypted and shown on data bus 86. Local timing adjustment circuit 70 synchronizes the signal and address. Signals on data bus 81, address bus 84, and control line 83 are tested by reading and writing from all memory locations in all data states with different address sequences.

The data comparator 80 compares the data read from the memory with the corresponding input data and notifies the result, ie pass / fail, under the control of the read enable bus 19 and the diagnostic / shift signal 18. For this information to be useful, two or more lines can be added to cause the data comparator to notify the controller of the address location of any bad bits again. The information can be combined with information about which patterns and data polarities were used and information notified to an external tester for further analysis, redundancy repair, or other measures.

3 shows a logic diagram of a preferred embodiment of a pseudo-random row address generator 40. The pseudo random row address generator is based on a synchronous shift register with linear feedback. The feedback is determined by the initial polynomial, and the polynomial order depends on the number of addresses generated. Polynomials are well known in the art and are described, for example, in the book "Built-in Test for VLSI: Pseudo-random Techniques" by Bardell et al. have. In operation, the address reset signal 16 initially resets all outputs of all flip-flops of the register to " 0 ". Thus, an address of zero is the output of address bus 46 and is not generated by pseudo random generator 40 except upon reset. The address generator 40 then generates a seed by setting the A _C0 flip-flop 43 to " 1 " using the address initialization signal 15. A _C0 flip-flop 43 is selected for seeding by way of example only, and any other flip-flop may be appropriately selected for seeding of the generator. Clocking the shift register and the address clock 14 generates exactly one nonzero address in both pseudorandom orders on the address bus 46 exactly once, after which the generator is the same if there is no interruption. Repeat the order.

The multiplexer 45 selects the data or complement data output from the flip-flops 43 and 44 together with the increase / decrease signal 17, thereby ascending (i.e., starting with all "0") or descending order (address). That is, all start with "1"). Feedback network 47 is connected to the appropriate outputs of flip-flops 43 and 44 to form the desired initial polynomial. This polynomial feedback loop through the XOR gate 41 causes a pseudo random sequence of "0" and "1" to be shifted through the shift register. The output of multiplexer 45 forms the address bus 46 line.

In this function, such as in the master controller, the number of latches in the counter depends on the number of addresses generated, not whether it is divided into column and row addresses. Thus, the address generation area is not significantly affected by having separate column and row address generators.

When integrating different types of memory, such as nonvolatile memory and SRAM on the same integrated circuit, difficulties may arise that different memories have different sized address spaces. Writing over the entire address space can result in data corruption in a memory with a small address space since multiple addresses are aliased to the same address.

The present invention can prohibit writing to an aliased address on a memory having a small address space. One of the prohibition methods is to freeze the address signal and the data signal whose address threshold exceeds the signal of the last valid address. The signal is frozen until another valid signal (ie, an address in the address space of the memory) is asserted. This means that when the address generator provides an address that exceeds the address space of the small memory, it writes and reads the appropriate data for that location at the last valid address location, while writing and reading other data at different address locations in the large memory. Means.

The address filters 49, 59 generate a signal to indicate when the boundary value of the column or row address space of the memory has been exceeded. This functionality is only needed on integrated circuits, which have a smaller address space than the memory being tested at the same time. Thus, such blocks can be omitted from logical groups in combination with memory having an address space that is equivalent to the address space of the largest memory on the chip being tested. In addition, when pseudo-random techniques are used for address generation, addresses can be input and output alternately several times in an allowable address space of a small memory. The present invention effectively compensates for this condition.

For example, an address filter may be assigned to the assignee of the present application and subsequently incorporated by reference, and the address filter in the manner disclosed in the relevant publication SN 08 / 697,968 entitled "Efficient Filtering of Differing Address Space in Built-in Self Test for Embedded Memories". 50 can be generated. Splitting the address space can simplify filtering problems and reduce layout area.

The local timing adjustment circuit 70 provides pulse shaping and edge placement for the input signal to each of the internal memory arrays 90 and 91. The signals on the address bus 84, control line 83 and encoded data bus 81 test the built-in memories 90 and 91 by writing and reading from all memories of the two memories having different address sequences. The correction circuit 70 solves timing problems associated with accessing different internal memories 90 or 91 that may be separated by distances that may cause timing problems, such as more than one centimeter.

In addition, aliasing can be prevented by using the result of the address filtering function that controls the write / read signal. As disclosed in the related training SN 08 / 707,062, which is assigned to the assignee of the present application and hereafter incorporated by reference and entitled "Efficient Built-In Self Test For Embedded Memories With Differing Address Space", the approach involves a small address space. A method of using the output of the address counter at the master controller to generate a signal that interferes with the recording function.

4 is a circuit diagram simplifying the local timing adjustment circuit 70. The adjusting circuit 70 uses synchronized clock latches 72 and 73 to provide the adjusting function as is common in VLSI designs. An additional logic element, AND gate 71, prevents writing test data at an invalid address location. While the address stop signals 48 and 58 are high, the output of the AND gate 71, which is an essential clock signal 20, is controlled via the internal memory under test, the control signal 83, the address signal 84 and the data. The signal 81 continues to be transmitted. However, when the address halt signals 48 and 58 go low, they indicate an address output exceeding the boundary value of the address space of the small internal memory 91 and the If the output is always low, the output of latches 72 and 73, which are connected to the data and address lines, respectively, is frozen. Only control signal 83 is transmitted via latch 75. Thus, reading and writing is limited to the last valid address before exceeding the address space of the small memory, and then rewritten repeatedly at the location of the last valid address. The number of gates in this circuit has nothing to do with address splitting.

2 shows that the present embodiment uses separate counters 21 and 22 for each of the column and row addresses. In the main controller, two counters are controlled by the status signal 29. Either or both can run at the same time, depending on whether they are fast columns, fast rows, or random addressing sequences as desired. Two counters of the master controller determine the operation of each of the row and column address clocks 13, 14.

The above description is illustrative and not restrictive. Many variations of the invention will become apparent to those skilled in the art upon repetition of this specification. For example, many address spaces and other data patterns can be used, which will create different logic equations and logic diagrams. In addition, the same logical function can be implemented in various ways. Accordingly, the scope of the invention is not to be determined by the description, but rather by the claims appended herewith along with the full scope of equivalents.

Claims (20)

  A first memory (90) having a plurality of first memory cells occupying a first address space, wherein each memory cell stores and reads data when selected by a first address provided as input to the first memory. First memory 90,  A first data comparator 80 for comparing data written to each first memory cell with data read from each first memory cell, A first address generator 40, 50 for generating a first address sequence of addresses comprising an address in the first address space and an address outside the first address space, and Removing an address outside the first address space from the first address sequence and providing the first memory with the remaining address of the first address sequence as a first address input sequence to select the first memory cell; 1 address filter means (49, 59, 70) A semiconductor device comprising a. The method of claim 1, A second memory (91) having a plurality of second memory cells occupying a second address space, each storing data when each memory cell is selected by a second address provided as input to the second memory; A second memory 91 to read, A second data comparator 80 for comparing data written to each second memory cell with data read from each second memory cell,  A second address generator 40, 50 for generating a second address sequence identical to the first address sequence, the address including the address in the second address space and an address outside the second address space; A second address providing the remaining address of the second address sequence to the second memory as a second address input sequence to remove an address outside the second address space from the second address sequence and select the second memory cell; Address filter means (49, 59, 70) The semiconductor device of claim 1, wherein the first and second address spaces have different sizes. The method of claim 1, The first address generator comprises a column address generator, The first address filter means A column address filter for applying a column stop signal when the column address provided by the column address generator is out of the column address range by comparing the column address provided by the column address generator with the column address range of the first memory, and And a stop circuit for preventing an address in the first address sequence from being provided to the memory when a column stop signal is applied. The method of claim 3, The first address generator further comprises a row address generator, The first address filter means compares the row address provided by the row address generator with the row address range of the first memory to apply a row stop signal if the row address provided by the row address generator is outside the row address range. Further includes a row address filter, And the stop circuit prevents an address in the first address sequence from being provided to the memory when a column stop signal or a row stop signal is applied. The method of claim 1, The first address generator comprises a row address generator, The first address filter means A row address filter for applying a row stop signal when the row address provided by the row address generator is out of the row address range by comparing the row address provided by the row address generator with the row address range of the first memory; and And a stop circuit for preventing an address in the first address sequence from being provided to the memory when a row stop signal is applied. delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete

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