Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
  • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
  • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits

Definitions

• the present invention relates to semiconductor integrated circuits and, more particularly, to test circuits built into the integrated circuits (ICs) that enable efficient testing of embedded memory, especially read/write memory.
• embedded memory As integrated circuits achieve higher and higher levels of integration it is common to find several memory blocks of differing sizes embedded within blocks of logic in the integrated circuit.
• a typical example of embedded memory is the data and instruction cache memories along with their associated tag and valid data cache memories that are embedded in most modern microprocessors. These memories are called “embedded” because they are not directly accessible from the input and output pins of the integrated circuit chip.
• an embedded memory is separated by logic blocks from the input and output pins in ordinary operation of the circuit. Testing of these embedded memories is therefore complicated because any access to these memories during normal operation of the chip is mediated by the associated logic.
• Integrated circuits are widely used because they offer a high functionality per unit of cost. To achieve the economies necessary in modern integrated circuit manufacturing, it is necessary to minimize both the cost of the raw circuit as well as the cost of testing it. In many cases, the cost of testing the device is comparable to the cost of manufacturing the raw die in the fabrication plant. The cost of a functional die is roughly proportional to the inverse exponential of the die area. Therefore, it is necessary to minimize the die area in order to minimize die costs . The cost of testing is approximately proportional to the product of the test time and the cost of the testing equipment. Therefore, it is desirable to minimize both the test time and the complexity of the test equipment to minimize testing costs.
• Testing of memories is generally accomplished by applying test vectors to the memory and reading back the results to ensure proper memory operation.
• testing an embedded memory through the surrounding logic may require a number of test vectors larger than the available memory available in the automatic test equipment used for testing the device and is, in any case, very time-consuming. It is additionally undesirable because the development of programs to execute such tests require a large amount of skilled test engineering time, which adds to the overhead costs.
• Another possible approach to testing embedded memories is to connect the control, address, and data lines of the memories to external pads of the integrated circuit. Multiplexer blocks are implemented within the integrated circuit to connect the embedded memories either to the external pads for testing or to internal buses for standard circuit operation.
• a drawback to this approach is that the extra bus lines and pads increase the size of the semiconductor die and the extra pads increase the number of pins required of the tester. The cost of the tester is generally roughly proportional to the number of pins. Since the trend is toward wide memories of increasingly large capacity in modern ICs, the number of extra buses and pads required can frequently exceed one-hundred, which represents a prohibitive cost burden.
• BIST built-in self test
• BIST attempts to provide complete fault coverage while minimizing test time and the area of the die that is occupied by the BIST circuitry. In some applications, it is also desirable that diagnostic information be available for faults that are detected. These requirements are in conflict because adding diagnostic capability adds size to the BIST.
• Various schemes have been developed which optimize one factor at the expense of the others.
• One method for reducing the area on the chip devoted to data buses is to use a serial data-in line and a serial data-out line. Buffers are loaded serially and then used for parallel operation during writing, reading and comparison of the results read from the memory with the stored data.
• a disadvantage to this approach is that the maximum operational frequency is reduced by the width of the data word (e.g. 32 bits) , so that the memory is tested at much less than operational frequency. Thus, faults that appear only at normal speed operation, such as capacitive coupling faults and transition faults, are not detected.
• Another consequence is that the time needed to test the memory is increased by the time necessary to load the buffers serially. This can increase the test time by a factor approximately equal to the width of the memory words .
• Another approach is to add multiplexers to the memory input/output lines such that the data read from the memory can be loaded back into adjacent bits during the subsequent write while the memory is in the test mode.
• the data from bit 1 is available for writing into bit 2; the data from bit 2 is available for writing into bit 3; etc.
• the first bit receives new data and the data output from the last bit is routed back to the finite state machine BIST controller for comparison.
• the multiplexers connect the memory data lines to the chip data bus . Because data is always available for writing when a read operation is completed, the memory may be tested at operational speeds, which increases the quality and accuracy of the test procedure .
• the output of the last bit of a word in the first memory is fed into the input of the first bit of a word in the second memory, etc. so as to make all of the memories into effectively one very wide memory for testing purposes.
• Another implementation involves adding a series of control lines so that each memory can be enabled separately. This allows each memory to be tested sequentially.
• the second method must be used because the first method requires that the memory depths be the same.
• Information as to which bit failed is not available because the word is structured to operate as a serial shift register with no internal observability. Indeed, in the case that the first proposed method of chaining words in parallel is used, not even the memory that failed can be ascertained. For simple pass or fail testing, it is sufficient to identify that a failure has occurred. However, if redundancy is to be used to repair the failure or if the cause of the failure is to be analyzed, critical information is not available. In fact, if the word were to contain an even number of transition or capacitive coupling faults which cause the bit to read the opposite of the intended data, even the presence of the faults is masked. An alternate approach is to generate data patterns and address sequences centrally and route them to the embedded memories.
• One approach that has been proposed to solve this problem is to use the state of the higher order addresses to inhibit the write signal to the smaller memory, which can be efficient in a few special cases. For example, if one memory is smaller in the row direction and the size of the row address space of the smaller memory is a binary multiple (e.g. 2 k ) of the larger array, OR'ing the higher order row addresses that are unused in the smaller memory provides a simple means of generating the needed inhibit signal.
• the smaller array is of an arbitrary size that is not a binary multiple of the larger array, a magnitude comparator is required which becomes prohibitively complex for larger address spaces and consequently consumes an unacceptably large chip area. In some types of memory there are important differences between row and column addresses.
• DRAMs sense a complete row at once. Therefore it is common that the access time for address transitions among the column addresses within the same row are much faster than the access time for address transitions that involve selection of differing rows.
• certain types of nonvolatile memories have the capability to write to a page at a time wherein the page lies along the same row. Because of this capability, the write timings for transitions along a row may be quite different than those for transitions from one row to another.
• the present invention provides a method and apparatus for independently controlling the row and column addressing of a semiconductor memory by a BIST circuit.
• the present invention also allows use of different patterns of rows and columns during test to accommodate memories having address spaces of different sizes or configurations.
• a semiconductor device in one embodiment, includes a memory having a matrix of addresses and a BIST circuit for use in testing the memory, the BIST circuit including an input circuit that is coupled to the memory and that is capable of independently selecting a row address or a column address of the memory and providing test signals to the selected row or column.
• the present invention provides a method of testing a semiconductor device using a BIST circuit, the device including plural memories each having a matrix of addresses, the method including selecting a first address in a first memory by independently selecting a first row and a first column of the first address, selecting a second address in a second memory by independently selecting a second row and a second column of the second address, and applying test signals to the two addresses.
• the present invention also provides for preventing overwriting of data sent to a memory address when multiple memories are tested contemporaneously and one memory has a smaller address space than another. For example, to prevent overwriting, the present invention may inhibit further application of test signals to a memory that has had test signals applied to all of its addresses, or it may continue to apply the last signal to the last address selected. By preventing undesired overwriting, the invention provides for improved diagnosis .
• the present invention also provides that when plural memories are tested contemporaneously, the test signals may be delayed in order to apply the signals to the memories substantially simultaneously. This allows for improved testing of memories that are disposed at different distances away from the BIST circuit.
• Figure 1 is a block diagram of an entire BIST circuit and routing connections of a BIST function designed in accordance with the teachings of this invention.
• FIG. 2 is a block diagram of a main controller in accordance with the teachings of this invention.
• Figure 3 is a logic diagram of a local address generator designed in conformance with the teachings of this invention.
• FIG. 4 is a logic diagram of an example of a local timing de-skewing circuit designed in accordance with the teachings of this invention.
• Fig. 1 shows an overall block diagram of a preferred embodiment of a BIST circuit according to the present invention.
• the circuitry for a BIST function such as the one shown in Fig. 1 can be generated by a logic synthesizer that receives input data in a high-level design language describing the function to be performed.
• those lines that are actually buses are indicated by having a diagonal line across them, e.g., line 86 between a decoder 85 and a local timing de-skewing circuit 70.
• a main controller 10 is shown to the left of the dashed line in the figure.
• Blocks that appear to the right of the dashed line in this figure are distributed, one group per embedded memory to be tested (e.g., memories 90 and 91) .
• Two such groups of logic functions are shown in Fig. 1 as 100 and 101.
• Blocks that are distributed for the BIST function are row and column address generators 40 and 50, address filters 49 and 59, the data decoder 85, a data comparator 80, and the local timing de-skewing circuit 70. Note that only one of the lines running from the main controller to the distributed blocks is a bus, encoded data line 12.
• the number of lines in the bus can be shown to be less than or equal to log2 (number of patterns) for an encoding circuit that properly minimizes the width of the encoded data bus, as shown in a related application serial no. 08/697,969 entitled "Method and
• the decoder 85 decodes the pattern information and provides data to the memory under test. This data is decoded and asserted onto the data bus 86. This signal and the addresses are synchronized by the local timing de-skewing circuit 70. The signals on the data bus 81, address bus 84 and control line 83 exercise the memory by writing and reading from all of the memory locations in both data states with differing address sequences.
• the data comparator 80 compares the data read out of the memory with the corresponding input data and reports the results, pass/fail, under the control of a read enable bus 19 and a diagnosis/shift signal 18. Should the information be deemed valuable, the addition of two more lines allows the data comparator to report the address location of any failing bits back to the controller. This information can be combined with information as to what pattern and data polarity were used and reported to an external tester for further analysis, redundancy repair or other actions.
• Fig. 3 shows a logic diagram of a preferred embodiment of a pseudo-random column address generator 40.
• the pseudo-random column address generator is based on a synchronous shift register with linear feedback.
• the feedback is determined by a primitive polynomial, and the polynomial order is dependent upon the number of addresses to be generated.
• the polynomials are well-known in the field and are shown, for example, in the book "Built-in Test for VLSI: Pseudo-random Techniques" by Bardell et al .
• address reset signal 16 first resets all the outputs of all flip-flops in the register to "0". An address of zero (all O's) is thus output on address bus 46, which is not otherwise generated by a pseudo-random generator, other than at reset.
• the address generator 40 is seeded by using address initialization signal 15 to set the A ⁇ flip-flop 43 to "1".
• a co flip-flop 43 is chosen for seeding merely by way of example; any of the other flip-flops could have been chosen for seeding the generator, as appropriate. Clocking the shift register with the address clock 14 will generate all non-zero addresses exactly once in a pseudo-random order on address bus 46, after which the generation is repeated in the same order, if not interrupted.
• Multiplexers 45 are used to determine whether the addresses will be sequenced in incrementing order (i.e., start with "all O's") or decrementing order (i.e., start with "all l's") by selecting either the data or complement data output from the flip-flops 43 and 44 with the increment/decrement signal 17.
• a feedback network 47 is connected at the appropriate outputs of the flip-flops 43 and 44 to form the desired primitive polynomial.
• This polynomial feedback loop through an exclusive-OR (XOR) gate 41 permits generation of the pseudo-random sequence of "O's" and "l's” that is shifted through the shift register.
• the outputs of multiplexers 45 form the lines of the address bus 46.
• the number of latches in the counter is dependent upon the number of addresses to be generated and not whether they are partitioned into row and column addresses.
• the chip area devoted to address generation is not significantly affected by having separate row and column address generators.
• a difficulty that may arise when different types of memories, e.g., nonvolatile memory and SRAM, are integrated on the same integrated circuit is that the different memories will have different sized address spaces. Writing to the whole of the larger address spaces can cause data corruption in the memories with smaller address spaces because a plurality of addresses are aliased into the same address.
• This invention can inhibit writing to aliased addresses on memories with smaller address spaces.
• One method of doing this operates by freezing the address signals and data signals when the address bounds are exceeded at the signals of the last valid address. These signals are frozen until another valid address (i.e., an address within the address space of the memory) is asserted. This means that as the address generator provides addresses outside the smaller memory's address space, the last valid address location is written to and read from with the data appropriate to that location while other data may be written to and read from other address locations in the larger memory.
• the address filters 49 and 59 generate signals to indicate when the bounds of either the row or column address space of the memory are exceeded. This function is only needed for those memories on the IC that have address spaces smaller than other memories that are to be tested at the same time. Thus, this block may be omitted from the logic groups associated with those memories with address spaces equal to that of the largest memory on the chip to be tested. Also, when a pseudo-random approach to the address generation is employed, the addresses may alternate in and out of the allowed address space for the smaller memories a number of times. The present invention can effectively compensate for this situation.
• Address filter 50 may be generated, for example, by the method described in related application serial no.
• Local timing de-skewing circuit 70 provides pulse shaping and edge placement for the input signals to each embedded memory array 90 and 91.
• the signals on address bus 84, control line 83 and decoded data bus 81 exercise embedded memories 90 and 91 by writing and reading from all of the memory locations in both polarities with differing address sequences.
• the de-skewing circuit 70 assures that there are no timing problems associated with accessing different embedded memory arrays 90 or 91 that may be separated by distances that might create timing problems, such as a centimeter or more.
• Fig. 4 shows a simplified circuit diagram of the local timing de-skewing circuit 70.
• the de-skewing circuit 70 employs synchronously clocked latches 72 and 73 to provide the de-skewing function, as is common practice in VLSI design.
• An additional logic element, AND gate 71 inhibits the writing of test data to invalid address locations.
• address halt signal 52 As long as address halt signal 52 is high, the output of the AND gate 71, which is essentially clock signal 20, continues to propagate control signal 83, address signals 84 and data signals 81 through to the embedded memory under test.
• address halt signal 48 or 58 goes low, signifying an address out of bounds of the address space of a smaller embedded memory 91
• the output of AND gate 71 is always low, freezing the outputs of latches 72, 73 and 74 coupled to the data and address lines, respectively. Only control signal 83 is allowed to propagate through latch 75. Thus, reading and writing is restricted to the last valid address before the address space of the smaller memory was exceeded, and the data is therefore rewritten over and over again to the location of the last valid address.
• the number of gates in this circuit is not dependent upon the address segmentation.
• Fig. 2 illustrates that this embodiment employs separate counters 21 and 22 for the row and column addresses, respectively.
• the two counters are controlled by the state signal 29. Either one, the other, or both may be running at one time depending on whether a fast row, a fast column, or a random addressing sequence in desired.
• the output of the two counters in the main controller determine the operation of the row and column address clocks 13 and 14, respectively.

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• For Increasing The Reliability Of Semiconductor Memories (AREA)
• Tests Of Electronic Circuits (AREA)
• Static Random-Access Memory (AREA)
• Techniques For Improving Reliability Of Storages (AREA)
• Test And Diagnosis Of Digital Computers (AREA)
• Dram (AREA)

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• 1998
  • 1998-08-21 JP JP2000566851A patent/JP2002523854A/ja active Pending
  • 1998-08-21 WO PCT/US1998/017298 patent/WO2000011674A1/en active IP Right Grant
  • 1998-08-21 KR KR1020007014379A patent/KR100589532B1/ko not_active IP Right Cessation
  • 1998-08-21 EP EP98945762A patent/EP1105876A4/en not_active Withdrawn

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