EP1105876A4 - Method and apparatus for built-in self test of integrated circuits - Google Patents
Method and apparatus for built-in self test of integrated circuitsInfo
- Publication number
- EP1105876A4 EP1105876A4 EP98945762A EP98945762A EP1105876A4 EP 1105876 A4 EP1105876 A4 EP 1105876A4 EP 98945762 A EP98945762 A EP 98945762A EP 98945762 A EP98945762 A EP 98945762A EP 1105876 A4 EP1105876 A4 EP 1105876A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- built
- integrated circuits
- self test
- self
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US1998/017298 WO2000011674A1 (en) | 1998-08-21 | 1998-08-21 | Method and apparatus for built-in self test of integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP1105876A1 EP1105876A1 (en) | 2001-06-13 |
| EP1105876A4 true EP1105876A4 (en) | 2003-09-17 |
Family
ID=22267708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP98945762A Withdrawn EP1105876A4 (en) | 1998-08-21 | 1998-08-21 | Method and apparatus for built-in self test of integrated circuits |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP1105876A4 (en) |
| JP (1) | JP2002523854A (en) |
| KR (1) | KR100589532B1 (en) |
| WO (1) | WO2000011674A1 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6550034B1 (en) | 2000-02-17 | 2003-04-15 | Hewlett Packard Development Company, L.P. | Built-in self test for content addressable memory |
| US6658610B1 (en) * | 2000-09-25 | 2003-12-02 | International Business Machines Corporation | Compilable address magnitude comparator for memory array self-testing |
| JP2006252702A (en) * | 2005-03-11 | 2006-09-21 | Nec Electronics Corp | Semiconductor integrated circuit apparatus and its inspection method |
| JP2008065862A (en) * | 2006-09-04 | 2008-03-21 | System Fabrication Technologies Inc | Semiconductor memory device |
| US8185694B2 (en) * | 2008-07-25 | 2012-05-22 | International Business Machines Corporation | Testing real page number bits in a cache directory |
| KR101232195B1 (en) * | 2011-02-25 | 2013-02-12 | 연세대학교 산학협력단 | A test method for a semiconductor memory device and a test apparatus thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0492624A1 (en) * | 1990-12-27 | 1992-07-01 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit |
| US5258986A (en) * | 1990-09-19 | 1993-11-02 | Vlsi Technology, Inc. | Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories |
| US5477494A (en) * | 1992-05-26 | 1995-12-19 | Ando Electric Co., Ltd. | Apparatus for generating address bit patterns for testing semiconductor memory devices |
| US5588111A (en) * | 1988-12-09 | 1996-12-24 | Tandem Computers, Incorporated | Fault-tolerant computer system having switchable I/O bus interface modules |
| US5615159A (en) * | 1995-11-28 | 1997-03-25 | Micron Quantum Devices, Inc. | Memory system with non-volatile data storage unit and method of initializing same |
| US5659551A (en) * | 1995-05-31 | 1997-08-19 | International Business Machines Corporation | Programmable computer system element with built-in self test method and apparatus for repair during power-on |
| US5661732A (en) * | 1995-05-31 | 1997-08-26 | International Business Machines Corporation | Programmable ABIST microprocessor for testing arrays with two logical views |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4817093A (en) * | 1987-06-18 | 1989-03-28 | International Business Machines Corporation | Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure |
| KR0141432B1 (en) * | 1993-10-01 | 1998-07-15 | 기다오까 다까시 | Semiconductor memory |
| US5617531A (en) * | 1993-11-02 | 1997-04-01 | Motorola, Inc. | Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor |
| US5805789A (en) * | 1995-12-14 | 1998-09-08 | International Business Machines Corporation | Programmable computer system element with built-in self test method and apparatus for repair during power-on |
-
1998
- 1998-08-21 JP JP2000566851A patent/JP2002523854A/en active Pending
- 1998-08-21 EP EP98945762A patent/EP1105876A4/en not_active Withdrawn
- 1998-08-21 WO PCT/US1998/017298 patent/WO2000011674A1/en not_active Ceased
- 1998-08-21 KR KR1020007014379A patent/KR100589532B1/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5588111A (en) * | 1988-12-09 | 1996-12-24 | Tandem Computers, Incorporated | Fault-tolerant computer system having switchable I/O bus interface modules |
| US5258986A (en) * | 1990-09-19 | 1993-11-02 | Vlsi Technology, Inc. | Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories |
| EP0492624A1 (en) * | 1990-12-27 | 1992-07-01 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit |
| US5477494A (en) * | 1992-05-26 | 1995-12-19 | Ando Electric Co., Ltd. | Apparatus for generating address bit patterns for testing semiconductor memory devices |
| US5659551A (en) * | 1995-05-31 | 1997-08-19 | International Business Machines Corporation | Programmable computer system element with built-in self test method and apparatus for repair during power-on |
| US5661732A (en) * | 1995-05-31 | 1997-08-26 | International Business Machines Corporation | Programmable ABIST microprocessor for testing arrays with two logical views |
| US5615159A (en) * | 1995-11-28 | 1997-03-25 | Micron Quantum Devices, Inc. | Memory system with non-volatile data storage unit and method of initializing same |
Non-Patent Citations (1)
| Title |
|---|
| See also references of WO0011674A1 * |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010052985A (en) | 2001-06-25 |
| KR100589532B1 (en) | 2006-06-13 |
| WO2000011674A1 (en) | 2000-03-02 |
| JP2002523854A (en) | 2002-07-30 |
| EP1105876A1 (en) | 2001-06-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| 17P | Request for examination filed |
Effective date: 20001201 |
|
| AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE FR GB NL |
|
| A4 | Supplementary search report drawn up and despatched |
Effective date: 20030806 |
|
| RIC1 | Information provided on ipc code assigned before grant |
Ipc: 7G 01R 31/3193 B Ipc: 7G 01R 31/3187 A |
|
| 17Q | First examination report despatched |
Effective date: 20031104 |
|
| GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
| 18D | Application deemed to be withdrawn |
Effective date: 20050826 |