JP2002522920A - 集積回路トレンチ構造およびその作製方法 - Google Patents

集積回路トレンチ構造およびその作製方法

Info

Publication number
JP2002522920A
JP2002522920A JP2000565562A JP2000565562A JP2002522920A JP 2002522920 A JP2002522920 A JP 2002522920A JP 2000565562 A JP2000565562 A JP 2000565562A JP 2000565562 A JP2000565562 A JP 2000565562A JP 2002522920 A JP2002522920 A JP 2002522920A
Authority
JP
Japan
Prior art keywords
nanocrystals
wafer
nanocrystal
copper
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000565562A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002522920A5 (enExample
Inventor
エイヴァリー エヌ ゴールドスタイン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of JP2002522920A publication Critical patent/JP2002522920A/ja
Publication of JP2002522920A5 publication Critical patent/JP2002522920A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2000565562A 1998-08-14 1999-08-13 集積回路トレンチ構造およびその作製方法 Pending JP2002522920A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US9661698P 1998-08-14 1998-08-14
US60/096,616 1998-08-14
US09/373,295 1999-08-12
US09/373,295 US6277740B1 (en) 1998-08-14 1999-08-12 Integrated circuit trenched features and method of producing same
PCT/US1999/018430 WO2000010197A1 (en) 1998-08-14 1999-08-13 Integrated circuit trenched features and method of producing same

Publications (2)

Publication Number Publication Date
JP2002522920A true JP2002522920A (ja) 2002-07-23
JP2002522920A5 JP2002522920A5 (enExample) 2006-09-21

Family

ID=26791884

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000565562A Pending JP2002522920A (ja) 1998-08-14 1999-08-13 集積回路トレンチ構造およびその作製方法

Country Status (5)

Country Link
US (3) US6277740B1 (enExample)
JP (1) JP2002522920A (enExample)
KR (1) KR100653337B1 (enExample)
AU (1) AU5560499A (enExample)
WO (1) WO2000010197A1 (enExample)

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US6855202B2 (en) 2001-11-30 2005-02-15 The Regents Of The University Of California Shaped nanocrystal particles and methods for making the same
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JPH04134827A (ja) * 1990-09-27 1992-05-08 Toshiba Corp 半導体装置の製造方法
JPH0578107A (ja) * 1991-09-19 1993-03-30 Yoshikiyo Ogino 窒化物粉体
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JPH09134891A (ja) * 1995-09-06 1997-05-20 Vacuum Metallurgical Co Ltd 半導体基板への薄膜形成方法

Also Published As

Publication number Publication date
US20020006723A1 (en) 2002-01-17
US6277740B1 (en) 2001-08-21
US20040023488A1 (en) 2004-02-05
AU5560499A (en) 2000-03-06
KR20010072473A (ko) 2001-07-31
WO2000010197A1 (en) 2000-02-24
US6774036B2 (en) 2004-08-10
KR100653337B1 (ko) 2006-12-01

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