US20020006723A1 - Integrated circuit trenched features and method of producing same - Google Patents

Integrated circuit trenched features and method of producing same Download PDF

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US20020006723A1
US20020006723A1 US09934303 US93430301A US2002006723A1 US 20020006723 A1 US20020006723 A1 US 20020006723A1 US 09934303 US09934303 US 09934303 US 93430301 A US93430301 A US 93430301A US 2002006723 A1 US2002006723 A1 US 2002006723A1
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nanocrystals
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wafer
structure
solvent
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Avery Goldstein
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Nanospin Solutions
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Goldstein Avery N.
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The formation of microelectronic structures in trenches and vias of an integrated circuit wafer are described using nanocrystal solutions. A nanocrystal solution is applied to flood the wafer surface. The solvent penetrates the trench recesses within the wafer surface. In the process, nanocrystals dissolved or suspended in the solution are carried into these regions. The solvent volatilizes more quickly from the wafer plateaus as compared to the recesses causing the nanocrystals to become concentrated in the shrinking solvent pools within the recesses. The nanocrystals become stranded in the dry trenches. Heating the wafer to a temperature sufficient to sinter or melt the nanocrystals results in the formation of bulk polycrystalline domains. Heating is also carried out concurrently with nanocrystals solution deposition. Copper nanocrystals of less than about 5 nanometers are particularly well suited for formation of interconnects at temperatures of less than 350 degrees Celsius.

Description

    RELATED APPLICATIONS
  • This application is a continuation-in-part of patent application Ser. No. 09/373,295 filed Aug. 12, 1999, which claims the benefit of provisional patent application Ser. No. 60/096,616 which was filed Aug. 14, 1998 and is hereby incorporated by reference.[0001]
  • FIELD OF THE INVENTION
  • The present invention relates to microelectronic trenched feature formation and more particularly to the formation of an interconnect from a nanocrystal solution. [0002]
  • BACKGROUND OF THE INVENTION
  • An integrated circuit requires conductive interconnects between semiconducting domains in order to communicate signals therebetween. In order to create ever faster microprocessors, smaller dimension interconnects of higher conductivity materials is an ongoing goal. [0003]
  • As microelectronic efficiencies have increased, interconnects have decreased in dimensional size and efforts have been made to increase the electrical conductivity of interconnect features. There is an ongoing need for ever smaller interconnects. [0004]
  • The rapid miniaturization of interconnects is occurring simultaneously with the transition from Al to Cu metallization for sub-0.25 μm ICs. The transition from Al to Cu has led to a change in the way interconnects are formed. While Al has been deposited as a blanket layer which is then patterned by reactive ion etching, Cu interconnects are formed by evaporative deposition into preformed (damascene) trenches and vias followed by chemical mechanical polishing (CMP). [0005]
  • As the interconnect width decreases and the aspect ratio increases, conventional vacuum deposition techniques approach the theoretical resolution threshold. Deep, narrow trenches and vias preferentially collect material at the damascene feature edges, leading to void formation. Blanket and selective chemical vapor deposition (CVD) are well-established Cu deposition techniques that have a demonstrated ability to fill current interconnect trenches. (A. E. Kaloyeros and M. A. Fury, [0006] MRS Bull. (June 1993), pp. 22-29).
  • Nonetheless, CVD does not inherently fill trenches preferentially over any other portion of substrate having nucleation sites. Unlike CVD, the proposed method preferentially deposits Cu into trenches based on differential solvent evaporation associated with trenches and as such is expected to work better, the narrower the trench width and higher the aspect ratio. Additionally, heating of the IC substrate during CVD to assure crystalline growth degrades fine architecture structures on the substrate. Thus, the semiconductor industry is in need of an interconnect formation process capable of achieving higher resolution at lower temperature and ideally, at a lower cost. [0007]
  • The mesoscopic size regime between atoms and bulk materials is characterized by unusual properties. Mesoscopic systems exhibit collective atomic behavior, but not to a sufficient extent so as to preclude quantized effects. Many of the unusual thermodynamic and spectroscopic anomalies associated with mesoscopic systems are attributable to surface effects. Studies have shown surface energies that are 10 to 400% greater for nanocrystals than for bulk Au and Pt (C. Solliard and M. Flueli, [0008] Surf. Sci. 156 (1985), pp. 487-494), and Al (J. Wolterdorf, A. S. Nepijko and E. Pippel, Surf. Sci. 106 (1981), pp. 64-72). In the bulk, surface atoms represent such a small percentage of the total that surface effects are largely inconsequential. Surfaces generally possess modified atomic coordination numbers, geometries and diminished lattice energies relative to the bulk. The result of these modifications is that physical, spectroscopic, and thermodynamic properties, which are constant in the bulk, become size dependent variables in nanocrystals. The ability to modify the thermodynamic properties of nanocrystals, particularly the melting temperature, is exploited in the present invention to produce thin film IC structures at low temperature.
  • Metallic nanocrystals have been shown to reduce melting temperatures compared with the bulk. (Ph. Buffat and J-P. Borel, [0009] Phys. Rev. A, 13 (1976), pp. 2287-2298; C. J. Coombes, J. Phys. 2 (1972), pp. 441-449; J. Eckert, J. C. Holzer, C. C. Ahn, Z. Fu and W. L. Johnson, Nanostruct. Matls. 2 (1993), pp. 407-413; C. R. M. Wronski, Brit. J. Appl. Phys. 18 (1967), pp. 1731-1737 and M. Wautelet, J Phys. D, 24 (1991), pp. 343-346). The depression in melting and annealing temperature is evident throughout the nanocrystal size regime, with the most dramatic effects observed in nanocrystals having a diameter from 2 to 6 nm. Melting studies on a range of nanocrystals have established that the melting temperature is size dependent in the nanometer size regime and is approximately proportional to the inverse particle radius regardless of the material identity. The size dependent melting temperature of metallic nanocrystals has included studies of Au, Pb and In, Al and Sn. (Au: Ph. Buffat and J-P. Borel, Phys. Rev. A, 13 (1976), pp. 2287-2298; Pb and In: C. J. Coombes, J. Phys. 2 (1972), pp. 441-449; Al: J. Eckert, J. C. Holzer, C. C. Ahn, Z. Fu and W. L. Johnson, Nanostruct. Matis 2 (1993), pp. 407-413; and Sn: C. R. M. Wronski, Brit. J. Appl. Phys. 18 (1967), pp. 1731-1737). The reduction in melting temperature as a function of nanocrystal size can be enormous. For example, 2 nm Au nanocrystals melt at about 300 degrees Celsius, as compared to 1065 degrees Celsius for bulk gold. (M. Wautelet, J. Phys. D, 24 (1991), pp. 343-346).
  • SUMMARY OF THE INVENTION
  • A method is described for producing a structure including the application of a solvent containing metal or semiconductor nanocrystals to a wafer having a trench cut therein. The nanocrystals having a diameter of between 1 and 20 nanometers. Heating the nanocrystals to form a continuous polycrystalline domain from the nanocrystals within the trench. The nanocrystals are applied alternatively as a coating overlying trench features, with the nanocrystal wicking into the features upon heating or by direct coating into features. The nanocrystals are preferably copper nanocrystals when the structure is destined to form an interconnect. A microelectronic structure is also formed including nanocrystalline domains in electrical contact with one another, said domains formed to an existing recess within a wafer substrate. The use of nanocrystals to form microelectronic structures in an existing recess within a wafer substrate is also taught. [0010]
  • DETAILED DESCRIPTION OF THE INVENTION
  • A method is detailed herein which uses a damascene process to create interconnects from nanocrystalline precursors materials. While the present invention is not limited to a particular metal, or metallic cation-containing compound such as an oxide, nitride, phosphide, or intermetallic, it is particularly well suited for the efficient formation of copper interconnects at temperatures below 400 degrees Celsius and even below 300 degrees Celsius. A silicon wafer that has been patterned by lithography and etched to form a series of trenches is the substrate for the instant invention the exposed surface of which also contains SiO[0011] 2. It is appreciated that an intermediate wetting layer is optionally applied to the substrate to promote interconnect wetting thereof and to prevent interdiffusion during subsequent IC processing.
  • The present invention identifies significant cost efficiencies based on the deposition characteristics of nanocrystal-based construction of electronic devices. The nanocrystal solutions or suspensions are applied by spray or spin coating onto a trenched integrated circuit (IC) wafer. The present invention supplants expensive vacuum evaporation equipment with a paint booth or spin coating technology for the formation of integrated circuitry interconnect structures. Unlike chemical and physical vapor deposition techniques, the present invention selectively deposits nanocrystal particulate in the IC trenches by taking advantage of the slower volatilization of a solvent carrier from trenches, causing the nanocrystals to congregate in high aspect ratio features. As a result, the quantity of extraneous deposition material, which must be removed by CMP, is diminished. Lastly, an environmental benefit results from pre-selecting aqueous and or benign organic solvents the nanocrystal solution, in place of solvents currently used in the chip manufacturing process. [0012]
  • The present invention also identifies cost savings associated with production defects. Nanocrystal deposition of interconnects is both reversible and repairable. Poor deposition technique is corrected by resolubilizing nanocrystals stranded on a trenched IC substrate by solvent washing prior to sintering the nanocrystals. Further, trench regions showing incomplete filling or separation from the trench walls can be remedied after sintering or melting to form bulk material interconnect features through the reapplication of a nanocrystal solution. Because the solvent containing the nanocrystals can freely penetrate fissures and voids associated with an IC patterned for an interconnect, additional nanocrystals are deposited into poorly filled regions. [0013]
  • A nanocrystal solution is applied to flood the wafer surface. The solvent penetrates the trench recesses within the wafer surface, including those shadowed or otherwise obscured from evaporative methods. In the process nanocrystals dissolved or suspended in the solution are carried into these regions. The solvent volatilizes more quickly from the wafer plateaus as compared to the recesses causing the nanocrystals to become concentrated in the shrinking solvent pools within the recesses. The nanocrystals become stranded in the dry trenches. Heating the wafer to a temperature sufficient to sinter or melt the nanocrystals results in the formation of bulk polycrystalline domains. [0014]
  • In the case of many technologically important interconnect materials such as copper, the intermediate layer is illustratively a layer of TiN or TaN having a sufficient thickness to assure continuity. Other such intermediate layers are formed by evaporation of a base metal layer onto the trenched substrate and thereafter exposing the base metal layer to a nitrogen plasma to induce a surface nitriding as is conventional to the art. [0015]
  • A solution of dissolved or suspended nanocrystals is applied to the contoured surface of the wafer. Preferably, the nanocrystal solution or suspension is concentrated to opaqueness to facilitate rapid deposition of interconnect structures. Following the evaporation of the solvent, adjacent particles are heated to form bulk domains within the trenches. Extraneous nanocrystal material is removed from exposed surfaces by conventional wafer polishing techniques subsequent to heating such as ultrasonic cleaning, touch up chemical mechanical polishing or a reverse chemical vapor deposition process to form a volatile organometallic product impregnated lint-free cloth prior to heating. [0016]
  • The solvent utilized to form the solution is optionally aqueous or organic. The solvent is chosen based on factors including, but not limited to hydrophilicity of the wafer surface, solubility of the nanocrystals therein, vapor pressure, toxicity, purity and the like. [0017]
  • The nanocrystal is defined as a particle having a linear dimension in any direction on the order of nanometers, namely 1 to 100 nm in diameter. Preferably, the nanocrystal of the present invention is between 1.5 and 20 nm. More preferably, the nanocrystal of the present invention is between 1.5 and 10 nm. The size distribution of the nanocrystals in solution is of some importance, since the sintering temperature of particles in this size regime is size dependent. Likewise, the melting temperature is size dependent. Preferably, a size distribution of less than 30% of the average particle diameter is used for nanocrystals of an average diameter of less than about 6 nm with increasingly greater tolerances being preferred as the average particle increases beyond 6 nm. Alternatively, smaller nanocrystals having a lower melting temperature form a flux that facilitates uniform melting of larger nanocrystals within the distribution. The nanocrystals are optionally either dispersed in a solvent by conventional means illustratively including sonication, agitation, solution shearing and the like; or the nanocrystal surface is coupled to a passivating agent by adsorption or chemically bonding thereto. The passivating agent preferably being soluble in the solvent and thus imparting solubility to the particles. Preferably, the nanocrystals are soluble to promote segregation into low volatilization rate, trench and via regions as compared to wafer plateaus. More preferably, the nanocrystals are copper for the formation of an interconnect. [0018]
  • The passivating agent is introduced to prevent nanocrystal growth beyond a pre-selected size and preferably to also impart solubility on the nanocrystal in a solvent. The passivating agent illustratively includes a variety of thermally volatile organics including those of the formula XRY where X is a moiety capable of chemically bonding to a surface atom of the nanocrystal and illustratively includes alcohol, amine, carboxylate, ketone, thiol, imide, amide, sulfonyl, nitryl, aldehyde, and phosphorus containing moieties; R is C[0019] 1-C30 aliphatic, aryl or heteroatom substituted derivative thereof and Y is X or hydrogen. The RY portion of the passivating agent is optionally chosen to interact with the solvent to impart solubility. In another embodiment, Y bonds to the surface of a second nanocrystal to tether nanocrystals together. Further, dendritic or polymeric variants of XRY are operative to form an extended matrix of nanocrystals. Preferably, the passivating agent is a linear C2-C24 alkane-thiol, amine, carboxylate or phosphorus-containing moiety. The nanocrystal surface binding passivating agent moiety being dictated by established organometallic chemistry.
  • The nanocrystal size is selected to take advantage of size dependent sintering and melting temperatures. The stability of the underlying wafer architecture is typically the controlling factor in determining optimal melting temperature and thus nanocrystal size. Preferably, nanocrystals are selected having a maximal heating requirement to obtain desired electrical conductivities from the resulting bulk structure of less than about 350 degrees Celsius. More preferably, the nanocrystals are heated to less than 300 degrees Celsius. The melting temperature of various sizes of nanocrystals is calculable (Wautelet, [0020] J. Phys. D, 24 (1991), p. 343).
  • Nanocrystals are applied to the wafer by applying the solution thereto. Layering a solution of the instant invention onto a wafer is operative. Preferably, the solution is applied in such a way as to promote uniform deposition of the nanocrystals across whole wafers, such methods illustratively include atomizing the solution and applying as a fine nanocrystal paint spray; and spin coating the solution onto a rotating wafer. Optionally, a binder is dispersed in the solution to minimize particle movement as the solvent pool evaporates. A binder useful in the present invention includes low molecular weight and polymeric organic substances. The binder being chosen such that upon heating to a temperature of less than about 250 to 300 degrees Celsius, the binder is volatilized. The binder is chosen to minimize binder residues, the residues likely to decrease conductivity of the bulk domain resulting from heating the nanocrystals. Binders illustratively include waxes; aliphatic compounds containing at least eight carbon atoms including carboxylic acids alcohols, aldehydes, amines, thiols and salt thereof wherein the cation is a conductive metal ion illustratively including copper aluminum, magnesium, gold, silver, manganese, molybdenum and the like; polymeric materials which volatilize to greater than 95% by weight below 250 degrees Celsius including poly (acrylic acid), polyglycols, polycarbonates, polyalkyls, polyalcohols, polyesters and the like; proteinaceous substrates such as albumin, gelatin and collagen; carbohydrates; and organosilanes. [0021]
  • It is appreciated that a binder is operative herein to increase the nanocrystal solution viscosity such that after solution application to the wafer substrate, a surface coating results which does not generally penetrate trenches and vias associated with the wafer substrate. A surface coating upon heating volatilizes the binder and nanocrystal passivating agent thereby causing the nanocrystals to be wicked into the wafer substrate trenches and vias so as to coat trench and via wall surfaces and initiate top to bottom wafer substrate feature fill. This inventive feature fill technique is particularly well suited for the formation of barrier layers and seed layers. [0022]
  • The nanocrystals of the instant invention are composed of any material that is conventionally used to create interconnect structures, intermediate layers or barrier structures in microelectronics. These materials illustratively include: aluminum, copper, gold, manganese, molybdenum, nickel, palladium, platinum, tin, zinc, tantalum, titanium and silver, alloys, oxides, nitrides and phosphides thereof. In addition, the instant invention is operative for the spin coating of semiconductors illustratively including indium antimonide; gallium indium antimonide; transition metal sulfides, selenides and tellurides; silicon; gallium arsenide and doped forms thereof. Silicon nanocrystal formation is illustratively detailed in U.S. Pat. No. 5,850,064; R. A. Bley et al., [0023] J. Am. Chem. Soc. 118 (1996), p. 12461; and K. P. Johnston et al., J. Am. Chem. Soc. 221st Meeting (2001) EIC-375. GaAs nanocrystals are formed as detailed in M. A. Olshavsky et al., J. Am. Chem. Soc. 112 (1990), p. 9438. Further, in instances where one wishes to create a metal-oxide-semiconductor (MOS) junction intermediate or barrier structures, nanocrystals of the metallic elements may be deposited and oxidized to positive oxidation state greater than zero by heating to a temperature of less than 500 degrees Celsius or subjecting the metal to a gaseous plasma in an atmosphere of the gaseous oxidant. The metallic elements being oxidized to form a variety of metal compounds including oxides, nitrides, and phosphides. Alternately, nanocrystals of the oxides are synthesized and stranded directly into IC wafer trenches and vias. It is appreciated that upon heating metallic nanocrystals in order to form conductive structures, it may be necessary to perform such heating under an inert or reducing atmosphere to prevent unwanted or undue oxidation. Nanocrystals of various compositions may be mixed together and heated to form intermetallic composition interconnects. Simultaneous sintering and or fusion of the differing composition nanocrystals are assured through the choice of particle sizes.
  • There are three temperature ranges important to the process of converting a trench of wafer filled with nanocrystals into an operative IC structure. The nanocrystal application temperature occurs at any temperature at which to solvent is liquid. It is appreciated that higher application temperature decreases the number of wafer surface sites a nanocrystal contacts prior to being stranded on a dry wafer. In a preferred embodiment, the nanocrystal surface is coated with a passivating agent that imparts solvent solubility to the nanocrystal. Upon heating a nanocrystal filled wafer above the passivating agent thermalization temperature, the passivating agent is volatilized allowing clean nanocrystal surfaces of contiguous nanocrystals into contact. While the passivating agent volatilization temperature is largely size independent and related to the chemisorption or physisorption energy between the passivating agent and the nanocrystal surface atoms, nanocrystal sintering and melting temperature are controllable over hundreds of degrees Celsius through nanocrystal size domain selection. Once the passivating agent is volatilized contiguous nanocrystals are able to sinter. [0024]
  • Sintering is defined as the interfacial coalescence of contiguous particles while the particle cores retain prior crystalline properties. Sintering temperature is calculable or approximated as two-thirds of the substance melting temperature in degrees Kelvin. Further, heating beyond the sintering temperature brings the nanocrystals to a size dependent melting temperature. Melting of a contiguous matrix of nanocrystals results in a densified polycrystalline bulk structure limiting the interfacial resistivity between sintered domains. [0025]
  • The present invention is capable of overcoming prior art limitations regarding dimensional shrinkage associated with densification, thin film instability through repetitive nanocrystal solution application. (K. T. Miller et al., [0026] J. Mater Res. 5 (1990), pp. 151-160; B. A. Korgel and D. Fitzmaurice, Phys. Rev. Let. 80 (1998), pp. 3531-3534; A. G. Evans et al., J. Mater. Res. 3 (1988), pp. 1043-1049).
  • Significant shrinkage is associated with passivating agent volatilization, thus after applying a nanocrystal solution to a wafer, the wafer is heated to the passivating agent volatilization temperature and additional nanocrystal solution applied to fill feature voids associated with volatilization. This process is optionally repeated prior to raising the wafer to a sintering of melting temperature for the nanocrystal mass filling a wafer trench or via. It is appreciated that nanocrystal deposition is optionally carried out at a temperature above the passivating agent volatilization temperature such that active nanocrystal surfaces are formed upon contact with a trenched wafer. [0027]
  • The relevant volatilization sintering and melting temperatures for a given nanocrystal solution are determinable through thermals analysis, techniques such as differential scanning calorimetry (DSC), thermal gravimetric analysis (TGA), temperature dependent spectroscopies and conductivity. [0028]
  • In another embodiment, the passivating agent is an electrically conductive polymer that electrically couples contiguous nanocrystals to one another obviating the need for passivating agent volatilization. [0029]
  • In instances where the interconnect is being deposited onto a silicon oxide surface other factors need to be considered. Metals often poorly wet oxide surfaces and thus an intermediate conventional adhesion-promoting layer is applied. In those instances where a hydrophobic solvent is used to coat a hydrophilic oxide surface, the solvent can be induced to wet the oxide surface by washing the wafer surface with a silanol or similar surfactant prior to deposition of the particle containing solvent. The silanol wash creates a thin layer that projects organic functionalities away from the surface which attractively interact with the particle surfaces of hydrophobic particles and simultaneously bonds to the oxide surface through the hydroxyl functionality. It is appreciated that other adhesion promoters known to the art of laminating non-wettable oxide and metallic layers are operative herein under the disclosed thermal conditions. [0030]
  • In order to fill a trench with a conductive interconnect, there must be enough particles present such that the particles as deposited are at or above the percolation threshold. The percolation threshold is defined herein as a spatial density of particles sufficient to traverse the region through at least one continuous pathway of contiguous particles. To assure percolation threshold attainment and therefore conductivity upon sintering or fusing the particles, a trench feature is preferably at least 7 particle widths in the directions parallel to the wafer surface. Thus, the instant invention is best utilized with trench features larger than about 7 nm. [0031]
  • In another embodiment of the present invention, an organometallic compound is applied to a wafer substrate, the organometallic compound containing a positive oxidation state metal ion complexed with a ligand containing a moiety capable of reducing the metal to a zero oxidation state upon ligand decomposition. Operative ligand moieties capable of reducing metal ions illustratively include hydrazines, azides, diazoles, triazoles, thiazoles and polyols. Specifically, hydrazine carboxylate and substituted forms thereof are bidentate ligands well suited to complex metals illustratively including copper, silver and gold. Copper bis hydrazine carboxylate decomposes upon heating to yield gaseous byproducts and copper metal. Hydrazine carboxylate substituents include replacing a hydrazine proton with C[0032] 1-C8 alkyl, cycloalkyl, alkenyl, cycloalkenyl and variants thereof having solubility imparting moieties illustratively including hydroxyl amine and carboxyl groups. A process for application of a reductant containing organometallic compound includes forming a solution or suspension of the reductant containing organometallic compound in a solvent suitable for spin coating. The suspension or solution is applied to a trenched wafer substrate with simultaneous or subsequent wafer heating to a temperature sufficient to decompose the reductant containing organometallic compound to induce formation of zero oxidation state metal and volatilization of ligand byproducts. In order to accommodate removal of gaseous ligand byproducts, it is appreciated that organometallic compound decomposition is preferably performed repeatedly to build up a densified feature fill.
  • A reductant containing organometallic compound preferably has a decomposition temperature to form zero oxidation state metal of between 50 and 200 degrees Celsius. Thermolysis of the organometallic compound is provided by induction heating, photolysis, sonication, laser ablation and introduction of a heated gas stream.[0033]
  • Having described the inventions, the following illustrative examples are provided which are not intended to limit the scope of the invention. [0034]
  • EXAMPLE 1
  • A solution of 3 nm gold nanocrystals passivated with dodecanethiol are synthesized using the method of Leff et al., [0035] J. Phys. Chem. 99 (1995), p. 7036. The gold particles are redissolved in toluene and the toluene solution pipetted onto a trenched silicon wafer having a silicon dioxide surface and a 50 nm layer of TiN over 100 nm of Ti and trench widths of from 5 microns to 0.2 microns. The solution is reddish-black in color and leaves a black film on the wafer following solvent evaporation. The wafer is then allowed to air dry and then heated in air for 2 hours at 300 degrees Celsius. Upon heating the black film of gold nanocrystals takes on a metallic yellowish hue of bulk gold. The surface shows no traces the dodecanethiol passivating agent as determined by X-ray Photospectroscopy (XPS). The gold is observed to be preferentially deposited in the trenches, as compared to the wafer upper surface.
  • EXAMPLE 2
  • The procedure of Example 1 is repeated with the particles dissolved in hexane in place of toluene, with similar results. [0036]
  • EXAMPLE 3
  • The nanocrystals of Example 1 are spun coated at 300 rpm onto a rotating trenched wafer. Upon light reflectance associated with the wafer trench pattern being obscured by the black nanocrystal deposits thereon, the wafer is heated to 150 degrees Celsius for 20 minutes. Greater than 99.9% of the dodecanethiol is observed to volatilize according to TGA. Additional nanocrystal solution is applied to the wafer. Following drying, the wafer is heated to 300 degrees Celsius resulting in complete filling of the wafer trenches with bulk gold features. Few isolated gold domains are observed on the wafer plateau. [0037]
  • EXAMPLE 4
  • The procedure of Example 3 is repeated after dissolving one part by weight of paraffin in the nanocrystal solution per 50 parts toluene. The solution is atomized onto the wafer and allowed to dry. Upon heating as above, a more uniform distribution of particles across the wafer plateau and trenches is noted. [0038]
  • EXAMPLE 5
  • The procedure of Example 3 is repeated with copper nanocrystals made by a preparation analogous to Leff et al. with copper (II) chloride used in place of hydrogen tetrachloroaurate and the amine substituted for the thiol. The particles are synthesized in batches having average sizes ranging from 1.5 to 6 nm by adjusting the molar ratio to passivating molecule to copper. The copper particles are heated in a reducing atmosphere of 10% hydrogen and 90% nitrogen at 300 degrees Celsius for 2 hours. A metallic sheen characteristic of bulk copper is observed. [0039]
  • EXAMPLE 6
  • Copper nanocrystals and silver nanocrystal of 3 and 3.5 nm, respectively, are made as per A. Manna et al., [0040] Chem. Mater. 9 (1997), pp. 3032-3036. The nanocrystals are mixed with 3 nm Au nanocrystals to an Au: Cu: Ag total weight ratio of 7:78:15 and dissolved in hexane. The nanocrystal is spray coated using a paint sprayer onto a trenched wafer, prior to heating to 350 degrees Celsius. The wafer features are wholly filled with metal having a resistivity consistent with literature values.
  • EXAMPLE 7
  • The procedure of Example 3 is repeated with the nanocrystal solution applied to a wafer heated to 150 degrees Celsius. Following solution application, the wafer is heated to 350 degrees Celsius to yield a bulk gold interconnects in the wafer trenches. [0041]
  • EXAMPLE 8
  • The procedure of Example 7 is repeated with the nanocrystal solution applied to a wafer at 350 degrees Celsius. Bulk gold is observed coating the plateau and trenches uniformly. [0042]
  • EXAMPLE 9
  • A solution of 3 nm copper nanocrystals was synthesized as per Lisecki et al., [0043] J. Phys. Chem. 99 (1995), pp. 5077-5082 with the addition of pyridine in a stoichiometric molar ratio of greater than 3:1 relative to copper. The resulting copper nanocrystals are collected on filter paper and dissolved in pyridine. The concentrated pyridine solution containing copper nanocrystals is applied to a trenched wafer surface by spin coating resulting in the formation of a surface overcoating having a thickness of about 100 nm and characterized by limited trench and via penetration. Heating the sample to 150 degrees Celsius is sufficient to drive off the pyridine passivating coat yet is too low a temperature to sinter or otherwise cause particle fusion. The overcoating layer is observed to thin as the material is wicked into wafer features. Continued heating to 280 degrees Celsius results in isolated islands of copper metal on the wafer surface and a uniform coating of wafer trench and via features walls and bottoms with a copper film having a thickness of about 20 nm. Excess copper beyond that needed to coat feature walls is noted to bottom fill the features.
  • EXAMPLE 10
  • The process of Example 9 is repeated using the gold nanocrystals of Example 1. A gold seed layer and bottom feature fill is noted. [0044]
  • EXAMPLE 11
  • Copper hydrazine carboxylate is synthesized as per Dhas et al., [0045] Chem. Mater. 10 (1990), pp. 1446-1452. 300 mg of copper hydrazine carboxylate is dissolved in 100 ml of distilled water and applied by spin coating to a trenched wafer surface. Exposing the coating of copper hydrazine carboxylate to the electron beam of a scanning electron microscope induced reduction to form copper metal and gaseous organic byproducts preferentially within wafer features. Parallel coated wafer samples were also heated in 5% hydrogen with a nitrogen carrier gas to 100 degrees Celsius to also yield copper metal preferentially within wafer features.
  • EXAMPLE 12
  • The procedure of Example 10 is repeated with the substitution of dimethyl hydrazine carboxylate for copper hydrazine carboxylate. Dodecane also replaced the water of Example 11 as the spin coating solvent, with comparable results being obtained. [0046]
  • EXAMPLE 13
  • A 5% solution by weight of hexane soluble silicon nanocrystals is applied by spin coating onto a rotating trenched wafer. The silicon nanocrystals having an average size of 2 nm. The wafer is then heated to 350 degrees Celsius to form silicon filled wafer features with an aspect ratio of greater than 3. Stranded silicon domains observed on wafer plateaus are removed by chemical mechanical polishing. [0047]
  • It is appreciated that various modification of the present invention in addition to those shown and described herein will be apparent to those skilled in the art from the above description. Such modifications are also intended to fall within the scope of the appended claims. [0048]
  • All references cited herein are intended to be incorporated by reference to the same extent as if each was individually and explicitly incorporated by reference. [0049]

Claims (39)

  1. 1. A method for producing a structure comprising the steps of:
    applying a solvent comprising semiconductor nanocrystals dissolved therein to a wafer having a feature cut therein, said nanocrystals having a diameter of between 1.5 and 20 nanometers; and
    heating said wafer to form a continuous polycrystalline domain from said nanocrystals within said trench.
  2. 2. The method of claim 1 wherein said nanocrystals are composed of a material selected from the group consisting of: indium antimonide; gallium indium antimonide; transition metal sulfides, selenides and tellurides; silicon; gallium arsenide and doped forms thereof.
  3. 3. The method of claim 1 wherein said solvent further comprises a binder.
  4. 4. The method of claim 1 wherein applying and heating are performed simultaneously.
  5. 5. The method of claim 1 wherein said nanocrystals are copper.
  6. 6. The method of claim 1 wherein said continuous polycrystalline domain comprises sintered nanocrystals.
  7. 7. The method of claim 1 wherein said continuous polycrystalline domain comprises melted nanocrystals.
  8. 8. The method of claim 1 wherein said wafer is heated to less than 350 degrees Celsius.
  9. 9. A method of producing a microelectronic structure comprising the steps of:
    applying a plurality of nanocrystals in a solvent to a wafer having a trench cut therein to form a coating over the trench; and
    heating said wafer to wick said nanocrystals into the trench.
  10. 10. The method of claim 9 wherein applying and heating are performed simultaneously.
  11. 11. The method of claim 9 wherein applying said solution involves spin coating.
  12. 12. A method of producing a structure comprising the steps of:
    applying an organometallic compound having a positive oxidation state metal ion and a reductant containing ligand in a solvent to a wafer having a feature cut therein; and
    decomposing said organometallic compound to yield a zero oxidation state metal within the feature and volatile organic byproducts.
  13. 13. The method of claim 12 wherein said organometallic compound is an organo copper compound.
  14. 14. The method of claim 13 wherein the organo copper compound has the oxidation state of 1+ or 2+.
  15. 15. The method of claim 12 wherein the ligand comprises a moiety selected from the group consisting of: hydrazine, hydride, azide, azole, diazole, triazole and thiazole.
  16. 16. The method of claim 12 wherein the ligand is a hydrazine carboxylate.
  17. 17. The method of claim 12 wherein the decomposition step is thermal.
  18. 18. The method of claim 12 wherein the decomposition step is photolytic.
  19. 19. A microelectronic intermediate structure comprising:
    nanocrystalline domains of a material selected from the group consisting of metal and semiconductor having melting temperatures of less than 350 degrees Celsius having organic molecules preventing contact between said nanocrystalline domains in a coating overlying wafer features.
  20. 20. The structure of claim 19 wherein said domains having dimension of 2 to 10 nanometers.
  21. 21. The structure of claim 19 wherein said domains comprise an element or compound selected from the group consisting of: aluminum, copper, gold, tantalum, titanium, silver, silicon, gallium arsenide, and transition metal sulfides.
  22. 22. The structure of claim 19 wherein said domains comprise copper.
  23. 23. The use of passivated semiconductor nanocrystals to form a microelectronic structure in an existing recess within a wafer substrate.
  24. 24. The use of claim 23 wherein said nanocrystals are silicon.
  25. 25. A method for producing a structure comprising the steps of:
    applying a solvent comprising semiconductor containing nanocrystals to a wafer having a trench cut therein, said nanocrystals having a diameter of between 1 and 20 nanometers; and
    heating said wafer to less than 350 degrees Celsius form a continuous polycrystalline domain from said nanocrystals within said trench.
  26. 26. The method of claim 25 wherein said nanocrystals are composed of a material selected from the group consisting of: silicon, gallium arsenide, indium antimonide, and transition metal sulfides, -selenides and -tellurides.
  27. 27. The method of claim 25 wherein said nanocrystals dissolved in said solvent.
  28. 28. The method of claim 25 wherein said solvent further comprises a binder.
  29. 29. The method of claim 25 wherein applying and heating are performed simultaneously.
  30. 30. The method of claim 25 wherein heating is performed under a gaseous atmosphere to inhibit compound semiconductor disproportionation.
  31. 31. The method of claim 25 wherein said nanocrystals are silicon.
  32. 32. The method of claim 25 wherein said continuous polycrystalline domain comprises sintered nanocrystals.
  33. 33. The method of claim 26 wherein said continuous polycrystalline domain comprises melted nanocrystals.
  34. 34. A microelectronic intermediate structure comprising:
    passivated semiconductor nanocrystalline domains filling an existing recess within a wafer substrate.
  35. 35. The structure of claim 34 wherein said domains have dimension of 1 to 10 nanometers.
  36. 36. The structure of claim 34 wherein said domains comprise an element or compound selected from the group consisting of: silicon, gallium arsenide, indium antimonide, and transition metal sulfides, -selenides and -tellurides.
  37. 37. The structure of claim 34 wherein said domains comprise silica.
  38. 38. The use of semiconductor nanocrystals having a melting temperature less than 350 degrees Celsius to form a microelectronic structure in an existing recess within a wafer substrate.
  39. 39. The use of claim 38 wherein said nanocrystals are silica.
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WO2000010197A1 (en) 2000-02-24 application

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