JP2002507362A - 多層ネットワーク要素のためのシステムおよび方法 - Google Patents
多層ネットワーク要素のためのシステムおよび方法Info
- Publication number
- JP2002507362A JP2002507362A JP50565699A JP50565699A JP2002507362A JP 2002507362 A JP2002507362 A JP 2002507362A JP 50565699 A JP50565699 A JP 50565699A JP 50565699 A JP50565699 A JP 50565699A JP 2002507362 A JP2002507362 A JP 2002507362A
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- 238000000034 method Methods 0.000 title claims description 38
- 230000015654 memory Effects 0.000 claims abstract description 163
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/60—Software-defined switches
- H04L49/602—Multilayer or multiprotocol switching, e.g. IP switching
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services
- H04L49/205—Quality of Service based
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3009—Header conversion, routing tables or routing tags
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/35—Switches specially adapted for specific applications
- H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.パケットが入力ポートでネットワーク要素に入り、適切な出力ポートがある 場合に適切な出力ポートでネットワーク要素から出ていく、少なくとも1つの入 力ポートと少なくとも1つの出力ポートとを有するネットワーク要素に入来する パケットの中継決定を行う方法であって、 (1)パケットの第1のヘッダ部分を受け取るステップと、 (2)前記第1のヘッダ部分から第1のサーチ・キーを判断するステップと、 (3)前記第1のサーチ・キーに関連づけられた第1の中継情報をメモリから 出力させるステップと、 (4)前記パケットの第2のヘッダ部分を受け取るステップと、 (5)前記第2のヘッダ部分に基づいて前記パケットのクラス情報を判断する ステップであって、各クラス情報は、クラスと、前記第2のヘッダ部分のどのフ ィールドを第2のサーチ・キーの作成に使用すべきかを示す第2のヘッダ・キー 情報と、前記クラスに分類されるパケットのデフォルト中継情報とを含むステッ プと、 (6)前記第2のヘッダ部分キー情報に基づいて前記第2のヘッダ部分から前 記第2のサーチ・キーを作成するステップと、 (7)前記第2のサーチ・キーに関連づけられた第2の中継情報がある場合は 前記の第2の中継情報をメモリから出力させるステップと、 (8)前記適切な出力ポートがある場合は、前記第1の中継情報と前記第2の 中継情報と前記デフォルト中継情報とに基づいて前記適切な出力ポートを判断す るステップと を含む方法。 2.ステップ(3)が、前記第1の宛先に応じて、前記メモリ内の対応する内容 に前記第1の中継情報が記憶されている第1のアドレスを判断するステップを含 み、 ステップ(7)が、前記第2のキーに応じて、前記メモリ内の対応する内容に 前記第2の中継情報が記憶されている第2のアドレスを判断するステップを含む 、請求項1に記載の方法。 3.前記第1のアドレスを判断するステップが、前記第1の宛先アドレスを使用 して内容アドレス・メモリをサーチし、前記第1のアドレスを生成するステップ と、 前記第2のアドレスを判断するステップが、前記サーチ・キーを使用して前記 内容アドレス・メモリをサーチし、前記第2のアドレスを生成するステップを含 む請求項2に記載の方法。 4.第1の中継情報を記憶する第1のメモリおよび第2の中継情報を記憶する第 2のメモリとして前記メモリを設けるステップをさらに含む請求項2に記載の方 法。 5.前記内容アドレス・メモリを前記第1のアドレスを記憶する第1の内容アド レス・メモリと前記第2のアドレスを記憶する第2の内容アドレス・メモリとし て構成するステップをさらに含む、請求項3に記載の方法。 6.前記第1のアドレスを判断するステップが、前記第1の宛先に対してハッシ ュ機能を使用して前記第1のアドレスを生成するステップを含み、 前記第2のアドレスを判断するステップが前記サーチ・キーに対してハッシュ 機能を使用して前記第2のアドレスを生成するステップを含む請求項2に記載の 方法。 7.前記第1の中継情報がそのように指示する場合、ステップ(8)が前記第1 の中継情報のみを使用して実行される請求項1に記載の方法。 8.前記第2の中継情報がそのように指示する場合、ステップ(8)が前記第1 の中継情報のみを使用して実行される請求項1に記載の方法。 9.前記第2のサーチ・キーが第2の中継情報を出力することができない場合、 ステップ(8)が前記第1の中継情報とデフォルト中継情報のみを使用して実行 される請求項1に記載の方法。 10.前記デフォルト中継情報がそのように指示し、しかも前記第2のサーチ・ キーが第2の中継情報を出力することができない場合、ステップ(8)が前記第 1の中継情報のみを使用して実行される請求項9に記載の方法。 11.ステップ(8)が前記第2の中継情報のみを使用して実行される請求項1 に記載の方法。 12.ステップ(8)が前記第1の中継情報と第2の中継情報との組合せを使用 して実行される請求項1に記載の方法。 13.前記第2の中継情報がサービス品質情報を含む請求項9に記載の方法。 14.前記サービス品質情報が前記パケットの優先順位を含む請求項13に記載 の方法。 15.少なくとも1つのネットワーク・ポートと少なくとも1つの出力ポートと を有するネットワーク要素への入力として供給され、入力ポートでネットワーク に入り、適切な出力ポートがある場合に1つまたは複数の適切な出力ポートで前 記ネットワーク要素から出ていく、ヘッダを有するパケットの中継決定を行う装 置であって、 前記ヘッダに基づいて、クラスと、前記ヘッダの各部分を識別するキー情報と 、前記クラスに分類されるパケットのデフォルト中継情報とを含む、前記パケッ トのクラス情報を出力するように構成されたクラス論理回路と、 前記ヘッダに基づいて第1のサーチ・キーと、前記ヘッダに基づいて、前記ク ラスと、前記キー情報と、第2のサーチ・キーとを出力するように構成されたサ ーチ論理回路と、 前記第1のサーチ・キーに応答して第1の中継結果を出力し、ある場合には前 記第2のサーチ・キーに応答して第2の中継結果を出力するように構成されたメ モリと、 前記デフォルト中継情報と、前記第1の中継結果と、前記第2の中継結果とに 応答して、適切な出力ポートに関する情報を出力するように構成されたマージ論 理回路と、 前記パケットを前記入力ポートから、前記適切な出力ポートに関する前記情報 に基づいて、適切な出力ポートがある場合には前記適切な出力ポートまで導く中 継論理回路とを含む装置。 16.前記メモリが、前記第1のサーチ・キーに応じて第1のアドレスを出力し 、前記第2のサーチ・キーに応じて第2のアドレスを出力するように構成された インタフェース論理回路を含み、 前記メモリが、前記第1のアドレスに応答して前記第1の中継結果を出力し、 前記第2のアドレスに応答して前記第2の中継結果を出力するように構成された 請求項15に記載の装置。 17.前記メモリが、前記第1のサーチ・キーを使用してアクセスされた場合に 第1の中継情報アドレスを出力し、前記第2のサーチ・キーを使用してアクセス された場合に第2の中継情報アドレスを出力するように構成された内容アドレス メモリと、 前記第1の中継情報アドレスを使用してアクセスされた場合に前記第1の中継 結果を出力し、前記第2の中継情報アドレスを使用してアクセスされた場合に前 記第2の中継アドレスを出力するように構成された中継メモリとを含む請求項1 5に記載の装置。 18.前記インタフェース論理回路が内容アドレス・メモリである請求項17に 記載の装置。 19.前記内容アドレスメモリが、 前記第1のサーチ・キーを使用してアクセスされた場合に前記第1の中継情報 アドレスを出力するように構成された第1の内容アドレス・メモリと、 前記第2のサーチ・キーを使用してアクセスされた場合に第2の中継情報アド レスを出力するように構成された第2の内容アドレス・メモリとを含む請求項1 8に記載の装置。 20.前記デフォルト中継情報と前記第2の中継結果がサービス品質情報を含む 請求項17に記載の装置。 21.前記マージ論理回路が、前記メモリが前記第2の中継結果を出力すること ができない場合、前記デフォルト中継情報および前記第1の中継結果のみを使用 して適切な出力ポートに関する情報を出力するように構成された請求項17に記 載の装置。 22.前記デフォルト中継情報がサービス品質情報を含む請求項21に記載の装 置。 23.前記クラス論理回路が、前記パケットに関するカプセル化情報に基づいて 前記ヘッダ内の場所を指すポインタを出力する少なくとも1つのカプセル化フィ ルタを含む請求項15に記載の装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/884,244 | 1997-06-30 | ||
US08/884,244 US6088356A (en) | 1997-06-30 | 1997-06-30 | System and method for a multi-layer network element |
PCT/US1998/013016 WO1999000948A1 (en) | 1997-06-30 | 1998-06-23 | A system and method for a multi-layer network elememt |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2002507362A true JP2002507362A (ja) | 2002-03-05 |
JP3842303B2 JP3842303B2 (ja) | 2006-11-08 |
Family
ID=25384250
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50565699A Expired - Lifetime JP3842303B2 (ja) | 1997-06-30 | 1998-06-23 | 多層ネットワーク要素のためのシステムおよび方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6088356A (ja) |
EP (1) | EP1005743B1 (ja) |
JP (1) | JP3842303B2 (ja) |
DE (1) | DE69825596T2 (ja) |
WO (1) | WO1999000948A1 (ja) |
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JP2003518873A (ja) * | 1999-12-28 | 2003-06-10 | モサイド・テクノロジーズ・インコーポレイテッド | パケットスイッチにおける転送オーバライド |
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JP2004362581A (ja) * | 2003-06-06 | 2004-12-24 | Microsoft Corp | マルチレイヤーファイアウォールアーキテクチャ |
JP2004362590A (ja) * | 2003-06-06 | 2004-12-24 | Microsoft Corp | ネットワークファイアウォールを実装するための多層ベースの方法 |
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JP4572089B2 (ja) * | 2003-06-06 | 2010-10-27 | マイクロソフト コーポレーション | マルチレイヤーファイアウォールアーキテクチャ |
Also Published As
Publication number | Publication date |
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EP1005743B1 (en) | 2004-08-11 |
EP1005743A1 (en) | 2000-06-07 |
DE69825596D1 (de) | 2004-09-16 |
DE69825596T2 (de) | 2005-09-29 |
US6088356A (en) | 2000-07-11 |
EP1005743A4 (en) | 2002-07-17 |
JP3842303B2 (ja) | 2006-11-08 |
WO1999000948A1 (en) | 1999-01-07 |
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