JP2002366447A5 - - Google Patents

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Publication number
JP2002366447A5
JP2002366447A5 JP2002126736A JP2002126736A JP2002366447A5 JP 2002366447 A5 JP2002366447 A5 JP 2002366447A5 JP 2002126736 A JP2002126736 A JP 2002126736A JP 2002126736 A JP2002126736 A JP 2002126736A JP 2002366447 A5 JP2002366447 A5 JP 2002366447A5
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JP
Japan
Prior art keywords
memory
memory controller
controller emulator
output
address information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002126736A
Other languages
English (en)
Japanese (ja)
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JP2002366447A (ja
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Publication date
Priority claimed from US09/848,019 external-priority patent/US6978352B2/en
Application filed filed Critical
Publication of JP2002366447A publication Critical patent/JP2002366447A/ja
Publication of JP2002366447A5 publication Critical patent/JP2002366447A5/ja
Withdrawn legal-status Critical Current

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JP2002126736A 2001-05-03 2002-04-26 メモリコントローラエミュレータ Withdrawn JP2002366447A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/848,019 US6978352B2 (en) 2001-05-03 2001-05-03 Memory controller emulator for controlling memory devices in a memory system
US09/848019 2001-05-03

Publications (2)

Publication Number Publication Date
JP2002366447A JP2002366447A (ja) 2002-12-20
JP2002366447A5 true JP2002366447A5 (enExample) 2005-09-08

Family

ID=25302123

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002126736A Withdrawn JP2002366447A (ja) 2001-05-03 2002-04-26 メモリコントローラエミュレータ

Country Status (3)

Country Link
US (1) US6978352B2 (enExample)
JP (1) JP2002366447A (enExample)
TW (1) TWI253651B (enExample)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
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US7188208B2 (en) * 2004-09-07 2007-03-06 Intel Corporation Side-by-side inverted memory address and command buses
US20060247905A1 (en) * 2005-04-29 2006-11-02 Vikas Agrawal System, method and apparatus for placing and routing
US7590796B2 (en) 2006-07-31 2009-09-15 Metaram, Inc. System and method for power management in memory systems
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US7609567B2 (en) * 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
WO2008063251A2 (en) * 2006-07-31 2008-05-29 Metaram, Inc. Memory circuit system and method
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US7392338B2 (en) 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US7580312B2 (en) 2006-07-31 2009-08-25 Metaram, Inc. Power saving system and method for use with a plurality of memory circuits
DE112006002300B4 (de) 2005-09-02 2013-12-19 Google, Inc. Vorrichtung zum Stapeln von DRAMs
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
DE202010017690U1 (de) * 2009-06-09 2012-05-29 Google, Inc. Programmierung von Dimm-Abschlusswiderstandswerten
US10121528B2 (en) * 2012-11-30 2018-11-06 Intel Corporation Apparatus, method and system for providing termination for multiple chips of an integrated circuit package
JP6910739B2 (ja) * 2018-03-05 2021-07-28 東芝情報システム株式会社 評価解析対象メモリ装置及びメモリ評価解析システム

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US6381715B1 (en) * 1998-12-31 2002-04-30 Unisys Corporation System and method for performing parallel initialization and testing of multiple memory banks and interfaces in a shared memory module

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