JP2002366447A - メモリコントローラエミュレータ - Google Patents

メモリコントローラエミュレータ

Info

Publication number
JP2002366447A
JP2002366447A JP2002126736A JP2002126736A JP2002366447A JP 2002366447 A JP2002366447 A JP 2002366447A JP 2002126736 A JP2002126736 A JP 2002126736A JP 2002126736 A JP2002126736 A JP 2002126736A JP 2002366447 A JP2002366447 A JP 2002366447A
Authority
JP
Japan
Prior art keywords
memory
output
data
address
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002126736A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002366447A5 (enExample
Inventor
B Reinhamu Michael
マイケル・ビー・レインハム
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2002366447A publication Critical patent/JP2002366447A/ja
Publication of JP2002366447A5 publication Critical patent/JP2002366447A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56004—Pattern generation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP2002126736A 2001-05-03 2002-04-26 メモリコントローラエミュレータ Withdrawn JP2002366447A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/848019 2001-05-03
US09/848,019 US6978352B2 (en) 2001-05-03 2001-05-03 Memory controller emulator for controlling memory devices in a memory system

Publications (2)

Publication Number Publication Date
JP2002366447A true JP2002366447A (ja) 2002-12-20
JP2002366447A5 JP2002366447A5 (enExample) 2005-09-08

Family

ID=25302123

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002126736A Withdrawn JP2002366447A (ja) 2001-05-03 2002-04-26 メモリコントローラエミュレータ

Country Status (3)

Country Link
US (1) US6978352B2 (enExample)
JP (1) JP2002366447A (enExample)
TW (1) TWI253651B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019153118A (ja) * 2018-03-05 2019-09-12 東芝情報システム株式会社 評価解析対象メモリ装置及びメモリ評価解析システム

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040201968A1 (en) * 2003-04-09 2004-10-14 Eric Tafolla Multi-bank memory module
US7188208B2 (en) * 2004-09-07 2007-03-06 Intel Corporation Side-by-side inverted memory address and command buses
US20060247905A1 (en) * 2005-04-29 2006-11-02 Vikas Agrawal System, method and apparatus for placing and routing
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US7609567B2 (en) * 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US7590796B2 (en) 2006-07-31 2009-09-15 Metaram, Inc. System and method for power management in memory systems
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US7392338B2 (en) 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US7580312B2 (en) 2006-07-31 2009-08-25 Metaram, Inc. Power saving system and method for use with a plurality of memory circuits
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
DE112006002300B4 (de) 2005-09-02 2013-12-19 Google, Inc. Vorrichtung zum Stapeln von DRAMs
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
DK3364298T3 (da) * 2006-07-31 2020-03-02 Google Llc System og fremgangsmåde til hukommelseskredsløb
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
DE202010017690U1 (de) * 2009-06-09 2012-05-29 Google, Inc. Programmierung von Dimm-Abschlusswiderstandswerten
EP3651154A1 (en) 2012-11-30 2020-05-13 INTEL Corporation Apparatus, method and system for providing termination for multiple chips of an integrated circuit package

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6381715B1 (en) * 1998-12-31 2002-04-30 Unisys Corporation System and method for performing parallel initialization and testing of multiple memory banks and interfaces in a shared memory module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019153118A (ja) * 2018-03-05 2019-09-12 東芝情報システム株式会社 評価解析対象メモリ装置及びメモリ評価解析システム

Also Published As

Publication number Publication date
US6978352B2 (en) 2005-12-20
US20020165706A1 (en) 2002-11-07
TWI253651B (en) 2006-04-21

Similar Documents

Publication Publication Date Title
JP2002366447A (ja) メモリコントローラエミュレータ
US10114073B2 (en) Integrated circuit testing
US8166361B2 (en) Integrated circuit testing module configured for set-up and hold time testing
KR100592648B1 (ko) 다중 모드형 동기식 메모리 소자 및 그 동작 및 검사 방법
US8427892B2 (en) Write strobe generation for a memory interface controller
CN101002390B (zh) 数字锁频延迟线
US20060253266A1 (en) Integrated circuit test array including test module
CN102467978B (zh) 半导体装置的输入/输出电路和方法及具有其的系统
KR100626375B1 (ko) 고주파로 동작하는 반도체 메모리 장치 및 모듈
US8001439B2 (en) Integrated circuit testing module including signal shaping interface
WO2006102241A1 (en) Integrated circuit testing module
KR20210034219A (ko) 신호 생성 회로 및 이를 이용하는 반도체 장치
US7365557B1 (en) Integrated circuit testing module including data generator
US6578180B2 (en) Method and system for testing interconnected integrated circuits
KR101082426B1 (ko) 클럭 생성 회로 및 클럭 생성 회로를 포함하는 테스트 시스템
JP3650757B2 (ja) 同期メモリ回路をテストするためのテスト回路
US7171611B2 (en) Apparatus for determining the access time and/or the minimally allowable cycle time of a memory
US7446551B1 (en) Integrated circuit testing module including address generator
KR100633455B1 (ko) 반도체 소자 테스터를 위한 신호 분배 장치
US20070041255A1 (en) System and method for injecting phase jitter into integrated circuit test signals
JP4041801B2 (ja) 半導体デバイス試験装置
US7549092B2 (en) Output controller with test unit
KR100794147B1 (ko) 반도체 소자 테스터 제어 장치
JP2001319494A (ja) メモリ回路用の組込み自己試験装置
KR100903384B1 (ko) 반도체 메모리 장치와 그의 구동 방법

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050310

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050310

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20070110