JP2003121506A5 - - Google Patents
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- Publication number
- JP2003121506A5 JP2003121506A5 JP2001320772A JP2001320772A JP2003121506A5 JP 2003121506 A5 JP2003121506 A5 JP 2003121506A5 JP 2001320772 A JP2001320772 A JP 2001320772A JP 2001320772 A JP2001320772 A JP 2001320772A JP 2003121506 A5 JP2003121506 A5 JP 2003121506A5
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- circuit
- frequency
- signal
- mhz
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 5
- 238000010998 test method Methods 0.000 claims 1
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001320772A JP2003121506A (ja) | 2001-10-18 | 2001-10-18 | 電子機器テスト回路 |
| US10/273,170 US6741094B2 (en) | 2001-10-18 | 2002-10-18 | Electronic apparatus test circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001320772A JP2003121506A (ja) | 2001-10-18 | 2001-10-18 | 電子機器テスト回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003121506A JP2003121506A (ja) | 2003-04-23 |
| JP2003121506A5 true JP2003121506A5 (enExample) | 2005-06-23 |
Family
ID=19138110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001320772A Withdrawn JP2003121506A (ja) | 2001-10-18 | 2001-10-18 | 電子機器テスト回路 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6741094B2 (enExample) |
| JP (1) | JP2003121506A (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7161992B2 (en) * | 2001-10-18 | 2007-01-09 | Intel Corporation | Transition encoded dynamic bus circuit |
| US7005885B1 (en) * | 2003-02-21 | 2006-02-28 | Aeluros, Inc. | Methods and apparatus for injecting an external clock into a circuit |
| US7154300B2 (en) * | 2003-12-24 | 2006-12-26 | Intel Corporation | Encoder and decoder circuits for dynamic bus |
| US7272029B2 (en) * | 2004-12-29 | 2007-09-18 | Intel Corporation | Transition-encoder sense amplifier |
| CN118826956A (zh) * | 2023-11-07 | 2024-10-22 | 中国移动通信有限公司研究院 | 信息传输方法、装置、设备和存储介质 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6202103B1 (en) * | 1998-11-23 | 2001-03-13 | 3A International, Inc. | Bus data analyzer including a modular bus interface |
| JP4106851B2 (ja) | 2000-04-05 | 2008-06-25 | セイコーエプソン株式会社 | テスト回路付きリンク層デバイス及びテスト回路付き物理層デバイス |
| JP4032660B2 (ja) * | 2001-04-06 | 2008-01-16 | セイコーエプソン株式会社 | 半導体チップのテスト方法、半導体チップのテスト実施装置、及び半導体チップ |
-
2001
- 2001-10-18 JP JP2001320772A patent/JP2003121506A/ja not_active Withdrawn
-
2002
- 2002-10-18 US US10/273,170 patent/US6741094B2/en not_active Expired - Fee Related
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