DE60212688D1 - Daten- und taktrückgewinnungsschaltung und eine vorrichtung mehrerer dieser schaltungen enthaltend - Google Patents
Daten- und taktrückgewinnungsschaltung und eine vorrichtung mehrerer dieser schaltungen enthaltendInfo
- Publication number
- DE60212688D1 DE60212688D1 DE60212688T DE60212688T DE60212688D1 DE 60212688 D1 DE60212688 D1 DE 60212688D1 DE 60212688 T DE60212688 T DE 60212688T DE 60212688 T DE60212688 T DE 60212688T DE 60212688 D1 DE60212688 D1 DE 60212688D1
- Authority
- DE
- Germany
- Prior art keywords
- frequency
- data
- phase
- recovery circuit
- pll
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000011084 recovery Methods 0.000 title abstract 2
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Communication Control (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP01203121 | 2001-08-16 | ||
EP01203121 | 2001-08-16 | ||
PCT/IB2002/003229 WO2003017563A2 (en) | 2001-08-16 | 2002-08-02 | Data and clock recovery circuit and an arrangement comprising a plurality of such circuits |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60212688D1 true DE60212688D1 (de) | 2006-08-03 |
DE60212688T2 DE60212688T2 (de) | 2007-06-14 |
Family
ID=8180800
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60212688T Expired - Fee Related DE60212688T2 (de) | 2001-08-16 | 2002-08-02 | Daten- und taktrückgewinnungsschaltung und eine vorrichtung mehrerer dieser schaltungen enthaltend |
Country Status (7)
Country | Link |
---|---|
US (1) | US20030035503A1 (de) |
EP (1) | EP1446911B1 (de) |
JP (1) | JP4124123B2 (de) |
CN (1) | CN100337421C (de) |
AT (1) | ATE331358T1 (de) |
DE (1) | DE60212688T2 (de) |
WO (1) | WO2003017563A2 (de) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008011173A (ja) * | 2006-06-29 | 2008-01-17 | Nippon Telegr & Teleph Corp <Ntt> | Cdr回路 |
KR100885888B1 (ko) | 2007-05-16 | 2009-02-26 | 삼성전자주식회사 | 클록-데이터 복원 회로, 이를 포함하는 멀티-포트 수신기및 클록-데이터 복원 방법 |
CN101420294B (zh) * | 2007-10-24 | 2011-06-15 | 大唐移动通信设备有限公司 | 一种时钟锁相环控制方法及装置 |
FI124040B (fi) * | 2011-04-04 | 2014-02-14 | Tellabs Oy | Menetelmä ja laite taajuustahdistuksen ohjaamiseksi |
US9503250B2 (en) * | 2011-10-28 | 2016-11-22 | Koninklijke Philips N.V. | Data communication with interventional instruments |
US8958513B1 (en) * | 2013-03-15 | 2015-02-17 | Xilinx, Inc. | Clock and data recovery with infinite pull-in range |
KR102222449B1 (ko) * | 2015-02-16 | 2021-03-03 | 삼성전자주식회사 | 탭이 내장된 데이터 수신기 및 이를 포함하는 데이터 전송 시스템 |
EP3276832B1 (de) | 2015-04-15 | 2019-03-13 | Mitsubishi Electric Corporation | Synthesizer |
US9442512B1 (en) | 2015-11-20 | 2016-09-13 | International Business Machines Corporation | Interface clock frequency switching using a computed insertion delay |
US10305495B2 (en) * | 2016-10-06 | 2019-05-28 | Analog Devices, Inc. | Phase control of clock signal based on feedback |
US10439793B2 (en) * | 2017-05-03 | 2019-10-08 | Global Unichip Corporation | Device and method for recovering clock and data |
CN107682007B (zh) * | 2017-09-22 | 2021-01-15 | 哈尔滨工业大学 | 基于双环路的快锁定低抖动的时钟数据恢复电路 |
WO2023102439A1 (en) * | 2021-11-30 | 2023-06-08 | Arizona Board Of Regents On Behalf Of Arizona State University | Fast tracking pll with analog mixer for phase detection |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4897874A (en) * | 1988-03-31 | 1990-01-30 | American Telephone And Telegraph Company At&T Bell Laboratories | Metropolitan area network arrangement for serving virtual data networks |
JP2511591B2 (ja) * | 1990-10-29 | 1996-06-26 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 無線光通信システムの動作方法および光通信システム |
US5369376A (en) * | 1991-11-29 | 1994-11-29 | Standard Microsystems, Inc. | Programmable phase locked loop circuit and method of programming same |
US5490282A (en) * | 1992-12-08 | 1996-02-06 | International Business Machines Corporation | Interface having serializer including oscillator operating at first frequency and deserializer including oscillator operating at second frequency equals half first frequency for minimizing frequency interference |
US5446416A (en) * | 1993-10-20 | 1995-08-29 | Industrial Technology Research Institute | Time acquisition system with dual-loop for independent frequency phase lock |
AUPM972594A0 (en) * | 1994-11-28 | 1994-12-22 | Curtin University Of Technology | Steered frequency phase locked loop |
US5608357A (en) * | 1995-09-12 | 1997-03-04 | Vlsi Technology, Inc. | High speed phase aligner with jitter removal |
US6215835B1 (en) * | 1997-08-22 | 2001-04-10 | Lsi Logic Corporation | Dual-loop clock and data recovery for serial data communication |
US6819728B2 (en) * | 2000-12-28 | 2004-11-16 | International Business Machines Corporation | Self-correcting multiphase clock recovery |
-
2002
- 2002-08-02 AT AT02751575T patent/ATE331358T1/de not_active IP Right Cessation
- 2002-08-02 CN CNB028159373A patent/CN100337421C/zh not_active Expired - Fee Related
- 2002-08-02 WO PCT/IB2002/003229 patent/WO2003017563A2/en active IP Right Grant
- 2002-08-02 DE DE60212688T patent/DE60212688T2/de not_active Expired - Fee Related
- 2002-08-02 EP EP02751575A patent/EP1446911B1/de not_active Expired - Lifetime
- 2002-08-02 JP JP2003521532A patent/JP4124123B2/ja not_active Expired - Fee Related
- 2002-08-12 US US10/217,818 patent/US20030035503A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
DE60212688T2 (de) | 2007-06-14 |
US20030035503A1 (en) | 2003-02-20 |
ATE331358T1 (de) | 2006-07-15 |
CN100337421C (zh) | 2007-09-12 |
EP1446911B1 (de) | 2006-06-21 |
WO2003017563A2 (en) | 2003-02-27 |
CN1599998A (zh) | 2005-03-23 |
JP4124123B2 (ja) | 2008-07-23 |
EP1446911A2 (de) | 2004-08-18 |
JP2005500742A (ja) | 2005-01-06 |
WO2003017563A3 (en) | 2004-06-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE60212688D1 (de) | Daten- und taktrückgewinnungsschaltung und eine vorrichtung mehrerer dieser schaltungen enthaltend | |
DE60005030D1 (de) | Multimode Funkkommunikationsgerät mit gemeinsamen Referenzoszillator | |
EP1791262A3 (de) | Integrierter Halbleiterschaltkreis, der als Phasenregelkreis betrieben werden kann | |
TW200701649A (en) | Phase locked loop circuit and method of locking a phase | |
EP0701329A3 (de) | Phasenregelkreis mit einer leistungsarmen Rückkopplung und Betriebsverfahren | |
WO2001052417A3 (en) | Phase lock loop system and method | |
CA2131104A1 (en) | Signal Processing Device Having PLL Circuits | |
WO2004077507A3 (en) | Control interface scheme for wireless communication chipsets | |
EP0102662A3 (de) | Gleichzeitige Träger- und Taktsynchronisierung ohne phasenverriegelte Schleife | |
CA2374777A1 (en) | Clock/data recovery circuit | |
EP0360691A3 (de) | Gerät zum Empfangen eines Digitalsignals | |
EP0597583B1 (de) | Serieller Bus zwischen integrierten Schaltungen | |
WO2004059844A3 (en) | Pahse locked loop comprising a variable delay and a discrete delay | |
AU2468701A (en) | Systems and methods for holdover circuits in phase locked loops | |
EP1309123A3 (de) | Ultraschnelle Schaltung für Taktrückgewinnung optischer Signale | |
AU3114400A (en) | Low jitter high phase resolution pll-based timing recovery system | |
ATE304241T1 (de) | Frequenzregelkreis, taktwiederherstellungsschaltung und empfänger | |
BR0116823A (pt) | Circuito travado em fase | |
ATE320627T1 (de) | Schaltung zur signalübertragung zwischen endlichen automaten unterschiedlicher taktfrequenz | |
TW316019U (en) | Receive lock apparatus for dual phase locked loop | |
WO2003049292A3 (en) | Single-chip digital phase frequency synthesiser | |
CN108306636A (zh) | 一种非连续微波探询信号的产生装置 | |
JP2003121506A5 (de) | ||
ATE396542T1 (de) | Schaltungen zur funkkommunikation | |
US6763080B1 (en) | Synchronous signal processing system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8328 | Change in the person/name/address of the agent |
Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: NXP B.V., EINDHOVEN, NL |
|
8339 | Ceased/non-payment of the annual fee |