JP2002334933A - タップ・セルを有する集積回路及び集積回路にタップ・セルを配置するための方法 - Google Patents

タップ・セルを有する集積回路及び集積回路にタップ・セルを配置するための方法

Info

Publication number
JP2002334933A
JP2002334933A JP2002027516A JP2002027516A JP2002334933A JP 2002334933 A JP2002334933 A JP 2002334933A JP 2002027516 A JP2002027516 A JP 2002027516A JP 2002027516 A JP2002027516 A JP 2002027516A JP 2002334933 A JP2002334933 A JP 2002334933A
Authority
JP
Japan
Prior art keywords
integrated circuit
tap
cells
cell
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002027516A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002334933A5 (enExample
Inventor
Clive Alva Barney
クリーブ・アルバ・バーニー
Scott Ryan Grange
スコット・ライアン・グランジェ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2002334933A publication Critical patent/JP2002334933A/ja
Publication of JP2002334933A5 publication Critical patent/JP2002334933A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2002027516A 2001-02-07 2002-02-05 タップ・セルを有する集積回路及び集積回路にタップ・セルを配置するための方法 Withdrawn JP2002334933A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/779036 2001-02-07
US09/779,036 US6560753B2 (en) 2001-02-07 2001-02-07 Integrated circuit having tap cells and a method for positioning tap cells in an integrated circuit

Publications (2)

Publication Number Publication Date
JP2002334933A true JP2002334933A (ja) 2002-11-22
JP2002334933A5 JP2002334933A5 (enExample) 2005-04-07

Family

ID=25115115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002027516A Withdrawn JP2002334933A (ja) 2001-02-07 2002-02-05 タップ・セルを有する集積回路及び集積回路にタップ・セルを配置するための方法

Country Status (2)

Country Link
US (1) US6560753B2 (enExample)
JP (1) JP2002334933A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9343461B2 (en) 2012-04-24 2016-05-17 Socionext Inc. Semiconductor device including a local wiring connecting diffusion regions

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6848089B2 (en) * 2002-07-31 2005-01-25 International Business Machines Corporation Method and apparatus for detecting devices that can latchup
JP4426166B2 (ja) * 2002-11-01 2010-03-03 ユー・エム・シー・ジャパン株式会社 半導体装置の設計方法、半導体装置設計用プログラム、及び半導体装置
US6925627B1 (en) * 2002-12-20 2005-08-02 Conexant Systems, Inc. Method and apparatus for power routing in an integrated circuit
US7617465B1 (en) * 2004-09-16 2009-11-10 Cadence Design Systems, Inc. Method and mechanism for performing latch-up check on an IC design
US7937682B2 (en) * 2008-01-31 2011-05-03 Synopsys, Inc. Method and apparatus for automatic orientation optimization
US20090300291A1 (en) * 2008-06-03 2009-12-03 Gerald Keith Bartley Implementing Cache Coherency and Reduced Latency Using Multiple Controllers for Memory System
US8276109B2 (en) * 2008-12-23 2012-09-25 Broadcom Corporation Mixed-height high speed reduced area cell library
US10192859B2 (en) 2011-05-11 2019-01-29 Texas Instruments Incorporated Integrated circuits and processes for protection of standard cell performance from context effects
US9082886B2 (en) 2011-05-12 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Adding decoupling function for tap cells
US8984467B2 (en) 2011-08-17 2015-03-17 Synopsys, Inc. Method and apparatus for automatic relative placement generation for clock trees
WO2013132841A1 (ja) 2012-03-08 2013-09-12 パナソニック株式会社 半導体集積回路装置
US9361417B2 (en) 2014-02-07 2016-06-07 Synopsys, Inc. Placement of single-bit and multi-bit flip-flops
CN104485332B (zh) * 2014-12-10 2017-05-03 中国电子科技集团公司第四十七研究所 阱连接单元的布置方法及包括该阱连接单元的半导体芯片
US10114919B2 (en) 2016-02-12 2018-10-30 Globalfoundries Inc. Placing and routing method for implementing back bias in FDSOI
US10872190B2 (en) * 2018-07-16 2020-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method and system for latch-up prevention
US11527527B2 (en) * 2020-05-21 2022-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Tap cell, integrated circuit structure and forming method thereof
US12027525B2 (en) * 2020-07-28 2024-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit device, method, and system
US11416666B1 (en) * 2021-03-04 2022-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit and method for forming the same
US12046603B2 (en) 2021-11-23 2024-07-23 Globalfoundries U.S. Inc. Semiconductor structure including sectioned well region
KR20230161704A (ko) 2022-05-19 2023-11-28 삼성전자주식회사 반도체 장치
US20240038760A1 (en) * 2022-08-01 2024-02-01 Qualcomm Incorporated Integrated circuit cell with dual row, back-to-back, transistor body ties
US12328880B2 (en) 2023-09-19 2025-06-10 Globalfoundries U.S. Inc. Hierarchical memory architecture including on-chip multi-bank non-volatile memory with low leakage and low latency

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5987086A (en) * 1996-11-01 1999-11-16 Motorola Inc. Automatic layout standard cell routing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9343461B2 (en) 2012-04-24 2016-05-17 Socionext Inc. Semiconductor device including a local wiring connecting diffusion regions

Also Published As

Publication number Publication date
US6560753B2 (en) 2003-05-06
US20020105049A1 (en) 2002-08-08

Similar Documents

Publication Publication Date Title
JP2002334933A (ja) タップ・セルを有する集積回路及び集積回路にタップ・セルを配置するための方法
JP3231741B2 (ja) スタンダードセル、スタンダードセル列、スタンダードセルの配置配線装置および配置配線方法
US6453447B1 (en) Method for fabricating integrated circuits
US7287320B2 (en) Method for programming a routing layout design through one via layer
JP5240614B2 (ja) 集積回路レイアウトを自動的に形成する方法
US7269803B2 (en) System and method for mapping logical components to physical locations in an integrated circuit design environment
JP3535804B2 (ja) フリップチップ型半導体装置の設計方法
CN105488244B (zh) 用于设计半导体装置的方法和系统
JPH08316331A (ja) 半導体集積回路及びその設計方法
US6804809B1 (en) System and method for defining a semiconductor device layout
JP2001306641A (ja) 半導体集積回路の自動配置配線方法
US6477696B2 (en) Routing definition to optimize layout design of standard cells
EP0021661B1 (en) Semiconductor master-slice device
KR930006726B1 (ko) 집적회로 및 전원간선 레이아웃방법
JP3270427B2 (ja) 半導体装置の設計方法
JP4237611B2 (ja) 半導体集積回路のレイアウト設計方法及びレイアウト設計装置
KR20020042507A (ko) 반도체장치, 그 제조방법 및 기억매체
TWI897516B (zh) 積體電路佈局及其產生的方法
JP3017181B1 (ja) 半導体集積回路の配線方法
JP4451629B2 (ja) 半導体集積回路のレイアウト装置および方法ならびこれらを使用して製造された半導体装置
JP3064925B2 (ja) レイアウト方法
JP2006202923A (ja) 半導体装置の設計方法、半導体装置の設計プログラム
JP3370259B2 (ja) マスクレイアウト設計方法
JP3147080B2 (ja) 半導体集積回路の自動配置配線装置とその方法及びその方法を記録した記録媒体
JPH07225785A (ja) 半導体装置の低消費電力レイアウト方法及びレイアウト装置並びにその半導体装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040524

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040524

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050428

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050517

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20050721

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20050726

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20051117

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20070309