JP2002334933A5 - - Google Patents

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Publication number
JP2002334933A5
JP2002334933A5 JP2002027516A JP2002027516A JP2002334933A5 JP 2002334933 A5 JP2002334933 A5 JP 2002334933A5 JP 2002027516 A JP2002027516 A JP 2002027516A JP 2002027516 A JP2002027516 A JP 2002027516A JP 2002334933 A5 JP2002334933 A5 JP 2002334933A5
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JP
Japan
Prior art keywords
tap
cells
integrated circuit
logic
logic cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002027516A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002334933A (ja
Filing date
Publication date
Priority claimed from US09/779,036 external-priority patent/US6560753B2/en
Application filed filed Critical
Publication of JP2002334933A publication Critical patent/JP2002334933A/ja
Publication of JP2002334933A5 publication Critical patent/JP2002334933A5/ja
Withdrawn legal-status Critical Current

Links

JP2002027516A 2001-02-07 2002-02-05 タップ・セルを有する集積回路及び集積回路にタップ・セルを配置するための方法 Withdrawn JP2002334933A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/779036 2001-02-07
US09/779,036 US6560753B2 (en) 2001-02-07 2001-02-07 Integrated circuit having tap cells and a method for positioning tap cells in an integrated circuit

Publications (2)

Publication Number Publication Date
JP2002334933A JP2002334933A (ja) 2002-11-22
JP2002334933A5 true JP2002334933A5 (enExample) 2005-04-07

Family

ID=25115115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002027516A Withdrawn JP2002334933A (ja) 2001-02-07 2002-02-05 タップ・セルを有する集積回路及び集積回路にタップ・セルを配置するための方法

Country Status (2)

Country Link
US (1) US6560753B2 (enExample)
JP (1) JP2002334933A (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6848089B2 (en) * 2002-07-31 2005-01-25 International Business Machines Corporation Method and apparatus for detecting devices that can latchup
JP4426166B2 (ja) * 2002-11-01 2010-03-03 ユー・エム・シー・ジャパン株式会社 半導体装置の設計方法、半導体装置設計用プログラム、及び半導体装置
US6925627B1 (en) * 2002-12-20 2005-08-02 Conexant Systems, Inc. Method and apparatus for power routing in an integrated circuit
US7617465B1 (en) * 2004-09-16 2009-11-10 Cadence Design Systems, Inc. Method and mechanism for performing latch-up check on an IC design
US7937682B2 (en) * 2008-01-31 2011-05-03 Synopsys, Inc. Method and apparatus for automatic orientation optimization
US20090300291A1 (en) * 2008-06-03 2009-12-03 Gerald Keith Bartley Implementing Cache Coherency and Reduced Latency Using Multiple Controllers for Memory System
US8276109B2 (en) * 2008-12-23 2012-09-25 Broadcom Corporation Mixed-height high speed reduced area cell library
US10192859B2 (en) 2011-05-11 2019-01-29 Texas Instruments Incorporated Integrated circuits and processes for protection of standard cell performance from context effects
US9082886B2 (en) 2011-05-12 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Adding decoupling function for tap cells
US8984467B2 (en) 2011-08-17 2015-03-17 Synopsys, Inc. Method and apparatus for automatic relative placement generation for clock trees
WO2013132841A1 (ja) 2012-03-08 2013-09-12 パナソニック株式会社 半導体集積回路装置
JP6056852B2 (ja) 2012-04-24 2017-01-11 株式会社ソシオネクスト 半導体装置
US9361417B2 (en) 2014-02-07 2016-06-07 Synopsys, Inc. Placement of single-bit and multi-bit flip-flops
CN104485332B (zh) * 2014-12-10 2017-05-03 中国电子科技集团公司第四十七研究所 阱连接单元的布置方法及包括该阱连接单元的半导体芯片
US10114919B2 (en) 2016-02-12 2018-10-30 Globalfoundries Inc. Placing and routing method for implementing back bias in FDSOI
US10872190B2 (en) * 2018-07-16 2020-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method and system for latch-up prevention
US11527527B2 (en) * 2020-05-21 2022-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Tap cell, integrated circuit structure and forming method thereof
US12027525B2 (en) * 2020-07-28 2024-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit device, method, and system
US11416666B1 (en) * 2021-03-04 2022-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit and method for forming the same
US12046603B2 (en) 2021-11-23 2024-07-23 Globalfoundries U.S. Inc. Semiconductor structure including sectioned well region
KR20230161704A (ko) 2022-05-19 2023-11-28 삼성전자주식회사 반도체 장치
US20240038760A1 (en) * 2022-08-01 2024-02-01 Qualcomm Incorporated Integrated circuit cell with dual row, back-to-back, transistor body ties
US12328880B2 (en) 2023-09-19 2025-06-10 Globalfoundries U.S. Inc. Hierarchical memory architecture including on-chip multi-bank non-volatile memory with low leakage and low latency

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5987086A (en) * 1996-11-01 1999-11-16 Motorola Inc. Automatic layout standard cell routing

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