WO2005024644A3 - Integrated data processing circuit with a plurality of programmable processors - Google Patents

Integrated data processing circuit with a plurality of programmable processors Download PDF

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Publication number
WO2005024644A3
WO2005024644A3 PCT/IB2004/051510 IB2004051510W WO2005024644A3 WO 2005024644 A3 WO2005024644 A3 WO 2005024644A3 IB 2004051510 W IB2004051510 W IB 2004051510W WO 2005024644 A3 WO2005024644 A3 WO 2005024644A3
Authority
WO
WIPO (PCT)
Prior art keywords
processors
data processing
processing circuit
integrated data
router
Prior art date
Application number
PCT/IB2004/051510
Other languages
French (fr)
Other versions
WO2005024644A2 (en
Inventor
Menno M Lindwer
Dalen Edwin J Van
Original Assignee
Koninkl Philips Electronics Nv
Menno M Lindwer
Dalen Edwin J Van
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Menno M Lindwer, Dalen Edwin J Van filed Critical Koninkl Philips Electronics Nv
Priority to US10/570,966 priority Critical patent/US20070165547A1/en
Priority to DE602004009324T priority patent/DE602004009324T2/en
Priority to EP04769834A priority patent/EP1665065B1/en
Priority to KR1020067004886A priority patent/KR101200598B1/en
Priority to JP2006525933A priority patent/JP4818920B2/en
Publication of WO2005024644A2 publication Critical patent/WO2005024644A2/en
Publication of WO2005024644A3 publication Critical patent/WO2005024644A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)

Abstract

An integrated data processing circuit contains matrix of programmable processors. Each processor (12) has private operand transfer connections to its neighboring processors (12) in the matrix, typically for passing operands of transfer commands. An additional tree communication structure contain router circuits (16, 18, 19) hierarchically coupled to each other and to the processors. The processors (12) form leave nodes of the tree structure, the router circuits (16, 18, 19) being arranged to route a message with an address from a root router (19) circuit to an addressed processor (12), selectively via a path through the tree structure, the router circuits (16, 18, 19) each selecting a part of the path under control of the address.
PCT/IB2004/051510 2003-09-09 2004-08-20 Integrated data processing circuit with a plurality of programmable processors WO2005024644A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US10/570,966 US20070165547A1 (en) 2003-09-09 2004-08-20 Integrated data processing circuit with a plurality of programmable processors
DE602004009324T DE602004009324T2 (en) 2003-09-09 2004-08-20 INTEGRATED DATA PROCESSING CIRCUIT WITH MULTIPLE PROGRAMMABLE PROCESSORS
EP04769834A EP1665065B1 (en) 2003-09-09 2004-08-20 Integrated data processing circuit with a plurality of programmable processors
KR1020067004886A KR101200598B1 (en) 2003-09-09 2004-08-20 Integrated data processing circuit with a plurality of programmable processors
JP2006525933A JP4818920B2 (en) 2003-09-09 2004-08-20 Integrated data processing circuit having a plurality of programmable processors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03103322 2003-09-09
EP03103322.8 2003-09-09

Publications (2)

Publication Number Publication Date
WO2005024644A2 WO2005024644A2 (en) 2005-03-17
WO2005024644A3 true WO2005024644A3 (en) 2005-05-06

Family

ID=34259263

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2004/051510 WO2005024644A2 (en) 2003-09-09 2004-08-20 Integrated data processing circuit with a plurality of programmable processors

Country Status (8)

Country Link
US (1) US20070165547A1 (en)
EP (1) EP1665065B1 (en)
JP (1) JP4818920B2 (en)
KR (1) KR101200598B1 (en)
CN (1) CN1849598A (en)
AT (1) ATE374973T1 (en)
DE (1) DE602004009324T2 (en)
WO (1) WO2005024644A2 (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070124565A1 (en) * 2003-06-18 2007-05-31 Ambric, Inc. Reconfigurable processing array having hierarchical communication network
JP4755033B2 (en) * 2006-07-05 2011-08-24 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit
US20080052490A1 (en) * 2006-08-28 2008-02-28 Tableau, Llc Computational resource array
US20080126472A1 (en) * 2006-08-28 2008-05-29 Tableau, Llc Computer communication
US20080052525A1 (en) * 2006-08-28 2008-02-28 Tableau, Llc Password recovery
US20080052429A1 (en) * 2006-08-28 2008-02-28 Tableau, Llc Off-board computational resources
US7962717B2 (en) * 2007-03-14 2011-06-14 Xmos Limited Message routing scheme
US7994818B2 (en) * 2007-06-20 2011-08-09 Agate Logic (Beijing), Inc. Programmable interconnect network for logic array
JP4676463B2 (en) * 2007-07-13 2011-04-27 株式会社日立製作所 Parallel computer system
US7826455B2 (en) * 2007-11-02 2010-11-02 Cisco Technology, Inc. Providing single point-of-presence across multiple processors
CN101320364A (en) * 2008-06-27 2008-12-10 北京大学深圳研究生院 Array processor structure
US8307116B2 (en) * 2009-06-19 2012-11-06 Board Of Regents Of The University Of Texas System Scalable bus-based on-chip interconnection networks
US10698859B2 (en) * 2009-09-18 2020-06-30 The Board Of Regents Of The University Of Texas System Data multicasting with router replication and target instruction identification in a distributed multi-core processing architecture
KR101594853B1 (en) * 2009-11-27 2016-02-17 삼성전자주식회사 Computer chip and information routing method in the computer chip
CN102063408B (en) * 2010-12-13 2012-05-30 北京时代民芯科技有限公司 Data bus in multi-kernel processor chip
JP5171971B2 (en) * 2011-01-17 2013-03-27 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit
WO2013106210A1 (en) 2012-01-10 2013-07-18 Intel Corporation Electronic apparatus having parallel memory banks
JP6122135B2 (en) * 2012-11-21 2017-04-26 コーヒレント・ロジックス・インコーポレーテッド Processing system with distributed processor
US10452399B2 (en) 2015-09-19 2019-10-22 Microsoft Technology Licensing, Llc Broadcast channel architectures for block-based processors
US11062203B2 (en) * 2016-12-30 2021-07-13 Intel Corporation Neuromorphic computer with reconfigurable memory mapping for various neural network topologies
US10713558B2 (en) * 2016-12-30 2020-07-14 Intel Corporation Neural network with reconfigurable sparse connectivity and online learning
US10963379B2 (en) 2018-01-30 2021-03-30 Microsoft Technology Licensing, Llc Coupling wide memory interface to wide write back paths
CN111866069A (en) * 2020-06-04 2020-10-30 西安万像电子科技有限公司 Data processing method and device

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4251861A (en) * 1978-10-27 1981-02-17 Mago Gyula A Cellular network of processors
US4860201A (en) * 1986-09-02 1989-08-22 The Trustees Of Columbia University In The City Of New York Binary tree parallel processor
DE68920388T2 (en) * 1988-09-19 1995-05-11 Fujitsu Ltd Parallel computer system using a SIMD process.
US5161156A (en) * 1990-02-02 1992-11-03 International Business Machines Corporation Multiprocessing packet switching connection system having provision for error correction and recovery
DE4129614C2 (en) * 1990-09-07 2002-03-21 Hitachi Ltd System and method for data processing
US5561768A (en) * 1992-03-17 1996-10-01 Thinking Machines Corporation System and method for partitioning a massively parallel computer system
US6000024A (en) * 1997-10-15 1999-12-07 Fifth Generation Computer Corporation Parallel computing system
US6622233B1 (en) * 1999-03-31 2003-09-16 Star Bridge Systems, Inc. Hypercomputer
US6745317B1 (en) * 1999-07-30 2004-06-01 Broadcom Corporation Three level direct communication connections between neighboring multiple context processing elements
JP2001167066A (en) * 1999-12-08 2001-06-22 Nec Corp Inter-processor communication method and multiprocessor system
US20030123492A1 (en) 2001-05-14 2003-07-03 Locke Samuel Ray Efficient multiplexing system and method

Non-Patent Citations (9)

* Cited by examiner, † Cited by third party
Title
BRINKMANN A ET AL: "On-chip interconnects for next generation system-on-chips", ASIC/SOC CONFERENCE, 2002. 15TH ANNUAL IEEE INTERNATIONAL SEP 25-28, 2002, PISCATAWAY, NJ, USA,IEEE, 25 September 2002 (2002-09-25), pages 211 - 215, XP010622029, ISBN: 0-7803-7494-0 *
GUERRIER P ET AL: "A Generic Architecture for On-Chip Packet-Switched Interconnections", NN, 27 March 2000 (2000-03-27), pages 250 - 256, XP010377472 *
HEATON R A ET AL: "BLITZEN: A VLSI ARRAY PROCESSING CHIP", PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE. SAN DIEGO, 15 - 18 MAY, 1989, NEW YORK, IEEE, US, vol. CONF. 11, 15 May 1989 (1989-05-15), pages 1211 - 1215, XP000075629 *
KOCHTE M: "Packet-Switching Networks on Systems-on-a-Chip", INET, 12 June 2003 (2003-06-12), XP002320370, Retrieved from the Internet <URL:http://www.ra.informatik.uni-stuttgart.de/~tangyi/noc/noc-packet-switched-networks.pdf> [retrieved on 20050308] *
PANDE P P, GRECU C, IVANOV A, SALEH R: "Design of a Switch for Network on Chip Applications", CIRCUITS AND SYSTEMS, 2003. ISCAS '03., May 2003 (2003-05-01), XP002320369 *
PANDE P P, GRECU C, IVANOV A, SALEH R: "High-Throughput Switch-Based Interconnect for Future SoCs", PROCEEDINGS OF THE 3RD IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, July 2003 (2003-07-01), XP002320368 *
PECHANEK G G ET AL: "MFAST: a single chip highly parallel image processing architecture", PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON IMAGE PROCESSING. (ICIP). WASHINGTON, OCT. 23 - 26, 1995, LOS ALAMITOS, IEEE COMP. SOC. PRESS, US, vol. VOL. 3, 23 October 1995 (1995-10-23), pages 69 - 72, XP010196926, ISBN: 0-7803-3122-2 *
SCHMIDT U ET AL: "DATAWAVE: A SINGLE-CHIP MULTIPROCESSOR FOR VIDEO APPLICATIONS", IEEE MICRO, IEEE INC. NEW YORK, US, vol. 11, no. 3, 1 June 1991 (1991-06-01), pages 22 - 25,88, XP000237234, ISSN: 0272-1732 *
ZEFERINO C A ET AL: "A study on communication issues for systems-on-chip", INTEGRATED CIRCUITS AND SYSTEMS DESIGN, 2002. PROCEEDINGS. 15TH SYMPOSIUM ON 9-14, SEPT. 2002, PISCATAWAY, NJ, USA,IEEE, 9 September 2002 (2002-09-09), pages 121 - 126, XP010621778, ISBN: 0-7695-1807-9 *

Also Published As

Publication number Publication date
EP1665065A2 (en) 2006-06-07
EP1665065B1 (en) 2007-10-03
JP4818920B2 (en) 2011-11-16
CN1849598A (en) 2006-10-18
KR20060131730A (en) 2006-12-20
DE602004009324T2 (en) 2008-07-10
KR101200598B1 (en) 2012-11-12
JP2007505383A (en) 2007-03-08
US20070165547A1 (en) 2007-07-19
DE602004009324D1 (en) 2007-11-15
WO2005024644A2 (en) 2005-03-17
ATE374973T1 (en) 2007-10-15

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