JP2002222875A - Non-volatile semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve data retention characteristics and the resistance to repeated writing and erasing of a non-volatile semiconductor memory device, a kind of MONOS flash memory. SOLUTION: The non-volatile semiconductor memory device 200 comprises a gate insulation film 7 having a discrete trap which is formed between a gate electrode G of a MIS transistor and a semiconductor substrate (Si substrate 1), and stores and erases data by charging and discharging of the trap. In the gate insulation film 7, a discrete extremely thin film 12 including high melting point metal is formed as a trap formation layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a data storage element used in a MIS type LSI, and relates to a nonvolatile semiconductor storage element capable of holding data regardless of ON / OFF of a power supply of the element.

[0002]

2. Description of the Related Art In a MIS type LSI, a large number of non-volatile semiconductor storage elements capable of retaining data irrespective of ON / OFF of the power supply of the element are used.
Various types of non-volatile semiconductor storage elements are known. A floating gate electrode made of poly-Si or the like is provided in the middle of a gate insulating film having a MIS structure, and a Si substrate is used as a floating gate electrode. Charges are injected by hot carriers, tunnel currents, and the like through an insulating film (tunnel oxide film) between the substrate and the floating gate electrode, and the floating gate electrode is charged to change the threshold voltage of the MIS transistor and store the data. A so-called floating gate type flash memory that holds the data has been put to practical use.

However, a floating gate type flash memory has a floating gate electrode and a Si
If there is even a partial leak in the tunnel oxide film between the substrate and the substrate, all of the charges accumulated in the floating gate electrode are lost, and it is extremely difficult to reduce the thickness of the tunnel oxide film. As a result, the data write voltage becomes 1
It cannot be lowered below about 7 V, making it difficult to miniaturize the corresponding structure of the drain and the like.
It is considered that practical application is difficult as a fine nonvolatile memory element of the μm generation or later.

On the other hand, metal (gate electrode), Si oxide film, Si nitride film, Si oxide film (tunnel oxide film),
A MONOS structure composed of an i-substrate is formed, and the threshold of the transistor is changed by accumulating charges in a discrete trap existing in the Si nitride film and near the interface between the Si oxide film and the Si nitride film on the gate electrode side. A so-called MONOS type flash memory has been developed which holds data in a flash memory.

A MONOS type flash memory is shown in FIG.
It is manufactured as shown in FIG. First, a well isolation or element isolation film 2 is formed on a Si substrate 1 by a normal LOCOS method, a shallow trench method, or the like, and a buried layer 3 for adjusting a threshold voltage is formed by an ion implantation method (FIG. 1A). ).

Next, a Si oxide film (tunnel oxide film) 4 having a thickness of about 3 nm is formed on the substrate by thermal oxidation at 800 ° C. for about 15 minutes (FIG. 1B), and LP-CV is formed thereon.
An Si nitride film 5 having a thickness of about 8 nm is formed by D or plasma CVD. Then, the Si nitride film 5 is re-oxidized to form a Si oxide film 6 having a thickness of about 3 to 5 nm.
Is formed to obtain a gate insulating film 7 having an ONO structure composed of a Si oxide film 6, a Si nitride film 5, and a Si oxide film (tunnel oxide film) 4 (FIG. 3C).

Next, poly-Si and WSi containing phosphorus or the like at a high concentration, which become the gate electrode G, are sequentially deposited on the Si oxide film 6 to form a gate electrode layer 8 (FIG. 1D). The structure is patterned using a lithography technique and an RIE technique to form a gate electrode G. Using this gate electrode G as a mask, phosphorus or arsenic, for example, 5 ×
Low-concentration regions LDD _a and LDD _b are formed by ion implantation at a concentration of about 10 ¹³ / cm ² (FIG. 3E).

Next, the side wall 9 of the gate electrode G is formed of a Si oxide film using a normal CVD and an etch back method, and using this as a mask, for example, phosphorus or the like is 5 × 10 ¹⁵ / cm
Impurities of the source S and the drain D are introduced by ion implantation at a concentration of about ² . Then, in order to activate the impurities, a heat treatment at 900 ° C. for about 30 minutes is performed by heating in an electric furnace, or a rapid heat treatment (RTP) apparatus is used.
Heat treatment is performed at 050 ° C. for about 10 seconds (FIG. 6F).

Next, an interlayer insulating film 10 such as an Si oxide film is formed (FIG. 1G), a connection hole is opened, and a plug 11 made of W or poly-Si is formed. MONOS type flash memory 10
0 is obtained (FIG. 7 (h)).

[0010]

In the MONOS type flash memory 100 manufactured as described above, the gate insulating film 7 is composed of the Si oxide film 6, the Si nitride film 5, and the Si oxide film (tunnel oxide film) 4. Although the ONO structure is provided, in this ONO structure, S is formed near the interface between the Si oxide film 6 and the Si nitride film 5 on the gate electrode side formed by re-oxidation.
It is considered that an iON transition layer is formed, and a deep-order trap that accumulates charges in the SiON transition layer and the Si nitride film 5 is formed.

This trap has a long life as stored charge, which is advantageous for data retention. Further, since the traps are formed discretely, even if there is a partial leak in the tunnel oxide film 4, most of the accumulated charges are not lost. Therefore, the thickness of the tunnel oxide film 4 is set to 3
The thickness can be reduced to about nm, which is considerably smaller than that of the floating gate type flash memory. As a result, there is a possibility that the write voltage can be reduced to about 10 V or less.

However, the trap density of the MONOS type flash memory 100 is 10 ¹² to 10 ¹³ / cm ^2, which is about 5 digits lower than that of the floating gate type flash memory. In addition, the trap density of the MONOS type flash memory 100 can be reproducibly measured.
And it is not easy to form it with good controllability. For this reason,
In the miniaturized MONOS type flash memory 100, the data retention time (Data Retention) and the write / erase repetition endurance are not always sufficient.

On the other hand, an object of the present invention is to improve the data retention characteristics and the write / erase repetition resistance in a nonvolatile semiconductor memory device similar to a MONOS type flash memory.

[0014]

Means for Solving the Problems The present inventor has developed a conventional MO.
In the NOS type flash memory 100, as a trap in the gate insulating film 7, SiON discretely formed near the interface between the Si nitride film 5 and the Si oxide film 6 formed by thermal oxidation of the Si nitride film 5 is used. Although a transition layer is used, an atomic layer chemical vapor deposition (Atom)
ic Layer Chemical Vapor Deposition (ALCVD), etc., forms a discrete ultra-thin layer containing a high melting point metal, which becomes a trap. , And can be formed at a desired depth to improve data retention characteristics and write / erase repetition resistance.
According to this trap, the difference in threshold voltage as a memory effect can be made large, and it has been found that this trap is also advantageous for multi-value.

That is, in the present invention, a gate insulating film having discrete traps is provided between a gate electrode of a MIS transistor and a semiconductor substrate, and data is stored and erased by charging and discharging the traps. Provided is a nonvolatile semiconductor memory element, wherein a discrete ultrathin film containing a high melting point metal is provided as a trap formation layer in a gate insulating film.

As a method of manufacturing this nonvolatile semiconductor memory element, a gate insulating film having discrete traps is provided between the gate electrode of the MIS transistor and the semiconductor substrate. A method of manufacturing a nonvolatile semiconductor memory element for storing and erasing data, comprising forming an Si oxide film on a semiconductor substrate, and forming a trap on the Si oxide film by an atomic layer chemical vapor deposition method. Forming a discrete ultrathin film containing a high melting point metal, and then forming a gate insulating film by laminating an insulating film.

In the present invention, the term "discrete" refers to a state in which an electrically discontinuous film is formed instead of an electrically continuous film such as a floating gate electrode of a floating gate type flash memory. Further, that the discrete film containing the high melting point metal is extremely thin means that the average film thickness is 0.1 nm or less.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings. In each of the drawings, the same reference numerals represent the same or equivalent components.

Embodiment 1 FIG. 1 is a manufacturing process diagram of an embodiment of a nonvolatile semiconductor memory device of the present invention.

First, a well isolation or element isolation film 2 is formed on a semiconductor substrate such as an Si substrate 1 by a usual LOCOS method, a shallow trench method, or the like, and a buried layer 3 for adjusting a threshold voltage is formed by an ion implantation method. Then, an Si oxide film (tunnel oxide film) 4 is formed on the substrate by thermal oxidation at 800 to 850 ° C. for about 15 to 20 minutes (FIG. 12B). Here, as the Si substrate 1, a semiconductor substrate such as a silicon single crystal wafer, or an epitaxial silicon layer, a polysilicon layer, an amorphous silicon layer, or the like formed on an arbitrary substrate can be used. Also,
In the present invention, a substrate having a semiconductor layer formed on an arbitrary substrate can be used as the semiconductor substrate in addition to the above-described Si substrate.

The optimum thickness of the Si oxide film (tunnel oxide film) 4 varies depending on the ion implantation mechanism. For example, when the ion implantation is performed by a Fowler Mordheim tunnel current, the thickness is about 2.5 to 3.5 nm. When ion implantation is performed using channel hot carriers, the thickness is about 7 nm.

Next, a discrete ultrathin film 12 containing a high melting point metal such as W, WN, TiN, MoN is formed on the tunnel oxide film 4 by using an atomic layer chemical vapor deposition method. More specifically, in the case of the atomic layer chemical vapor deposition method, first, a precursor gas is selected according to the kind of the discrete ultrathin film 12 to be formed. For example, when forming a W film, W
WF ₆ / NH ₃ , Ti when forming a F ₆ , WN film
TiCl ₄ / NH ₃ is used when forming an N film, and MoCl ₅ / NH ₃ is used when forming a MoN film. Then, the precursor gas is heated to a temperature of 300 to 40 in the chamber.
At 0 ° C., it is adsorbed on the tunnel oxide film 4, then the supply of the precursor gas is stopped, ammonia or hydrogen (or hydrogen radical) is introduced into the chamber, and thermal decomposition is performed by nitridation or reduction, respectively. WN, TiN, M
A thin film such as oN is deposited. By this one-cycle deposition, an atomic layer or a molecular layer covering about 1/3 to 1/10 of the surface adsorption sites on the tunnel oxide film 4 is formed, depending on the size of the precursor molecule. Therefore,
The discrete ultrathin film 12 can be formed with good controllability, and the trap density can be formed to be about 1 to 5 × 10 ¹⁴ / cm ² . Here, the trap density is a value measured by a difference between _VFB before and after electron injection (IEEE).
Elect. Dev., ED30 (2), 122 (1983)).

Further, in order to increase the degree of discreteness of the discrete ultrathin film 12 by this method, it is only necessary to use a precursor of a relatively large molecule and reduce the surface occupancy of the ultrathin film to be formed.

According to the atomic layer chemical vapor deposition method,
By repeating the deposition process of an extremely thin film from several cycles to about 10 cycles, a continuous film of one atomic layer or one molecular layer can be formed. However, in the present invention, since traps are formed discretely, one atomic layer or one atomic layer is formed. No continuous layer or monolayer is formed.

After the formation of the discrete ultrathin film 12 containing a high melting point metal, the Si film having a thickness of about 5 to 10 nm is formed by a normal CVD method.
An oxide film 13 is formed. Thus, the gate insulating film 7 having the discrete ultrathin film 12 containing the high melting point metal as a trap.
Can be formed.

When the Si oxide film 13 is formed on the discrete ultra-thin film 12 containing a high melting point metal as in this embodiment,
The Si oxide film 13 has a wide forbidden band width, hardly leaks electric charge, and has a simple structure of the gate insulating film 7, so that the reliability of the device can be improved. The layer formed on the target ultrathin film 12 is not particularly limited as long as it has good adhesion to the gate electrode G.
For example, as in the case of the MONOS type flash memory shown in FIG. 4, a Si nitride film is deposited by a CVD method and then formed by a method of reoxidizing.

After the formation of the Si oxide film 13, similarly to the MONOS type flash memory shown in FIG. 4, poly-Si and WSi containing phosphorus or the like at a high concentration are sequentially deposited to form a gate electrode layer 8 (see FIG. 4). As shown in FIG. 3D, it is patterned by using lithography and RIE techniques to form a gate electrode G. Using this gate electrode G as a mask, phosphorus or arsenic is doped at a concentration of, for example, about 5 × 10 ¹³ / cm ^2. The low-concentration regions LDD _a , L
Forming a DD _b (FIG. (E)).

Next, the side wall 9 of the gate electrode G is formed of a Si oxide film using a normal CVD and etch-back method, and using this as a mask, for example, phosphorus or the like is 5 × 10 ¹⁵ / cm
Impurities of the source S and the drain D are introduced by ion implantation at a concentration of about ² . Then, in order to activate these impurities, heat treatment is performed at 900 ° C. for about 30 minutes by heating in an electric furnace, or 1 hour by a rapid heat treatment (RTP) apparatus.
Heat treatment is performed at 050 ° C. for about 10 seconds (FIG. 6F).

Next, an interlayer insulating film 10 such as a Si oxide film is formed (FIG. 9G), and a connection hole is opened to form a plug 11 made of W or poly-Si. Thus, a nonvolatile semiconductor memory device 200 similar to the MONOS type flash memory 100 of FIG. 4 is obtained (FIG. 4H).

Embodiment 2 FIG. 2 is a manufacturing process diagram of another embodiment of the nonvolatile semiconductor memory device of the present invention. An ultra-thin film containing a refractory metal is placed in a dummy groove formed by using a dummy gate method. This is an example of forming.

That is, similarly to the first embodiment, a well isolation or element isolation film 2 is formed on a Si substrate 1 by a normal LOCOS method, a shallow trench method, or the like, and a buried layer 3 for adjusting a threshold voltage is formed. It is formed by an ion implantation method (FIG. 3A).

Next, the substrate is placed at 800-850 ° C., 15 ° C.
An Si oxide film (tunnel oxide film) 4 is formed by thermal oxidation for about 20 minutes. Here, the optimum thickness of the Si oxide film (tunnel oxide film) 4 differs depending on the ion implantation mechanism. For example, when the ion implantation is performed by a Fowler Mordheim tunnel current, the thickness is about 2.5 to 3.5 nm. In case of ion implantation by carrier, about 7
nm.

On the Si oxide film (tunnel oxide film) 4, a poly Si film 14 having a thickness of about 500 to 600 nm to be a dummy gate DG is formed by LP-CVD or the like (FIG. 2B).

By patterning the laminated structure using lithography and RIE techniques, a dummy gate DG having a width of, for example, 0.13 μm is formed. Using the dummy gate DG as a mask, for example, 5 × phosphor or arsenic is deposited. Low-concentration regions LDD _a and LDD _b are formed by ion implantation at a concentration of about 10 ¹³ / cm ² (FIG. 3C).

Next, a normal CVD and etch-back method are used.
Then, the side wall 9 is formed with a Si oxide film on the dummy gate DG,
Using this as a mask, for example, phosphorus^Fifteen/
cm ²The source S can be obtained by ion-implanting
And impurities of the drain D are introduced to activate them.
850 to 950 ° C by electric furnace heating, about 20 to 30 minutes
Heat treatment or rapid heat treatment (RTP) equipment
Heat treatment at 1000-1100 ° C for about 5-10 seconds
(FIG. 3D).

Next, the dummy gate DG and the interlayer insulating film 10 surrounding the dummy gate DG are deposited by depositing a Si oxide film or the like.
To form Then, the interlayer insulating film 10 is flattened by a flattening technique such as CMP to expose the dummy gate DG,
The exposed dummy gate DG is removed by an etching method to form a gate groove 15 (FIG. 3E).

The tunnel oxide film 4 which has been the base of the dummy gate DG may be left after the etching of the dummy gate DG, or may be removed by etching following the removal of the dummy gate DG. When the tunnel oxide film 4 has been removed, the tunnel oxide film 4 is formed again on the bottom surface of the gate groove 15.

Next, W, WN and Ti are formed on the entire bottom and side surfaces in the gate groove 15 by atomic layer chemical vapor deposition.
A discrete ultrathin film 12 containing a high melting point metal such as N or MoN is formed. In this case, too, the discrete ultrathin film 1 containing a high melting point metal is used.
2, the coverage of the adsorption site of the Si oxide film is preferably about 1/3 to 1/10. Discrete ultra-thin film 12
An Si oxide film 13 having a thickness of 5
It is formed to a thickness of about 10 to 10 nm (FIG. 6F).

Next, poly S containing phosphorus or the like in high concentration on the entire surface
A gate groove 15 is buried by forming an interlayer insulating film 10 of i and WSi. Then, unnecessary WSi and poly-Si are removed by a CMP method to planarize the structure, thereby forming a gate electrode G (FIG. 9G). Then, a connection hole is opened in the interlayer insulating film 10 to form a plug 11 made of W, poly-Si, or the like, thereby obtaining a nonvolatile semiconductor memory element 201 of the present invention (FIG. 1H).

In this nonvolatile semiconductor memory element 201,
Before the formation of the discrete ultrathin film 12 containing a high melting point metal, ion implantation for introducing impurities of the source S or the drain D is performed before the formation of the discrete ultrathin film 12 containing the high melting point metal. There is no step of heating above ℃. Therefore, the trap once formed exists in a stable state. In addition, since the diffusion of the high melting point metal, which is the center of the trap, is reduced, the tunnel oxide film 4 can be formed thin. Therefore, the writing voltage can be reduced.

Embodiment 3 FIG. 3 is a manufacturing process diagram of still another embodiment of the present invention, in which a discrete ultrathin film containing a high melting point metal and a Si oxide film are multilayered and the write voltage is multivalued. It is.

That is, the nonvolatile semiconductor memory element 202
In the manufacturing process, a discrete ultrathin film 12 containing a high-melting-point metal is formed and a thickness of 0.5
A silicon oxide film 13 having a thickness of about 1.0 nm is formed.
(A)) Subsequently, the formation of the discrete ultrathin film 12 containing the high melting point metal and the formation of the Si oxide film 13 are repeated again, and the multilayer film 16 of the discrete ultrathin film 12 containing the high melting point metal and the Si oxide film 13 is repeated. Is formed to form the gate insulating film 7 (FIG. 3B). Next, poly-Si and WSi containing phosphorus or the like at a high concentration are sequentially deposited on the multilayer film 16 to form a gate electrode layer 8 (FIG. 3C), which is patterned into a gate electrode G (FIG. 3C). (D), the low-concentration region LDD _a ,
LDD _b, formation of side wall 9, introduction of impurity of source S and drain D, formation of interlayer insulating film 10, plug 1
1 are sequentially formed (FIG. 3E).

The gate insulating film 7 of the non-volatile semiconductor storage element 202 thus obtained has a trap having a higher density, so that a difference in threshold voltage corresponding to ON / OFF can be made large.

[0044]

According to the nonvolatile semiconductor memory element of the present invention, traps in the gate insulating film of the MONOS type flash memory are formed by a discrete ultrathin film of a high melting point metal by an atomic layer chemical vapor deposition method or the like. Since the trap is formed, the position, density, and the like of the trap can be formed with good control, and the data retention characteristics and the endurance for repeated writing / erasing can be improved.

Further, the nonvolatile semiconductor memory element of the present invention can make a difference between threshold voltages corresponding to ON / OFF large, so that it is suitable for multi-valued memory.

Further, by forming a discrete ultra-thin film of a high melting point metal after ion implantation into a source or a drain, the heat history at the time of device fabrication can be reduced. Therefore, the diffusion of traps in the gate insulating film can be reduced, and the writing voltage can be further reduced.

Further, by forming a multilayer of a discrete ultrathin film of a high melting point metal and a Si oxide film, the total trap density can be increased, and the difference between ON / OFF threshold voltages can be further increased. Become.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a manufacturing process of a nonvolatile semiconductor memory element according to an embodiment.

FIG. 2 is an explanatory diagram of a manufacturing process of the nonvolatile semiconductor memory element according to the embodiment.

FIG. 3 is an explanatory diagram of a manufacturing process of the nonvolatile semiconductor memory element of the embodiment.

FIG. 4 is an explanatory diagram of a manufacturing process of a conventional MONOS type flash memory.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Si substrate, 2 ... Element isolation film, 3 ... Embedding layer, 4
... tunnel oxide film, 5 ... Si nitride film, 6 ... Si oxide film, 7 ... gate insulating film, 8 ... gate electrode layer, 9 ...
Side wall, 10 ... interlayer insulating film, 11: plug, 12 ...
Discrete ultra-thin film containing refractory metal, 13 ... Si oxide film,
14: Poly Si film (dummy gate), 15: Gate groove, 16: Multi-layer film of discrete ultra-thin film containing refractory metal and Si oxide film, 200, 201, 202: Non-volatile semiconductor storage element, DG: Dummy gate , G: gate electrode,

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F001 AA11 AC02 AC06 AD17 AG02 AG12 AG21 AG30 5F083 EP17 EP50 EP63 EP68 ER03 ER09 GA21 JA35 MA06 MA19 NA01 NA08 PR12 PR21 PR34 PR39 PR40 5F101 BA41 BC02 BC11 BD07 BH02 BH03 BH09 BH16

Claims (11)

[Claims] A non-volatile semiconductor memory, wherein a gate insulating film having a discrete trap is provided between a gate electrode of a MIS transistor and a semiconductor substrate, and data is stored and erased by charging and discharging the trap. A non-volatile semiconductor storage element, wherein a discrete ultrathin film containing a high melting point metal is provided as a trap formation layer in a gate insulating film. 2. The non-volatile semiconductor storage element according to claim 1, wherein the trap formation layer is made of a W, WN, TiN or MoN discrete ultra-thin film formed by an atomic layer chemical vapor deposition method. 3. The method according to claim 1, wherein the discrete ultrathin film containing a high melting point metal has a Si oxide film formed by thermal oxidation on the semiconductor substrate side and a Si oxide film formed by a CVD method on the gate electrode side of the trap. Non-volatile semiconductor storage element. 4. The discrete ultra-thin film containing a high melting point metal has a Si oxide film by thermal oxidation on the semiconductor substrate side and a Si nitride film by a CVD method on the gate electrode side of the trap. Non-volatile semiconductor storage element. 5. The non-volatile memory according to claim 1, wherein a plurality of discrete ultra-thin layers containing a high melting point metal and Si oxide films or Si nitride films are alternately stacked in the gate insulating film. Semiconductor element. 6. A nonvolatile semiconductor memory in which a gate insulating film having a discrete trap is provided between a gate electrode of a MIS transistor and a semiconductor substrate, and data is stored and erased by charging and discharging the trap. A method for manufacturing a device, comprising: after forming a Si oxide film on a semiconductor substrate,
As a trap formation layer on the Si oxide film, a discrete ultrathin film containing a refractory metal is formed by atomic layer chemical vapor deposition, and a gate insulating film is formed by further laminating an insulating film. A method for manufacturing a nonvolatile semiconductor memory element. 7. W, WN, T
7. The method according to claim 6, wherein a discrete ultrathin film of iN or MoN is formed. 8. An Si oxide film is formed on a surface of a semiconductor substrate by thermal oxidation, and a discrete ultra-thin layer containing a refractory metal is formed on the Si oxide film by atomic layer chemical vapor deposition.
7. An Si oxide film is formed thereon by a CVD method.
Or a method for manufacturing a nonvolatile semiconductor memory element according to item 7. 9. An Si oxide film is formed on a surface of a semiconductor substrate by thermal oxidation, and a discrete ultra-thin layer containing a refractory metal is formed on the Si oxide film by atomic layer chemical vapor deposition.
7. An Si nitride film is formed thereon by a CVD method.
Or a method for manufacturing a nonvolatile semiconductor memory element according to item 7. 10. The method for manufacturing a nonvolatile semiconductor memory device according to claim 6, wherein after forming a source and a drain of the transistor, a discrete ultrathin layer containing a high melting point metal is formed. 11. The nonvolatile semiconductor device according to claim 6, wherein formation of a discrete ultrathin layer containing a high melting point metal and formation of a Si oxide film or a Si nitride film are alternately repeated a plurality of times. Production method.