WO2002045175A1 - Nonvolatile storage device and method for manufacturing nonvolatile storage device - Google Patents

Nonvolatile storage device and method for manufacturing nonvolatile storage device Download PDF

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Publication number
WO2002045175A1
WO2002045175A1 PCT/JP2001/010395 JP0110395W WO0245175A1 WO 2002045175 A1 WO2002045175 A1 WO 2002045175A1 JP 0110395 W JP0110395 W JP 0110395W WO 0245175 A1 WO0245175 A1 WO 0245175A1
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Prior art keywords
gate electrode
memory element
nonvolatile memory
floating gate
insulating film
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PCT/JP2001/010395
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French (fr)
Japanese (ja)
Inventor
Toshiharu Suzuki
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Sony Corporation
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Application filed by Sony Corporation filed Critical Sony Corporation
Priority to EP01999009A priority Critical patent/EP1267416A1/en
Priority to KR1020027009759A priority patent/KR20020074219A/en
Publication of WO2002045175A1 publication Critical patent/WO2002045175A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Definitions

  • the present invention relates to a nonvolatile memory element and a method of manufacturing the nonvolatile memory element.
  • the present invention relates to a nonvolatile memory element that retains data irrespective of ON / OFF of an element power supply and a method of manufacturing the nonvolatile memory element, and more particularly to a nonvolatile memory element having a FG type configuration and a nonvolatile memory element. And a method for manufacturing the element.
  • the MIS (Metal Insulated Semiconductor) type SI uses a large number of non-volatile storage elements that can hold data regardless of whether the element power is turned on or off. I have. Examples of such nonvolatile memory elements include FG (Floating Gate) nonvolatile memory elements and MONOS (metal—Si oxide film—Si nitride film—Si oxide film—Si substrate) nonvolatile memory. The elements are typical ones. In each case, electric charges are charged by a predetermined method to record information.
  • the FG type nonvolatile memory element is configured by providing a floating gate electrode such as polycrystalline Si in the middle of the gate insulating film of the MIS transistor, and by charging the floating gate electrode, The information is recorded by changing the threshold of the MIS transistor.
  • 8A to 8D and 9A to 9C are cross-sectional structural views for explaining a manufacturing process of the FG type nonvolatile memory element 100 in the conventional configuration.
  • the element isolation layer 102 is formed on the Si substrate 101 by using a wrench or the like. Then, a buried layer 103 for adjusting a threshold voltage is formed by using a normal ion implantation method.
  • this Si substrate 101 is thermally oxidized at a temperature of about 800 ° C. for about 15 minutes, and as shown in FIG. 8B ′, the surface of the Si substrate 101 is about 8 nm in thickness.
  • a tunnel oxide film 104 is formed.
  • a floating gate electrode 105 is formed on the surface with a thickness of about 6 nm using a method such as ordinary LP-CVD or plasma CVD, and an interlayer insulating film is further formed on the surface. Make up 106.
  • FIG. 8C is an enlarged view showing a detailed configuration of the tunnel oxide film 104, the floating gate electrode 105, and the interlayer insulating film 106 configured as described above.
  • the interlayer insulating film 106 has a three-layer structure of a Si oxide film 106a, a Si nitride film 106b, and a Si oxide film 106c. I have.
  • the Si oxide film 106a is formed to a thickness of about 5 nm by thermally oxidizing the surface of the floating gate electrode 105 at a temperature of about 850 ° C for about 10 minutes.
  • the Si nitride film 106 b is formed on the surface of the Si oxide film 106 a by using a conventional LP-CVD method, plasma CVD method, or the like to form a 12 nm thick Si nitride film 106 13.
  • the Si oxide film 106c is formed to a thickness of about 6 nm by thermal oxidation of the surface of the Si nitride film 106b.
  • a control electrode 107 is formed by polycrystalline Si, WSi, etc. containing a high concentration of phosphorus, etc., and further, using the conventional lithography technology and RIE technology, FIG. 9A The pattern of the control electrode 107 is formed as shown in FIG. Using the patterned control electrode 107 as a mask, an impurity such as phosphorus or arsenic is ion-implanted at a concentration of, for example, about 5 ⁇ 10 3 / cm 2 to form a low-concentration drain 1. 08 a and 108 b are formed.
  • a gate sidewall 109 is formed using a normal CVD and etch-back method, and the gate sidewall 109 is used as a mask to form phosphorus, arsenic, or the like.
  • the impurity is ion-implanted at, for example, about 5 ⁇ 10 15 cm 2 to form a source 110 a and a drain 11 Ob.
  • heat treatment is performed at about 900 ° C using a normal electric heating furnace for about 30 minutes, or at about 150 ° C using rapid thermal processing (RTP).
  • RTP rapid thermal processing
  • a heat treatment of about 10 seconds is performed to form an interlayer film 11 such as a Si oxide film, a plug 11 of W or polycrystalline Si, and a nonvolatile memory element 10 as shown in FIG. 9C. Configure 0.
  • this nonvolatile memory element 100 a voltage of about +20 V is applied to the control electrode 107 while the Si substrate 101 is grounded, whereby the channel of the Si substrate 101 is Electric charges are injected and accumulated from the region to the floating gate electrode 105 using FN tunnel current or the like.
  • the threshold voltage of the MIS transistor becomes high, and this state of charge accumulation is maintained even after the voltage application to the control electrode 107 is stopped.
  • the nonvolatile memory element 100 has no relation to the on / off of the element power supply. In addition, data can be retained.
  • the M ⁇ N ⁇ S type non-volatile memory element is composed of a metal _S i oxide film _S i nitride film-S i oxide film-S i substrate layer, and includes a Si nitride film and a Si oxide film. By accumulating charges in discrete traps near the boundary with the Si nitride film, the threshold of the transistor is changed and data is retained (IE3 Trans, Electron Dev. ED39 (2), 122 (1983)).
  • FIGS. 10A to 10C and 11A to 11C are cross-sectional structural views for explaining the manufacturing process of the MONOS nonvolatile memory element 200.
  • FIGS. 10A to 10C and 11A to 11C are cross-sectional structural views for explaining the manufacturing process of the MONOS nonvolatile memory element 200.
  • an element isolation layer 202 is formed on the Si substrate 201 by a sharpener wrench or the like. Further, a buried layer 203 for adjusting the threshold voltage is formed by using a normal ion implantation method.
  • the Si substrate 201 is thermally oxidized at a temperature of about 800 ° C. for about 15 minutes, and as shown in FIG. 10B, the surface of the Si substrate 201 is about 3 nm in thickness.
  • a tunnel oxide film 204 is formed.
  • a Si nitride film 205 having a thickness of about 8 nm is formed on the surface by using a method such as ordinary LP-CVD or plasma CVD.
  • a Si oxide film 206 of about 3 to 5 nm is formed.
  • a control electrode 207 is formed by polycrystalline Si, WSi or the like containing a high concentration of phosphorus or the like. And conventional lithographic techniques, and R Using 1E technology, a pattern of control electrodes 207 as shown in FIG. 11B is formed.
  • an impurity such as phosphorus or arsenic is ion-implanted at a concentration of, for example, about 5 ⁇ 10 3 / cm 2 , as shown in FIG. 11C.
  • Low-concentration drain 208 a Low-concentration drain 208 a
  • the gate sidewall 2 0 9 as a mask, phosphorous, impurities such as arsenic, for example, 5 X 1 0 15 / cm implanted at about 2, source one scan 2 1 0 a, to form a drain 2 1 0 b.
  • heat treatment is performed at about 900 ° C using a normal electric heating furnace for about 30 minutes, or at about 150 ° C using rapid thermal processing (RTP).
  • a heat treatment is performed for about 10 seconds to form an interlayer film 211 such as a Si oxide film, a plug of W or polycrystalline Si, and a nonvolatile memory element 200 is formed.
  • the Si nitride film 205 itself and the Si ON film near the interface between the Si oxide film 206 and the Si nitride film 205 are formed.
  • a trap for storing charge is formed in the transition layer, and the charge is discretely stored in this trap, so that the data can be maintained regardless of whether the power supply of the device is on or off. .
  • the conventional FG type non-volatile memory element 100 has a floating gate electrode 105 when there is a leak between the floating gate electrode 105 and the Si substrate 101. Therefore, it is extremely difficult to reduce the thickness of the tunnel oxide film 104 because all charges accumulated in the tunnel oxide film will be lost. Therefore, charge is injected from the channel region of the Si substrate 101 to the floating gate electrode 105. It is necessary to increase the applied voltage between the Si substrate 101 and the floating gate electrode 105 necessary for the insertion, and the data write voltage applied to the entire nonvolatile memory element 100 must also be increased. There is a problem that it is not.
  • the M ⁇ N 0 S type nonvolatile memory element 200 has a tunnel oxide film 204 and a Si oxide film near the interface between the Si oxide film 206 and the Si nitride film 205.
  • a tunnel oxide film 204 By storing charges discretely in traps in the ON transition layer, data is retained, so even if the tunnel oxide film 204 partially leaks, it is still stored in the traps. No charge is lost. Therefore, the thickness of the tunnel oxide film 204 can be made small, so that the write voltage can be kept low over time, and the FG type nonvolatile memory element 100 The size of the element can be reduced.
  • the trap density of the MONOS nonvolatile memory element 200 is not sufficiently high, and the charge density that can be stored is about five orders of magnitude lower than that of the FG nonvolatile memory element 100. There is a point.
  • the M ⁇ N ⁇ S type nonvolatile memory element 200 it is not easy to form this trap with good reproducibility of the density and good controllability.
  • the element 200 also has problems that the data retention time (Data Retention) and the write / erase repetition resistance (endurance) are not sufficient.
  • the present invention has been made in view of such a point, and has a sufficient storage.
  • a nonvolatile memory element and a method for manufacturing the nonvolatile memory element which can reduce the write voltage and reduce the size of the element while ensuring the accumulated charge density, the data retention time, and the write / erase repetition resistance. With the goal. Disclosure of the invention
  • the present invention provides a nonvolatile memory element that retains data regardless of the on / off state of a device power supply, a semiconductor substrate serving as a base, and a non-volatile memory element formed on the semiconductor substrate.
  • the surface of the floating gate electrode is formed in an uneven shape, the surface area of the floating gate electrode is increased, and the capacitance between the control electrode and the floating gate electrode can be increased. This makes it possible to increase the ratio (coupling ratio) of the capacitance between the control electrode and the floating gate electrode to the total capacitance of the floating gate electrode, and to increase the voltage applied to the entire nonvolatile memory element.
  • the voltage applied between the semiconductor substrate and the floating gate electrode can be increased without increasing the voltage.
  • the uneven shape of the floating gate electrode is an uneven shape on a substantially hemisphere.
  • the uneven shape of the floating gate electrode has a particle size of 10 nm to 2 O nm. +
  • the interlayer insulating film is formed by using an atomic layer chemical vapor deposition method.
  • the floating gate electrode and the interlayer insulating film are formed so as to surround the bottom and side surfaces of the control electrode.
  • the nonvolatile memory element of the present invention is for a flash memory.
  • a tunnel oxide film forming step of forming a tunnel oxide film on a base semiconductor substrate A floating gate electrode forming step of forming a floating gate electrode having an uneven surface on the film; an interlayer insulating film forming step of forming an interlayer insulating film on the floating gate electrode; A control electrode forming step of forming a control electrode on an insulating film.
  • the surface of the floating gate electrode is formed in an uneven shape, the surface area of the floating gate electrode is increased, and the capacitance between the control electrode and the floating gate electrode can be increased. This makes it possible to increase the ratio of the capacitance between the control electrode and the floating gate electrode to the total capacitance of the floating gate electrode (coupling ratio).
  • Semiconductor base without increasing the applied voltage It is possible to increase the voltage applied between the plate and the floating gate electrode.
  • the interlayer insulating film is formed by using an atomic layer chemical vapor deposition method.
  • the method for manufacturing a nonvolatile memory element according to the present invention preferably includes a tunnel oxide film formed by a tunnel oxide film forming step, a floating gate electrode forming step, an interlayer insulating film forming step, and a control electrode forming step.
  • the method further includes a gate electrode etching step of forming the gate electrode by etching the gate electrode, the interlayer insulating film, and the control electrode.
  • a dummy gate electrode forming step of forming a dummy gate electrode on the tunnel oxide film, and the dummy gate electrode is etched.
  • the floating gate electrode forming step the floating gate electrode is formed along the inner wall surface of the gate side wall, and the interlayer insulating film forming step is performed along the inner wall surface of the floating gate electrode. Then, an interlayer insulating film is formed.
  • FIGS. 1A to 1B are structural diagrams showing a configuration of a nonvolatile memory element.
  • FIG. 2A to 2C illustrate a manufacturing process of a nonvolatile memory element.
  • FIG. 2 is a cross-sectional structural diagram for the purpose of
  • 3A to 3C are cross-sectional structural views for explaining a manufacturing process of a nonvolatile memory element.
  • 4A to 4B are cross-sectional structural views showing the configuration of the nonvolatile memory element.
  • 5A to 5C are cross-sectional structural views for explaining a manufacturing process of the nonvolatile memory element.
  • 6A to 6C are cross-sectional structural views for explaining a manufacturing process of the nonvolatile memory element.
  • 7A to 7C are cross-sectional structural views for explaining a manufacturing process of the nonvolatile memory element.
  • 8A to 8D are cross-sectional structural views for describing a manufacturing process of an FG type nonvolatile memory element in a conventional configuration.
  • 9A to 9C are cross-sectional structural views for explaining a manufacturing process of an FG nonvolatile memory element in a conventional configuration.
  • FIGS. 10A to 10C are cross-sectional structural views for explaining the manufacturing process of the MONOS nonvolatile memory element.
  • FIGS. 11A to 11C are cross-sectional structural views for explaining the manufacturing process of the M0N ⁇ S type nonvolatile memory element. ⁇ Best mode for carrying out the invention
  • FIG. 1A to 1B are structural diagrams showing a configuration of a nonvolatile memory element 1 in the present embodiment.
  • FIG. 1A shows a cross-sectional view of the nonvolatile memory element 1
  • FIG. 1B shows a section A of FIG. 1A.
  • FIG. 3 shows an enlarged sectional view.
  • the non-volatile memory element 1 is, for example, an FG type non-volatile memory element used for flash memory, and is mainly composed of a Si substrate 2 serving as a base semiconductor substrate, an element isolation layer 3, i
  • the buried layer 4 for adjusting the threshold voltage formed in the substrate 2, the tunnel oxide film 5 formed on the Si substrate 2, and the tunnel oxide film 5 The formed contact gate electrode 6, the interlayer insulating film 7 formed on the contact gate electrode 6, the control electrode 8 formed on the interlayer insulating film 7, and the surface of the Si substrate 2 Low-concentration drains 9a and 9b formed, source 11a, drain lib, gate sidewall 10 formed on top of Si substrate 2, interlayer film 12 and plug 13 .
  • the floating gate electrode 6 of the nonvolatile memory element 1 is formed so that the surface has an uneven shape, thereby increasing the surface area of the floating gate electrode 6.
  • the configuration is such that the capacitance between the floating gate electrode 6 and the control electrode 8 can be increased.
  • the concavo-convex shape here may be any shape such as a substantially hemispherical shape such as a mushroom shape, a waveform, etc., but the formed surface area of the opening gate electrode 6 has a certain accuracy. A shape that can be formed while being maintained is desirable.
  • FIGS. 3A to 3C are cross-sectional structural views for explaining the manufacturing process of the nonvolatile memory element 1.
  • the manufacturing process of the nonvolatile memory element 1 mainly includes a tunnel oxide film forming step of forming a tunnel oxide film 5 on an Si substrate 2 serving as a base semiconductor substrate, and a surface Uneven shape
  • Forming a gate electrode Forming a gate electrode, forming a gate electrode by etching a tunnel oxide film 5, a floating gate electrode 6, an interlayer insulating film 7, and a control electrode 8, and forming a low concentration drain 9 a, 9b low-concentration drain formation process, gate sidewall 10 formation gate sidewall formation process, source 11a, drain lib formation source, drain formation process, interlayer film 1 2 And a plug forming step of forming the plug 13.
  • an element isolation layer 3 is formed on the Si substrate 2 by means of a sharp wrench or the like, and then a normal ion implantation is performed.
  • the buried layer 4 for adjusting the threshold voltage is formed by using the method.
  • this Si substrate 2 is thermally oxidized at a temperature of about 80 ° t: for about 15 minutes, and a tunnel oxide film of about 8 nm is formed on the surface of the Si substrate 2 as shown in FIG. 2B. 5 is formed (tunnel oxide film forming step). Further, a polycrystalline Si or the like is deposited on the surface of the tunnel oxide film 5 by a chemical vapor deposition (CVD) method or the like performed in a highly airtight CVD apparatus while excluding oxygen. Forming a floating gate electrode 6 having a substantially semicircular uneven shape (hemispherical grain) on the surface as shown in FIG. 1B (floating gate electrode forming step) .
  • CVD chemical vapor deposition
  • Such a hemispherical polysilicon can be achieved, for example, by using silane (S Amorphous silicon is deposited on the surface of the tunnel oxide film 5 by a chemical vapor deposition (CVD) method using iH4) at a temperature of about 550 ° C for about 40 minutes, and the An amorphous silicon film of about O nm is formed, annealed for about 10 minutes, and a hemispherical silicon having a particle size of about 10 nm to 20 nm is grown.
  • silane Silane
  • CVD chemical vapor deposition
  • the next step is to use an ultra-thin ultra-high uniform film formation method such as atomic layer chemical vapor deposition (AL-CVD: atomic layer chemical vapor 1 deposition).
  • A-CVD atomic layer chemical vapor 1 deposition
  • a highly reliable interlayer insulating film 7 such as SiO 2 or Si 3 N 4 is grown on the surface of the contact gate electrode 6 by about 15 nm (interlayer insulating film forming step).
  • the inter-layer insulating film 7 formed here is desirably configured to cover the surface of the hemispherical polysilicon of the floating gate electrode 6 with a uniform thickness.
  • control electrode 8 as shown in FIG. 2C is formed (control electrode forming step). Thereafter, a pattern of the control electrode 8 as shown in FIG. 3 is formed by using a normal lithography technique and an RI technique (gate electrode etching step).
  • the tunnel oxide film forming step, the floating gate electrode forming step, the interlayer insulating film forming step, and the control electrode forming step formed the tunnel oxide film 5, the floating gate electrode 6, and the interlayer insulating film 7 by the gate electrode etching step. Then, the control electrode 8 is etched to form a gate electrode.
  • a gate sidewall 10 is formed using a normal CVD and an etch pack method (gate sidewall forming step). Impurities such as arsenic are ion-implanted at, for example, about 5 ⁇ 10 15 / cm 2 to form a source 11 a and a drain lib (source and drain forming process).
  • the plug 13 is formed (plug forming step) to form the nonvolatile memory element 1 as shown in FIG. 3C.
  • a non-volatile memory element having a floating gate electrode 6 having a hemispherical polysilicon formed on its surface, and an interlayer insulating film 7 formed on the hemispherical silicon in a highly uniform manner.
  • the surface area of the floating gate electrode 6 is increased, and the capacitance between the control electrode 8 and the floating gate electrode 6 can be increased.
  • the ratio (coupling ratio) of the capacitance of the control electrode 8 to the capacitance of the floating gate electrode 6 with respect to the total capacitance of the floating gate electrode 6 can be increased. 1 It is possible to increase the voltage applied between the Si substrate 2 and the floating gate electrode 6 without increasing the write voltage to the whole.
  • the tunnel oxide film 5 is formed on the Si substrate 2 serving as the base, and the floating gate electrode 6 having a hemispherical polysilicon on the surface is formed on the tunnel oxide film 5.
  • Forming the nonvolatile memory element 1 by forming a highly uniform interlayer insulating film 7 on the floating gate electrode 6 and forming a control electrode 8 on the interlayer insulating film 7.
  • the write voltage in the nonvolatile memory element 1 can be reduced, and the required drain withstand voltage can be reduced, so that the element can be downsized.
  • the nonvolatile memory element 1 since the nonvolatile memory element 1 has an FG type configuration, it is possible to ensure sufficient accumulated charge density, data retention time, and write / erase repetition resistance.
  • This embodiment is an application of the first embodiment, and the arrangement of the floating gate electrode 30 and the interlayer insulating film 31 is different from that of the first embodiment.
  • FIG. 4A and 4B are structural views showing the configuration of the nonvolatile memory element 20 according to the present embodiment.
  • FIG. 4A shows a cross-sectional view of the nonvolatile memory element 20
  • FIG. 4B shows an enlarged cross-sectional view of a portion B in FIG. 4A.
  • the non-volatile memory element 20 is, for example, an FG type non-volatile memory element used for flash memory, and mainly includes a Si substrate 21 serving as a base semiconductor substrate, an element isolation layer 22, Si substrate 2
  • the embedded layer 23 for adjusting the threshold voltage, which is formed in 1 the tunnel oxide film 24 formed on the S ⁇ substrate 21 and the tunnel oxide film 24
  • Floating gate electrode 30 formed, interlayer insulating film 31 formed on floating gate electrode 30, control electrode 32 formed on interlayer insulating film 31, formed on surface of Si substrate 21
  • the floating gate electrode 30 and the interlayer insulating film 31 are formed so as to surround the bottom and side surfaces of the control electrode 32, which is different from the first embodiment. .
  • the ratio (coupling ratio) of the capacitance of the control electrode 32 to the floating gate electrode 30 with respect to the total capacitance of the floating gate electrode 30. Can be improved.
  • the floating gate electrode 30 of the nonvolatile memory element 20 is formed to have an uneven shape, thereby increasing the surface area of the floating gate electrode 30 to increase the floating gate electrode.
  • the capacitance between the gate electrode 30 and the control electrode 32 can be increased.
  • the concavo-convex shape here may be any shape such as a substantially hemispherical shape such as a mushroom shape, a waveform, etc., but the surface area of the formed floating gate electrode 30 can be maintained at a certain accuracy. A shape that can be formed is desirable.
  • FIGS. 5A to 5C and FIGS. 7A to 7C are cross-sectional structural views for explaining the manufacturing process of the nonvolatile memory element 20. It is.
  • the manufacturing process of the nonvolatile memory element 20 mainly includes a tunnel oxide film forming step of forming a tunnel oxide film 24 on a Si substrate 21 as a base semiconductor substrate, and a tunnel oxide film 24 Dummy gate electrode forming step to form dummy gate electrode 25, dummy gate electrode etching step to etch dummy gate electrode 25, low concentration drain formation to form low concentration drains 26a and 26b
  • a gate side wall forming step of covering the side surface of the dummy gate electrode 25 with a gate side wall 27, a source forming a source 28a and a drain 28b, a drain forming step, and an interlayer film 29 are formed.
  • an element isolation layer 22 is formed on the Si substrate 21 by a shear wrench or the like, and then a normal ion implantation is performed.
  • the buried layer 23 for adjusting the threshold voltage is formed by using the method.
  • the Si substrate 21 is thermally oxidized at a temperature of about 800 ° C. for about 15 minutes, and a tunnel oxidation of about 8 nm is formed on the surface of the Si substrate 21 as shown in FIG. 5B.
  • Film 24 is formed (tunnel oxide film formation process).
  • the polycrystalline Si A film is deposited to a thickness of about 600 nm to form a dummy gate electrode 25 (dummy gate electrode forming step).
  • a pattern of a dummy gate electrode 25 as shown in FIG. 5C is formed on the laminated structure by using a usual lithography technique and an RIE technique (dummy gate electrode etching step).
  • impurities such as phosphorus and arsenic are ion-implanted using the dummy gate electrode 25 as a mask, for example, at a concentration of about 5 ⁇ 10 13 cm 2 , and a low concentration is formed. Drains 26a and 26 are formed (low concentration drain formation step).
  • a gate sidewall 27 as shown in FIG. 6A is formed using a normal CVD and an etch-back method (gate sidewall formation step), and the gate sidewall 27 is used as a mask, for example, 5X
  • a source 28a and a drain 28b are formed by ion implantation of impurities such as phosphorus and arsenic of about 10 15 / cm 2 (source / drain formation step).
  • heat treatment for about 30 minutes at about 900 ° C using a normal electric heating furnace, or about 10 seconds at about 150 ° C by rapid heat treatment (RTP) Heat treatment is performed to deposit an interlayer film 29 such as a Si oxide film as shown in FIG. 6B (interlayer film forming step).
  • RTP rapid heat treatment
  • the surface of the interlayer film 29 is flattened by using a flattening technique such as CMP for an ordinary insulating film, and the dummy gate electrode 25 is exposed to the surface. Then, the dummy gate electrode 25 is removed by an ordinary etching method (dummy gate electrode removal step).
  • Electrode 30 is formed (floating gate forming step).
  • the formation of the floating gate electrode 30 here is performed along the inner wall surface of the gate side wall 27 and the upper surface of the interlayer film 29, and the formation of such a hemispherical polysilicon is performed.
  • the surface (inner wall surface) of the floating gate electrode 30 is then formed by atomic layer chemical vapor deposition at a temperature of about 400 ° C. along the high uniform S i ⁇ 2, S i 3 N 4 or the like of reliable interlayer insulating film 3 1 to 1 5 nm about sedimentary (interlayer insulating film forming step), and et to, the surface
  • polycrystalline Si to which phosphorus or the like is added is deposited to form a control electrode 32 (control electrode forming step).
  • FIG. 7B Thereafter, as shown in FIG. 7B, these are flattened and the gate section is formed. Other than the floating gate electrode 30, interlayer insulating film 31, and control electrode 32 are removed (planarization step). Finally, as shown in FIG. 7C, the source 28 a and the drain 2 are removed. A plug 33 of polycrystalline Si or the like to be a connection portion of 8b is formed (plug forming step).
  • the floating gate electrode 30 and the interlayer insulating film 31 each having a hemispherical polysilicon formed on the surface are used to cover the non-volatile memory element 20 so as to surround the bottom and side surfaces of the control electrode 32.
  • the capacitance between the control electrode 32 and the floating gate electrode 30 is compared with the case of the first embodiment.
  • the floating gate electrode 30 having a hemispherical polysilicon on the surface is formed so as to surround the bottom surface and the side surface of the control electrode 32, thereby constituting the nonvolatile memory element 20.
  • the ratio of the capacitance between the control electrode 32 and the floating gate electrode 30 (coupling ratio) with respect to the total capacitance of the floating gate electrode 30 can be greatly increased.
  • the voltage applied between the Si substrate 21 and the floating gate electrode 30 can be increased without increasing the voltage applied to the entire element 20, and the voltage applied to the entire nonvolatile memory element 20 can be increased. The pressure can be reduced.
  • the drain withstand voltage required for the drain can be reduced, and the size of the element can be reduced.
  • nonvolatile memory element 20 has an FG type configuration, it is possible to ensure a sufficient accumulated charge density, data retention time, and write / erase repetition resistance.
  • the gate length is 0.18 m
  • the gate width is 1.0 m
  • the coupling ratio is about 0.36
  • the coupling ratio of the nonvolatile memory element 20 of this embodiment is about 0.9, and it is possible to improve the coupling ratio by about 2.5 times. it can. Therefore, for example, when a writing voltage of 20 V is required in the conventional configuration, writing can be performed with a writing voltage of about 8.7 V in this embodiment.
  • a highly uniform interlayer insulating film is formed on the surface of a floating gate electrode having a hemispherical polysilicon by using atomic layer chemical vapor deposition.
  • any method other than atomic layer chemical vapor deposition may be used to form an interlayer insulating film as long as it is a manufacturing method capable of forming an ultrathin film almost conformally.
  • a tunnel oxide film is formed on a semiconductor substrate serving as a base, and a floating gate electrode formed so as to have an uneven shape on the surface is formed on the tunnel oxide film.
  • the FG type non-volatile memory element was constructed by forming an interlayer insulating film on the floating gate electrode with high uniformity and forming a control electrode on the interlayer insulating film. It is possible to reduce the write voltage and reduce the size of the element while ensuring the charge density, the data retention time, and the write / erase repetition resistance.

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Abstract

The reduction of write voltage and the miniaturization of a nonvolatile storage device while securing a sufficient stored charge density, data holding time, and write/erase repetition resistance. A tunnel oxide film (5) is formed over an Si substrate (2) serving as the base. A floating gate electrode (6) having uneven semispherical polysilicon on the surface is formed over the tunnel oxide film (5). An interlayer insulation film (7) of uniform height is formed over the uneven floating gate electrode (6). A control electrode (8) is formed over the interlayer insulation film (7). Thus, a nonvolatile storage device (1) is constituted.

Description

明細書 不揮発性記憶素子及び不揮発性記憶素子の製造方法 技術分野  TECHNICAL FIELD The present invention relates to a nonvolatile memory element and a method of manufacturing the nonvolatile memory element.
本発明は、 素子電源のオン ' オフに関係なくデータの保持を行 う不揮発性記憶素子及び不揮発性記憶素子の製造方法に関し、 特 に、 F G型の構成をとる不揮発性記憶素子及び不揮発性記憶素子 の製造方法に関する。 背景技術  The present invention relates to a nonvolatile memory element that retains data irrespective of ON / OFF of an element power supply and a method of manufacturing the nonvolatile memory element, and more particularly to a nonvolatile memory element having a FG type configuration and a nonvolatile memory element. And a method for manufacturing the element. Background art
M I S (Metal Insulated Semiconductor) 型し S I には、 デ —夕を保持する記憶素子として、 素子電源のオン · オフに関係な くデータを保持することが可能な不揮発性記憶素子が数多く用 い られている。 このような不揮発性記憶素子と しては、 F G (Floating Gate) 型不揮発性記憶素子、 M O N O S (金属— S i 酸化膜一 S i 窒化膜一 S i 酸化膜一 S i基板）型不揮発性記憶 素子が代表的なものであり、 いずれも、 所定の方法によって電荷 を帯電させ、 情報の記録を行、、う。  The MIS (Metal Insulated Semiconductor) type SI uses a large number of non-volatile storage elements that can hold data regardless of whether the element power is turned on or off. I have. Examples of such nonvolatile memory elements include FG (Floating Gate) nonvolatile memory elements and MONOS (metal—Si oxide film—Si nitride film—Si oxide film—Si substrate) nonvolatile memory. The elements are typical ones. In each case, electric charges are charged by a predetermined method to record information.
まず、 従来構成における F G型不揮発性記憶素子の製造プロセ スについて説明する。  First, the manufacturing process of the conventional FG type nonvolatile memory element will be described.
F G型の不揮発性記憶素子は、 M I S型 トランジスタのゲート 絶縁膜の中間に多結晶 S i 等のフローティ ングゲー ト電極を設 けることによって構成され、 このフローティ ングゲ一 ト電極を帯 電させることにより、 M I S型トランジスタの閾値を変化させ、 情報を記録する。 第 8 A〜 8 D図及び第 9 A〜 9 C図は、 従来構成における F G 型の不揮発性記憶素子 1 0 0 の製造プロセスを説明するための 断面構造図である。 The FG type nonvolatile memory element is configured by providing a floating gate electrode such as polycrystalline Si in the middle of the gate insulating film of the MIS transistor, and by charging the floating gate electrode, The information is recorded by changing the threshold of the MIS transistor. 8A to 8D and 9A to 9C are cross-sectional structural views for explaining a manufacturing process of the FG type nonvolatile memory element 100 in the conventional configuration.
F G型の不揮発性記憶素子 1 0 0 を製造する場合、 まず、 第 8 A図に示すように、 S i基板 1 0 1 にシャ口一 ト レンチ等によつ て素子分離層 1 0 2 を形成し、 さ らに、 通常のイオン注入法を用 い、 閾値電圧調整のための埋め込み層 1 0 3 を形成する。  When manufacturing the FG type non-volatile memory element 100, first, as shown in FIG. 8A, the element isolation layer 102 is formed on the Si substrate 101 by using a wrench or the like. Then, a buried layer 103 for adjusting a threshold voltage is formed by using a normal ion implantation method.
次に、 この S i 基板 1 0 1 を 8 0 0 °C程度の温度で 1 5分程度 熱酸化させ、 第 8 B'図に示すように、 S i 基板 1 0 1 の表面に 8 n m程度の トンネル酸化膜 1 0 4を形成する。 さ らに、 その表面 に、 通常の L P— C V D、 プラズマ C VD等の方法を用い、 フロ —ティ ングゲー ト電極 1 0 5を 6 n m程度の厚みで構成し、 また さらにその表面に層間絶縁膜 1 0 6を構成する。  Next, this Si substrate 101 is thermally oxidized at a temperature of about 800 ° C. for about 15 minutes, and as shown in FIG. 8B ′, the surface of the Si substrate 101 is about 8 nm in thickness. A tunnel oxide film 104 is formed. In addition, a floating gate electrode 105 is formed on the surface with a thickness of about 6 nm using a method such as ordinary LP-CVD or plasma CVD, and an interlayer insulating film is further formed on the surface. Make up 106.
第 8 C図は、 このよう に構成される トンネル酸化膜 1 0 4、 フ ローテイ ングゲー ト電極 1 0 5及び層間絶縁膜 1 0 6の詳細構 成を示した拡大図である。 第 8 C図に示すよう に、 層間絶縁膜 1 0 6は、 S i 酸化膜 1 0 6 a、 S i窒化膜 1 0 6 b、 S i 酸化膜 1 0 6 cの三層構造となっている。 S i酸化膜 1 0 6 aは、 フロ 一ティ ングゲー ト電極 1 0 5 の表面を 8 5 0 °C程度の温度で 1 0分間程度熱酸化させることによ り、 5 n m程度の厚みで形成さ れ、 S i 窒化膜 1 0 6 bは、 通常の L P— C V D、 プラズマ C V D等の方法を用い、 S i酸化膜 1 0 6 aの表面に S i 窒化膜 1 0 6 13を 1 2 n m程度堆積させることによって形成され、 S i酸化 膜 1 0 6 cは、 S.i 窒化膜 1 0 6 bの表面の熱酸化によって 6 n m程度の厚みに形成される。  FIG. 8C is an enlarged view showing a detailed configuration of the tunnel oxide film 104, the floating gate electrode 105, and the interlayer insulating film 106 configured as described above. As shown in FIG. 8C, the interlayer insulating film 106 has a three-layer structure of a Si oxide film 106a, a Si nitride film 106b, and a Si oxide film 106c. I have. The Si oxide film 106a is formed to a thickness of about 5 nm by thermally oxidizing the surface of the floating gate electrode 105 at a temperature of about 850 ° C for about 10 minutes. Then, the Si nitride film 106 b is formed on the surface of the Si oxide film 106 a by using a conventional LP-CVD method, plasma CVD method, or the like to form a 12 nm thick Si nitride film 106 13. The Si oxide film 106c is formed to a thickness of about 6 nm by thermal oxidation of the surface of the Si nitride film 106b.
層間絶縁膜 1 0 6が形成されると、 次に、 第 8 D図に示すよう に、 燐等を高濃度に含む多結晶 S i、 W S i 等によ り制御電極 1 0 7が形成され、 さ らに、 通常のリ ソグラフィ一技術、 及び R I E技術を用い、 第 9 A図に示すような制御電極 1 0 7 のパターン 形成を行う。 また、 このパターン形成された制御電極 1 0 7 をマ スク と して、 燐、 砒素等の不純物を、 例えば 5 X 1 0 | 3 / c m 2 程度の濃度でイオン注入し、 低濃度 ドレイ ン 1 0 8 a、 1 0 8 b を形成する。 After the interlayer insulating film 106 is formed, next, as shown in FIG. 8D In addition, a control electrode 107 is formed by polycrystalline Si, WSi, etc. containing a high concentration of phosphorus, etc., and further, using the conventional lithography technology and RIE technology, FIG. 9A The pattern of the control electrode 107 is formed as shown in FIG. Using the patterned control electrode 107 as a mask, an impurity such as phosphorus or arsenic is ion-implanted at a concentration of, for example, about 5 × 10 3 / cm 2 to form a low-concentration drain 1. 08 a and 108 b are formed.
次に、 第 9 B図に示すよう に、 通常の C V Dとエッチバック法 を用い、 ゲー ト側壁 1 0 9 を形成し、 このゲー ト側壁 1 0 9 をマ スク と して、 燐、 砒素等の不純物を、 例えば 5 X 1 0 1 5ノ c m 2 程度でイオン注入し、 ソース 1 1 0 a、 ドレイ ン 1 1 O b を形成 する。 Next, as shown in FIG. 9B, a gate sidewall 109 is formed using a normal CVD and etch-back method, and the gate sidewall 109 is used as a mask to form phosphorus, arsenic, or the like. The impurity is ion-implanted at, for example, about 5 × 10 15 cm 2 to form a source 110 a and a drain 11 Ob.
最後に、 注入した不純物を活性化させるため、 通常の電気加熱 炉による 9 0 0 °C程度で 3 0分程度の熱処理、 或いは、 急速熱処 理（R T P )による 1 0 5 0 °C程度で 1 0秒程度の熱処理を行い、 S i 酸化膜等の層間膜 1 1 1、 W或いは多結晶 S i のプラグ 1 1 2 を形成し、 第 9 C図に示すような不揮発性記憶素子 1 0 0 を構 成する。  Finally, in order to activate the implanted impurities, heat treatment is performed at about 900 ° C using a normal electric heating furnace for about 30 minutes, or at about 150 ° C using rapid thermal processing (RTP). A heat treatment of about 10 seconds is performed to form an interlayer film 11 such as a Si oxide film, a plug 11 of W or polycrystalline Si, and a nonvolatile memory element 10 as shown in FIG. 9C. Configure 0.
この不揮発性記憶素子 1 0 0 において、 S i 基板 1 0 1 を接地 した状態で、 制御電極 1 0 7 に + 2 0 V程度の電圧を加え、 これ により、 S i 基板 1 0 1 のチャ ンネル領域からフロ一ティ ングゲ 一ト電極 1 0 5 に対し、 F N トンネル電流等を利用して電荷が注 入、 蓄積される。 この電荷の蓄積状態においては、 M I S型 ト ラ ンジス夕の閾値電圧が高く なり、 また、 この電荷の蓄積状態は、 制御電極 1 0 7への電圧印加を止めた後も保持される。 これによ り、 不揮発性記憶素子 1 0 0 は、 素子電源のオン · オフに関係な く、 データの保持を行う ことが可能となる。 In this nonvolatile memory element 100, a voltage of about +20 V is applied to the control electrode 107 while the Si substrate 101 is grounded, whereby the channel of the Si substrate 101 is Electric charges are injected and accumulated from the region to the floating gate electrode 105 using FN tunnel current or the like. In this state of charge accumulation, the threshold voltage of the MIS transistor becomes high, and this state of charge accumulation is maintained even after the voltage application to the control electrode 107 is stopped. As a result, the nonvolatile memory element 100 has no relation to the on / off of the element power supply. In addition, data can be retained.
次に、 従来構成における M〇 N〇 S型不揮発性記憶素子の製造 プロセスについて説明する。  Next, a description will be given of a manufacturing process of the M〇N〇S type nonvolatile memory element in the conventional configuration.
M〇 N〇 S型の不揮発性記憶素子は、 金属 _ S i酸化膜 _ S i 窒化膜一 S i酸化膜— S i 基板の層によって構成され、 S i 窒化 膜、 及び S i酸化膜と S i窒化膜との境界近傍に存在する離散的 な トラップに電荷を蓄積することによ り、 トランジスタの閾値を 変化させ、 データ の保持を行う （ IE3 Trans, Electron Dev. ED39 (2) , 122 (1983))。  The M〇N〇S type non-volatile memory element is composed of a metal _S i oxide film _S i nitride film-S i oxide film-S i substrate layer, and includes a Si nitride film and a Si oxide film. By accumulating charges in discrete traps near the boundary with the Si nitride film, the threshold of the transistor is changed and data is retained (IE3 Trans, Electron Dev. ED39 (2), 122 (1983)).
第 1 0 A〜 1 0 C図及び第 1 1 A〜 1 1 C図は、 MO N O S型 の不揮発性記憶素子 2 0 0 の製造プロセスを説明するための断 面構造図である。  FIGS. 10A to 10C and 11A to 11C are cross-sectional structural views for explaining the manufacturing process of the MONOS nonvolatile memory element 200. FIGS.
M〇 N O S型の不揮発性記憶素子 2 0 0 を製造する場合、 まず 第 1 O A図に示すように、 S i 基板 2 0 1 にシャ 口一 ト レンチ等 によって素子分離層 2 0 2 を形成し、 さ らに、 通常のイオン注入 法を用い、 閾値電圧調整のための埋め込み層 2 0 3 を形成する。  When manufacturing the M〇NOS type nonvolatile memory element 200, first, as shown in FIG. 1A, an element isolation layer 202 is formed on the Si substrate 201 by a sharpener wrench or the like. Further, a buried layer 203 for adjusting the threshold voltage is formed by using a normal ion implantation method.
次に、 この S i基板 2 0 1 を 8 0 0 °C程度の温度で 1 5分程度 熱酸化させ、 第 1 0 B図に示すよう に、 S i基板 2 0 1の表面に 3 n m程度の トンネル酸化膜 2 0 4を形成する。 さ らに、 その表 面に、 通常の L P— C VD、 プラズマ C V D等の方法を用い、 S i 窒化膜 2 0 5 を 8 n m程度の厚みで形成する。 次に、 この S i 窒化膜 2 0 5 を再酸化させることによ り、 3〜 5 n m程度の S i 酸化膜 2 0 6を形成する。  Next, the Si substrate 201 is thermally oxidized at a temperature of about 800 ° C. for about 15 minutes, and as shown in FIG. 10B, the surface of the Si substrate 201 is about 3 nm in thickness. A tunnel oxide film 204 is formed. Further, a Si nitride film 205 having a thickness of about 8 nm is formed on the surface by using a method such as ordinary LP-CVD or plasma CVD. Next, by re-oxidizing the Si nitride film 205, a Si oxide film 206 of about 3 to 5 nm is formed.
S i 酸化膜 2 0 6が形成されると、 次に、 第 1 1 A図に示すよ うに、 燐等を高濃度に含む多結晶 S i 、 WS i 等により制御電極 2 0 7が形成され、 さ らに、 通常のリ ソグラフィー技術、 及び R 1 E技術を用い、 第 1 1 B図に示すような制御電極 2 0 7のパ夕 ーン形成を行う。 After the Si oxide film 206 is formed, as shown in FIG. 11A, a control electrode 207 is formed by polycrystalline Si, WSi or the like containing a high concentration of phosphorus or the like. And conventional lithographic techniques, and R Using 1E technology, a pattern of control electrodes 207 as shown in FIG. 11B is formed.
また、 このパターン形成された 御電極 2 0 7をマスクとして 燐、 砒素等の不純物を、 例えば 5 X 1 0 |3/ c m2程度の濃度でィ オン注入し、 第 1 1 C図に示すような低濃度 ドレイ ン 2 0 8 a、Using the patterned control electrode 207 as a mask, an impurity such as phosphorus or arsenic is ion-implanted at a concentration of, for example, about 5 × 10 3 / cm 2 , as shown in FIG. 11C. Low-concentration drain 208 a,
2 0 8 bを形成する。 Form 2 08 b.
次に、 通常の C V Dとエッチバック法を用い、 ゲー ト側壁 2 0 9 を形成し、 このゲー ト側壁 2 0 9 をマスク として、 燐、 砒素等 の不純物を、 例えば 5 X 1 015/ c m 2程度でイオン注入し、 ソ一 ス 2 1 0 a、 ドレイ ン 2 1 0 bを形成する。 Next, using a conventional CVD and etchback method to form a gate side wall 2 0 9, the gate sidewall 2 0 9 as a mask, phosphorous, impurities such as arsenic, for example, 5 X 1 0 15 / cm implanted at about 2, source one scan 2 1 0 a, to form a drain 2 1 0 b.
最後に、 注入した不純物を活性化させるため、 通常の電気加熱 炉による 9 0 0 °C程度で 3 0分程度の熱処理、 或いは、 急速熱処 理（R T P )による 1 0 5 0 °C程度で 1 0秒程度の熱処理を行い、 S i酸化膜等の層間膜 2 1 1、 W或いは多結晶 S i のプラグ 2 1 2を形成し、 不揮発性記憶素子 2 0 0 を構成する。  Finally, in order to activate the implanted impurities, heat treatment is performed at about 900 ° C using a normal electric heating furnace for about 30 minutes, or at about 150 ° C using rapid thermal processing (RTP). A heat treatment is performed for about 10 seconds to form an interlayer film 211 such as a Si oxide film, a plug of W or polycrystalline Si, and a nonvolatile memory element 200 is formed.
このよう に形成された不揮発性記憶素子 2 0 0では、 S i窒化 膜 2 0 5 自身、 及び、 S i酸化膜 2 0 6 と S i 窒化膜 2 0 5の界 面近傍にある S i O N遷移層に電荷を蓄積すべき ト ラ ップが形 成され、 この トラ ップに離散的に電荷を蓄積することにより、 素 子電源のオン · オフに関係なく、 デ一夕の保持を行う。  In the nonvolatile memory element 200 thus formed, the Si nitride film 205 itself and the Si ON film near the interface between the Si oxide film 206 and the Si nitride film 205 are formed. A trap for storing charge is formed in the transition layer, and the charge is discretely stored in this trap, so that the data can be maintained regardless of whether the power supply of the device is on or off. .
' しかし、 従来の F G型の不揮発性記憶素子 1 0 0 は、 フローテ イ ングゲー ト電極 1 0 5 と、 S i基板 1 0 1 との間にリークがあ ると、 フローティ ングゲー ト電極 1 0 5 に蓄積された全ての電荷 が失われてしまう ことになるため、 トンネル酸化膜 1 0 4を薄く することはきわめて困難である。 そのため、 S i 基板 1 0 1のチ ヤ ンネル領域から フローティ ングゲー ト電極 1 0 5へ電荷を注 入する際に必要な、 S i 基板 1 0 1 —フローティ ングゲート電極 1 0 5間の印加電圧を高くする必要があり、 不揮発性記憶素子 1 0 0全体に印加するデータ書き込み電圧も高く しなければなら ないという問題点がある。 'However, the conventional FG type non-volatile memory element 100 has a floating gate electrode 105 when there is a leak between the floating gate electrode 105 and the Si substrate 101. Therefore, it is extremely difficult to reduce the thickness of the tunnel oxide film 104 because all charges accumulated in the tunnel oxide film will be lost. Therefore, charge is injected from the channel region of the Si substrate 101 to the floating gate electrode 105. It is necessary to increase the applied voltage between the Si substrate 101 and the floating gate electrode 105 necessary for the insertion, and the data write voltage applied to the entire nonvolatile memory element 100 must also be increased. There is a problem that it is not.
また、 データ書き込み電圧を高く した場合、 ドレイン 1 1 O b の耐圧を確保するために、 ドレイン 1 1 0 bの微細化が困難とな り、 不揮発性記憶素子 1 0 0 の小型化が図れないという問題点も ある。  In addition, when the data write voltage is increased, it is difficult to miniaturize the drain 110 b in order to secure the withstand voltage of the drain 110 b, and the miniaturization of the nonvolatile memory element 100 cannot be achieved. There is also a problem.
また、 M〇 N 0 S型の不揮発性記憶素子 2 0 0は、 トンネル酸 化膜 2 0 4、 及び、 S i酸化膜 2 0 6 と S i窒化膜 2 0 5 の界面 近傍にある S i O N遷移層の トラップに電荷を離散的に蓄積す ることにより、 データの保持を行う こととな'るため、 トンネル酸 化膜 2 0 4が部分的にリークしても、 トラップに蓄積された電荷 が全て失われることはない。 そのため、 トンネル酸化膜 2 0 4の 膜厚を薄く構成することができるため、 デ一夕の書き込み電圧を 低く抑えることが可能であるとともに、 F G型の不揮発性記憶素 子 1 0 0に比べ、 素子の小型化を図ることができる。  In addition, the M〇N 0 S type nonvolatile memory element 200 has a tunnel oxide film 204 and a Si oxide film near the interface between the Si oxide film 206 and the Si nitride film 205. By storing charges discretely in traps in the ON transition layer, data is retained, so even if the tunnel oxide film 204 partially leaks, it is still stored in the traps. No charge is lost. Therefore, the thickness of the tunnel oxide film 204 can be made small, so that the write voltage can be kept low over time, and the FG type nonvolatile memory element 100 The size of the element can be reduced.
しかし、 M O N O S型の不揮発性記憶素子 2 0 0の トラップ密 度は十分高いとはいえず、 蓄積できる電荷密度は、 F G型の不揮 発性記憶素子 1 0 0に比べ 5桁程度低いという問題点がある。  However, the trap density of the MONOS nonvolatile memory element 200 is not sufficiently high, and the charge density that can be stored is about five orders of magnitude lower than that of the FG nonvolatile memory element 100. There is a point.
また、 M〇 N〇 S型の不揮発性記憶素子 2 0 0において、 この トラップを、 密度の再現性よく、 かつ、 制御性よく、 形成するこ とは容易ではなく、 微細化された不揮発性記憶素子 2 0 0では、 デ一夕保持時間 （Da t a Re t e n U o n )、 書き込み/消去繰り返し耐 性 （エンデュ ンス） が十分ではないという問題点もある。  Also, in the M〇N〇S type nonvolatile memory element 200, it is not easy to form this trap with good reproducibility of the density and good controllability. The element 200 also has problems that the data retention time (Data Retention) and the write / erase repetition resistance (endurance) are not sufficient.
本発明はこのような点に鑑みてなされたものであり、十分な蓄 積電荷密度、 データ保持時間、 及び書き込み/消去繰り返し耐性 を確保しつつ、 書き込み電圧の低減、 素子の小型化を図ることが 可能な不揮発性記憶素子及び不揮発性記憶素子の製造方法を提 供することを目的とする。 発明の開示 The present invention has been made in view of such a point, and has a sufficient storage. Provided are a nonvolatile memory element and a method for manufacturing the nonvolatile memory element, which can reduce the write voltage and reduce the size of the element while ensuring the accumulated charge density, the data retention time, and the write / erase repetition resistance. With the goal. Disclosure of the invention
本発明では上記課題を解決するために、 素子電源のオン · オフ に関係なくデ一夕の保持を行う不揮発性記憶素子において、 ベ一 スとなる半導体基板と、 前記半導体基板上に形成されたトンネル 酸化膜と、 前記トンネル酸化膜上に、 表面に凹凸形状を有するよ うに形成されたフローティ ングゲート電極と、 前記フローティ ン グゲー ト電極上に形成された層間絶縁膜と、 前記層間絶縁膜上に 構成された制御電極とを有することを特徴とする不揮発性記憶 素子が提供される。  In order to solve the above-described problems, the present invention provides a nonvolatile memory element that retains data regardless of the on / off state of a device power supply, a semiconductor substrate serving as a base, and a non-volatile memory element formed on the semiconductor substrate. A tunnel oxide film; a floating gate electrode formed on the tunnel oxide film so as to have an uneven surface; an interlayer insulating film formed on the floating gate electrode; And a control electrode configured as described above.
ここで、 フローティ ングゲー ト電極の表面が凹凸形状に形成さ れることによって、 フローティ ングゲー ト電極の表面積が大きく なり、 制御電極とフローティ ングゲ一ト電極との静電容量を大き く とることができる。 これにより、 フローティ ングゲート電極の 全静電容量に対する制御電極とフローティ ングゲ一ト電極との 静電容量の比 （カップリ ング比） を大きくすることができ、 不揮 発性記憶素子全体への印加電圧を増加させることなく、 半導体基 板一フローティ ングゲー ト電極間への印加電圧を大きくする こ とが可能となる。  Here, since the surface of the floating gate electrode is formed in an uneven shape, the surface area of the floating gate electrode is increased, and the capacitance between the control electrode and the floating gate electrode can be increased. This makes it possible to increase the ratio (coupling ratio) of the capacitance between the control electrode and the floating gate electrode to the total capacitance of the floating gate electrode, and to increase the voltage applied to the entire nonvolatile memory element. The voltage applied between the semiconductor substrate and the floating gate electrode can be increased without increasing the voltage.
また、 本発明の不揮発性記憶素子において、 好ましくは、 フロ —ティ ングゲート電極が有する凹凸形状は、 略半球上の凹凸形状 である。 また、 本発明の不揮発性記憶素子において、 好ましく は、 フロ 一ティ ングゲ一 ト電極が有する凹凸形状は、 粒径が 1 0 n m〜 2 O n mに形成される。 + また、 本発明の不揮発性記憶素子.において、 好ましく は、 層間 絶縁膜は、 原子層化学的気相成長法を用いて形成される。 In the nonvolatile memory element of the present invention, preferably, the uneven shape of the floating gate electrode is an uneven shape on a substantially hemisphere. In the nonvolatile memory element of the present invention, preferably, the uneven shape of the floating gate electrode has a particle size of 10 nm to 2 O nm. + In the nonvolatile memory element of the present invention, preferably, the interlayer insulating film is formed by using an atomic layer chemical vapor deposition method.
また、 本発明の不揮発性記憶素子において、 好ましく は、 フロ 一ティ ングゲ一 卜電極及び層間絶縁膜は、 制御電極の底面及び側 面を取り囲むように形成される。  Further, in the nonvolatile memory element of the present invention, preferably, the floating gate electrode and the interlayer insulating film are formed so as to surround the bottom and side surfaces of the control electrode.
また、 好ましく は、 本発明の不揮発性記憶素子は、 フラッシュ メモリ用である。  Preferably, the nonvolatile memory element of the present invention is for a flash memory.
また、 素子電源のオン · オフに関係なくデータの保持を行う不 揮発性記憶素子の製造方法において、 ベースとなる半導体基板上 に トンネル酸化膜を形成する トンネル酸化膜形成工程と、 前記ト ンネル酸化膜上に、 表面が凹凸形状を有するフローティ ングゲ一 ト電極を形成するフローティ ングゲー ト電極形成工程と、 前記フ ローティ ングゲ一ト電極上に層間絶縁膜を形成する層間絶縁膜 形成工程と、 前記層間絶縁膜上に制御電極を形成する制御電極形 成工程とを有する ことを特徴とする不揮発性記憶素子の製造方 法が提供される。  In addition, in a method of manufacturing a nonvolatile memory element that retains data irrespective of ON / OFF of an element power supply, a tunnel oxide film forming step of forming a tunnel oxide film on a base semiconductor substrate; A floating gate electrode forming step of forming a floating gate electrode having an uneven surface on the film; an interlayer insulating film forming step of forming an interlayer insulating film on the floating gate electrode; A control electrode forming step of forming a control electrode on an insulating film.
ここで、 フローティ ングゲー ト電極の表面が凹凸形状に形成さ れることによって、 フローティ ングゲー ト電極の表面積が大きく なり、 制御電極とフローティ ングゲー ト電極との静電容量を大き く とることができる。 これにより、 フローティ ングゲ一 ト電極の 全静電容量に対する、 制御電極とフローティ ングゲー ト電極との 静電容量の比 （カ ップリ ング比） を大きくする ことができ、 不揮 発性記憶素子全体への印加電圧を増加させることなく 、 半導体基 板一フ ローティ ングゲ一 卜電極間への印加電圧を大きくする こ とが可能となる。 Here, since the surface of the floating gate electrode is formed in an uneven shape, the surface area of the floating gate electrode is increased, and the capacitance between the control electrode and the floating gate electrode can be increased. This makes it possible to increase the ratio of the capacitance between the control electrode and the floating gate electrode to the total capacitance of the floating gate electrode (coupling ratio). Semiconductor base without increasing the applied voltage It is possible to increase the voltage applied between the plate and the floating gate electrode.
また、 本発明の不揮発性記憶素子の製造方法において、 好まし く は、 層間絶縁膜形成工程は、 原子層化学的気相成長法を用いて 層間絶縁膜の形成を行う。  In the method for manufacturing a nonvolatile memory element of the present invention, preferably, in the step of forming an interlayer insulating film, the interlayer insulating film is formed by using an atomic layer chemical vapor deposition method.
また、 本発明の不揮発性記憶素子の製造方法は、 好ましく は、 ト ンネル酸化膜形成工程、 フローティ ングゲー ト電極形成工程、 層間絶縁膜形成工程及び制御電極形成工程によって形成された トンネル酸化膜、 フローティ ングゲー ト電極、 層間絶縁膜及び制 御電極をエッチングし、 ゲー ト電極の形成を行うゲ一 ト電極エツ チング工程をさらに有する。  The method for manufacturing a nonvolatile memory element according to the present invention preferably includes a tunnel oxide film formed by a tunnel oxide film forming step, a floating gate electrode forming step, an interlayer insulating film forming step, and a control electrode forming step. The method further includes a gate electrode etching step of forming the gate electrode by etching the gate electrode, the interlayer insulating film, and the control electrode.
また、 本発明の不揮発性記憶素子の製造方法は、 好ましく は、 ト ンネル酸化膜形成工程の後、 ト ンネル酸化膜上にダミーゲー ト 電極を形成するダミーゲー ト電極形成工程と、 ダミーゲー ト電極 をエッチングするダミーゲ一 卜電極エッチング工程と、 ダミーゲ ー ト電極の側面をゲー ト側壁で覆うゲー ト側壁形成工程と、 ゲー ト側壁の形成後、 ダミーゲー ト電極を除去するダミーゲー ト電極 除去工程と、 をさ らに有し、 フローティ ングゲー ト電極形成工程 は、 ゲー ト側壁の内壁面に沿って、 フロ一ティ ングゲー ト電極の 形成を行い、 層間絶縁膜形成工程は、 フローティ ングゲー ト電極 の内壁面に沿って、 層間絶縁膜の形成を行う。 図面の簡単な説明  Preferably, in the method for manufacturing a nonvolatile memory element according to the present invention, after the tunnel oxide film forming step, a dummy gate electrode forming step of forming a dummy gate electrode on the tunnel oxide film, and the dummy gate electrode is etched. A dummy gate electrode etching step of covering the side surface of the dummy gate electrode with a gate sidewall, and a dummy gate electrode removing step of removing the dummy gate electrode after the formation of the gate sidewall. In the floating gate electrode forming step, the floating gate electrode is formed along the inner wall surface of the gate side wall, and the interlayer insulating film forming step is performed along the inner wall surface of the floating gate electrode. Then, an interlayer insulating film is formed. BRIEF DESCRIPTION OF THE FIGURES
第 1 A〜 1 B図は、 不揮発性記憶素子の構成を示した構造図で ある。  1A to 1B are structural diagrams showing a configuration of a nonvolatile memory element.
第 2 A〜 2 C図は、 不揮発性記憶素子の製造プロセスを説明す るための断面構造図である。 2A to 2C illustrate a manufacturing process of a nonvolatile memory element. FIG. 2 is a cross-sectional structural diagram for the purpose of
第 3 A〜 3 C図は、 不揮発性記憶素子の製造プロセスを説明す るための断面構造図である。  3A to 3C are cross-sectional structural views for explaining a manufacturing process of a nonvolatile memory element.
第 4 A〜 4 B図は、 不揮発性記憶素子の構成を示した断面構造 図である。  4A to 4B are cross-sectional structural views showing the configuration of the nonvolatile memory element.
第 5 A〜 5 C図は、 不揮発性記憶素子の製造プロセスを説明す るための断面構造図である。  5A to 5C are cross-sectional structural views for explaining a manufacturing process of the nonvolatile memory element.
第 6 A〜 6 C図は、不揮発性記憶素子の製造プロセスを説明す るための断面構造図である。  6A to 6C are cross-sectional structural views for explaining a manufacturing process of the nonvolatile memory element.
第 7 A〜 7 C図は、 不揮発性記憶素子の製造プロセスを説明す るための断面構造図である。  7A to 7C are cross-sectional structural views for explaining a manufacturing process of the nonvolatile memory element.
第 8 A〜 8 D図は、 従来構成における F G型の不揮発性記憶素 子の製造プロセスを説明するための断面構造図である。  8A to 8D are cross-sectional structural views for describing a manufacturing process of an FG type nonvolatile memory element in a conventional configuration.
第 9 A〜 9 C図は、 従来構成における F G型の不揮発性記憶素 子の製造プロセスを説明するための断面構造図である。  9A to 9C are cross-sectional structural views for explaining a manufacturing process of an FG nonvolatile memory element in a conventional configuration.
第 1 0 A〜 1 0 C図は、 M O N O S型の不揮発性記憶素子の製 造プロセスを説明するための断面構造図である。  FIGS. 10A to 10C are cross-sectional structural views for explaining the manufacturing process of the MONOS nonvolatile memory element.
第 1 1 A〜 1 1 C図は、 M 0 N〇 S型の不揮発性記憶素子の製 造プロセスを説明するための断面構造図である。 · 発明を実施するための最良の形態  FIGS. 11A to 11C are cross-sectional structural views for explaining the manufacturing process of the M0N〇S type nonvolatile memory element. · Best mode for carrying out the invention
以下、 本発明の実施の形態を図面を参照して説明する。  Hereinafter, embodiments of the present invention will be described with reference to the drawings.
まず、 本発明における第 1 の実施の形態について説明する。 第 1 A〜 1 B図は、 本形態における不揮発性記憶素子 1 の構成 を示した構造図である。 ここで、 第 1 A図は、 不揮発性記憶素子 1 の断面図を示しており、 第 1 B図は、 第 1 A図における A部の 拡大断面図を示している。 First, a first embodiment of the present invention will be described. 1A to 1B are structural diagrams showing a configuration of a nonvolatile memory element 1 in the present embodiment. Here, FIG. 1A shows a cross-sectional view of the nonvolatile memory element 1, and FIG. 1B shows a section A of FIG. 1A. FIG. 3 shows an enlarged sectional view.
不揮発性記憶素子 1 は、 例えば、 フラッ シュメモリ用として利 用'される F G型の不揮発性記憶素子であ り、 主に、 ベースとなる 半導体基板である S i 基板 2、 素子分離層 3 、 S i 基板 2内に構 成された閾値電圧調整のための埋め込み層 4 、 S i 基板 2上に形 成された ト ンネル酸化膜 5、 トンネル酸化膜 5上に、 表面が凹凸 形状を有するよう に形成されるフ口一ティ ングゲー ト電極 6、 フ 口一ティ ングゲー ト電極 6上に形成された層間絶縁膜 7、 層間絶 緣膜 7上に構成された制御電極 8 、 S i 基板 2表面に形成された 低濃度 ドレイ ン 9 a 、 9 b、 ソース 1 1 a、 ドレイ ン l i b、 S i 基板 2上面に形成されたゲー ト側壁 1 0 、 層間膜 1 2及びブラ グ 1 3 によって構成される。  The non-volatile memory element 1 is, for example, an FG type non-volatile memory element used for flash memory, and is mainly composed of a Si substrate 2 serving as a base semiconductor substrate, an element isolation layer 3, i The buried layer 4 for adjusting the threshold voltage formed in the substrate 2, the tunnel oxide film 5 formed on the Si substrate 2, and the tunnel oxide film 5 The formed contact gate electrode 6, the interlayer insulating film 7 formed on the contact gate electrode 6, the control electrode 8 formed on the interlayer insulating film 7, and the surface of the Si substrate 2 Low-concentration drains 9a and 9b formed, source 11a, drain lib, gate sidewall 10 formed on top of Si substrate 2, interlayer film 12 and plug 13 .
第 1 B図に示すよう に、 不揮発性記憶素子 1 のフ口一ティ ング ゲート電極 6 は、 表面が凹凸形状を有するよう に形成されており これによ り、 フローティ ングゲー ト電極 6 の表面積を拡大させ、 フローティ ングゲー ト電極 6 と制御電極 8 との間の静電容量を 大きく とる ことができる構成となっている。 ここでの凹凸形状は きのこ型のような略半球状、 波形等、 特にどのような凹凸形状で あってもよいが、 形成されたフ口一ティ ングゲー ト電極 6 の表面 積が一定の精度を保って形成できる形状が望ましい。  As shown in FIG. 1B, the floating gate electrode 6 of the nonvolatile memory element 1 is formed so that the surface has an uneven shape, thereby increasing the surface area of the floating gate electrode 6. The configuration is such that the capacitance between the floating gate electrode 6 and the control electrode 8 can be increased. The concavo-convex shape here may be any shape such as a substantially hemispherical shape such as a mushroom shape, a waveform, etc., but the formed surface area of the opening gate electrode 6 has a certain accuracy. A shape that can be formed while being maintained is desirable.
次に、 不揮発性記憶素子 1 の製造プロセスについて説明する。 第 2 A〜 2 C図及び第 3 A〜 3 C図は、 不揮発性記憶素子 1 の 製造プロセスを説明するための断面構造図である。  Next, a manufacturing process of the nonvolatile memory element 1 will be described. 2A to 2C and FIGS. 3A to 3C are cross-sectional structural views for explaining the manufacturing process of the nonvolatile memory element 1. FIG.
不揮発性記憶素子 1 の製造プロセスは、 主に、 ベースとなる半 導体基板である S i 基板 2 上に ト ンネル酸化膜 5 を形成する ト ンネル酸化膜形成工程、 トンネル酸化膜 5上に、 表面に凹凸形状 を有するフローティ ングゲー ト電極 6 を形成するフ ローティ ン グゲー ト電極形成工程、 フローティ ングゲー ト電極 6上に層間絶 縁膜 7 を形成する層間絶縁膜形成工程、 層間絶縁膜 7上に制御電 極 8 を形成する制御電極形成工程、 トンネル酸化膜 5、 フローテ ィ ングゲ一 ト電極 6、 層間絶縁膜 7及び制御電極 8 をエッチング し、 ゲー ト電極の形成を行うゲー ト電極エッチング工程、 低濃度 ドレイン 9 a、 9 bを形成する低濃度 ドレイ ン形成工程、 ゲー ト 側壁 1 0を形成するゲー ト側壁形成工程、 ソース 1 1 a、 ドレイ ン l i bを形成するソース、 ドレイ ン形成工程、 層間膜 1 2 を形 成する層間膜形成工程、 及びプラグ 1 3を形成するプラグ形成ェ 程によって構成されている。 The manufacturing process of the nonvolatile memory element 1 mainly includes a tunnel oxide film forming step of forming a tunnel oxide film 5 on an Si substrate 2 serving as a base semiconductor substrate, and a surface Uneven shape A floating gate electrode forming step of forming a floating gate electrode 6 having a structure, an interlayer insulating film forming step of forming an interlayer insulating film 7 on the floating gate electrode 6, and a control electrode 8 on the interlayer insulating film 7 Forming a gate electrode, forming a gate electrode by etching a tunnel oxide film 5, a floating gate electrode 6, an interlayer insulating film 7, and a control electrode 8, and forming a low concentration drain 9 a, 9b low-concentration drain formation process, gate sidewall 10 formation gate sidewall formation process, source 11a, drain lib formation source, drain formation process, interlayer film 1 2 And a plug forming step of forming the plug 13.
以下、 これらの各工程を順次説明していく。  Hereinafter, each of these steps will be sequentially described.
不揮発性記憶素子 1 を製造する場合、 まず、 第 2 A図に示すよ う に、 S i基板 2 にシャ口一 ト レンチ等によって素子分離層 3を 形成し、 さ らに、 通常のイオン注入法を用い、 閾値電圧調整のた めの埋め込み層 4を形成する。  In the case of manufacturing the nonvolatile memory element 1, first, as shown in FIG. 2A, an element isolation layer 3 is formed on the Si substrate 2 by means of a sharp wrench or the like, and then a normal ion implantation is performed. The buried layer 4 for adjusting the threshold voltage is formed by using the method.
次に、 この S i 基板 2 を 8 0 ◦ t:程度の温度で 1 5分程度熱酸 化させ、 第 2 B図に示すように、 S i 基板 2の表面に 8 n m程度 の トンネル酸化膜 5 を形成する （ ト ンネル酸化膜形成工程）。 さ らに、 気密性の高い C V D装置において酸素を排除した状態で行 われる化学的気相成長法 （ C V D) 等によ り、 トンネル酸化膜 5 の表面に、 多結晶 S i 等を堆積させ、 第 1 B図に示したような表 面に略半円状の凹凸形状 （半球状ポ リ シコ ン ： Hemispherical Grain) を有するフローティ ングゲー ト電極 6 を形成する （フロ 一ティ ングゲー ト電極形成工程）。 このような半球状ポリ シコン の形成は、 例えば、 超高真空対応の C VD装置内でのシラン （ S i H4) を用いた化学的気相成長法 （ C V D ) 等によ り、 5 5 0 °C 程度の温度で 4 0分程度、 アモルフ ァスシリ コンを トンネル酸化 膜 5の表面に体積させ、 1 0 O n m程度のアモルファスシリ コン 膜を形成し、 さ らに、 1 0分程度のァニールを行い、 粒径 1 O n m〜 2 0 n m程度の半球状ポリ シコ ンを成長させる ことによつ て行われる。 Next, this Si substrate 2 is thermally oxidized at a temperature of about 80 ° t: for about 15 minutes, and a tunnel oxide film of about 8 nm is formed on the surface of the Si substrate 2 as shown in FIG. 2B. 5 is formed (tunnel oxide film forming step). Further, a polycrystalline Si or the like is deposited on the surface of the tunnel oxide film 5 by a chemical vapor deposition (CVD) method or the like performed in a highly airtight CVD apparatus while excluding oxygen. Forming a floating gate electrode 6 having a substantially semicircular uneven shape (hemispherical grain) on the surface as shown in FIG. 1B (floating gate electrode forming step) . The formation of such a hemispherical polysilicon can be achieved, for example, by using silane (S Amorphous silicon is deposited on the surface of the tunnel oxide film 5 by a chemical vapor deposition (CVD) method using iH4) at a temperature of about 550 ° C for about 40 minutes, and the An amorphous silicon film of about O nm is formed, annealed for about 10 minutes, and a hemispherical silicon having a particle size of about 10 nm to 20 nm is grown. Will be
フローティ ングゲート電極 6が形成されると、 次に、 原子層化 学的気相成長法 （A L— C V D :A t o m i c L a y e r C h e m i c a 1 V a p o r D e p o s i t i o n )等の超薄 超高均一な成膜法により、 フ口一ティ ングゲ一 ト電極 6の表面に S i 02、 S i 3N4等の信頼性の高い層間絶縁膜 7 を 1 5 n m程度 成長させる （層間絶縁膜形成工程）。 なお、 ここで形成される層 間絶縁膜 7は、 フローティ ングゲー ト電極 6の半球状ポリ シコン の表面を均一な厚みで覆うように構成されることが望ましい。 層間絶縁膜 7が形成されると、 次に、 通常の L P— C VD等に よって、 層間絶縁膜 7の表面に燐等を高濃度に含む多結晶 S i 、 W S i 等を堆積させ、 第 2 C図に示すような制御電極 8が形成さ れる （制御 ϋ極形成工程）。 その後、 通常のリソグラフィー技術、 及び R I Ε技術を用い、 第 3 Α図に示すような制御電極 8 のパ夕 —ン形成を行う （ゲ一 ト電極エッチング工程）。 このゲー ト電極 エッチング工程によって、 トンネル酸化膜形成工程、 フローティ ングゲー ト電極形成工程、 層間絶縁膜形成工程及び制御電極形成 工程によって形成された トンネル酸化膜 5、 フローティ ングゲー ト電極 6、 層間絶縁膜 7及び制御電極 8がエッチングされ、 ゲー ト電極の形成が行われる。 Once the floating gate electrode 6 is formed, the next step is to use an ultra-thin ultra-high uniform film formation method such as atomic layer chemical vapor deposition (AL-CVD: atomic layer chemical vapor 1 deposition). As a result, a highly reliable interlayer insulating film 7 such as SiO 2 or Si 3 N 4 is grown on the surface of the contact gate electrode 6 by about 15 nm (interlayer insulating film forming step). The inter-layer insulating film 7 formed here is desirably configured to cover the surface of the hemispherical polysilicon of the floating gate electrode 6 with a uniform thickness. After the interlayer insulating film 7 is formed, next, polycrystalline Si, WSi, etc. containing a high concentration of phosphorus or the like is deposited on the surface of the interlayer insulating film 7 by ordinary LP-C VD or the like. The control electrode 8 as shown in FIG. 2C is formed (control electrode forming step). Thereafter, a pattern of the control electrode 8 as shown in FIG. 3 is formed by using a normal lithography technique and an RI technique (gate electrode etching step). The tunnel oxide film forming step, the floating gate electrode forming step, the interlayer insulating film forming step, and the control electrode forming step formed the tunnel oxide film 5, the floating gate electrode 6, and the interlayer insulating film 7 by the gate electrode etching step. Then, the control electrode 8 is etched to form a gate electrode.
次に、 このパターン形成された制御電極 8をマスク として、燐、 砒素等の不純物を、例えば 5 X I 0 | 3/ c m 2程度の濃度でイオン 注入し、 低濃度 ドレイ ン 9 a 、 9 b を形成する （低濃度ドレイ ン 形成工程）。 Next, using the patterned control electrode 8 as a mask, phosphorus, Impurities such as arsenic, for example, 5 XI 0 | 3 / cm 2 about concentration and ion implantation to form low concentration drain 9 a, 9 b (low concentration drain forming step).
次に、 第 3 B図に示すよう に、 通常の C V Dとエッチパック法 を用い、 ゲー ト側壁 1 0 を形成し （ゲー ト側壁形成工程）、 この ゲー ト側壁 1 0 をマスクとして、 燐、 砒素等の不純物を、 例えば 5 X 1 0 1 5 / c m 2程度でイオン注入し、 ソース 1 1 a、 ドレイ ン l i bを形成する （ソース、 ドレイ ン形成工程）。 Next, as shown in FIG. 3B, a gate sidewall 10 is formed using a normal CVD and an etch pack method (gate sidewall forming step). Impurities such as arsenic are ion-implanted at, for example, about 5 × 10 15 / cm 2 to form a source 11 a and a drain lib (source and drain forming process).
最後に、 注入し fこ不純物を活性化させるため、 通常の電気加熱 炉による 9 0 0 °C程度で 3 0分程度の熱処理、 或いは、 急速熱処 理（ R T P ) による 1 0 5 0 °C程度で 1 0秒程度の熱処理を行い、 ソース 1 1 a、 ドレイ ン 1 l bの接続部となる S i 酸化膜等の層 間膜 1 2 (層間膜形成工程）、 W或いは多結晶 S i のプラグ 1 3 を形成し （プラグ形成工程）、 第 3 C図に示すような不揮発性記 憶素子 1 を構成する。  Finally, to activate the impurities, heat treatment for about 30 minutes at about 900 ° C using a normal electric heating furnace or about 150 ° C using rapid thermal processing (RTP) Heat treatment for about 10 seconds is performed for about 10 seconds, and the inter-layer film 12 (inter-layer film forming process) such as Si oxide film to be the connection part of source 11a and drain 1 lb, W or polycrystalline Si The plug 13 is formed (plug forming step) to form the nonvolatile memory element 1 as shown in FIG. 3C.
以上のよう に表面に半球状ポリ シコ ンが形成されたフローテ ィ ングゲ一 ト電極 6、 及びこの半球状ポリ シコ ンの上部に高均一 に形成された層間絶縁膜 7 を有する不 発性記憶素子 1 を構成 することによ り、 フローティ ングゲー ト電極 6 の表面積が大きく なり、 制御電極 8 とフローティ ングゲー ト電極 6 との静電容量を 大きく とる ことができる。 これにより、 フローティ ングゲ一 卜電 極 6 の全静電容量に対する、 制御電極 8 とフローティ ングゲー ト 電極 6 との静電容量の比 （カップリ ング比） を大きくすることが でき、 不揮発性記憶率子 1全体への書き込み電圧を増加させるこ となく、 S i 基板 2 —フローティ ングゲ一 ト電極 6 間への印加電 圧を大きくすることが可能となる。 このように、 本形態では、 ベースとなる S i 基板 2上に トンネ ル酸化膜 5 を形成し、 トンネル酸化膜 5上に、 表面に半球状ポリ シコンを有するフロ一ティ ングゲ一 ト電極 6 を形成し、 フローテ イ ングゲー ト電極 6上に高均一の層間絶縁膜 7 を形成し、 層間絶 縁膜 7 上に制御電極 8 を形成する こ とによ り不揮発性記憶素子 1 を構成することとしたため、 カップリ ング比を大きく とること が可能となり、 不揮発性記憶素子 1全体への書き込み電圧を増加 させることなく、 S i 基板 2 —フ口一ティ ングゲー ト電極 6間へ の印加電圧を増加させることが可能となる。 As described above, a non-volatile memory element having a floating gate electrode 6 having a hemispherical polysilicon formed on its surface, and an interlayer insulating film 7 formed on the hemispherical silicon in a highly uniform manner. By configuring 1, the surface area of the floating gate electrode 6 is increased, and the capacitance between the control electrode 8 and the floating gate electrode 6 can be increased. As a result, the ratio (coupling ratio) of the capacitance of the control electrode 8 to the capacitance of the floating gate electrode 6 with respect to the total capacitance of the floating gate electrode 6 can be increased. 1 It is possible to increase the voltage applied between the Si substrate 2 and the floating gate electrode 6 without increasing the write voltage to the whole. As described above, in this embodiment, the tunnel oxide film 5 is formed on the Si substrate 2 serving as the base, and the floating gate electrode 6 having a hemispherical polysilicon on the surface is formed on the tunnel oxide film 5. Forming the nonvolatile memory element 1 by forming a highly uniform interlayer insulating film 7 on the floating gate electrode 6 and forming a control electrode 8 on the interlayer insulating film 7. As a result, it is possible to increase the coupling ratio, and increase the voltage applied between the Si substrate 2 and the opening gate electrode 6 without increasing the write voltage to the entire nonvolatile memory element 1. It becomes possible.
そのため、 不揮発性記憶素子 1 における書き込み電圧を低減さ せることが可能となり、 さ らに、 必要な ドレイ ン耐圧を低減させ る ことができるため、 素子の小型化を図ることが可能となる。 ま た、 不揮発性記憶素子 1 は F G型の構成をとるため、 十分な蓄積 電荷密度、 データ保持時間、 及び書き込み/消去繰り返し耐性を 確保することもできる。  Therefore, the write voltage in the nonvolatile memory element 1 can be reduced, and the required drain withstand voltage can be reduced, so that the element can be downsized. In addition, since the nonvolatile memory element 1 has an FG type configuration, it is possible to ensure sufficient accumulated charge density, data retention time, and write / erase repetition resistance.
次に、 本発明における第 2の実施の形態について説明する。 本形態は、 第 1 の実施の形態の応用例であり、 フ ローティ ング ゲー ト電極 3 0 及び層間絶縁膜 3 1 の配置構成が第 1 の実施の 形態と相違する。  Next, a second embodiment of the present invention will be described. This embodiment is an application of the first embodiment, and the arrangement of the floating gate electrode 30 and the interlayer insulating film 31 is different from that of the first embodiment.
第 4 A〜 4 B図は、 本形態における不揮発性記憶素子 2 0の構 成を示した構造図である。 ここで、 第 4 A図は、 不揮発性記憶素 子 2 0 の断面図を示しており、 第 4 B図は、 第 4 A図における B 部の拡大断面図を示している。  4A and 4B are structural views showing the configuration of the nonvolatile memory element 20 according to the present embodiment. Here, FIG. 4A shows a cross-sectional view of the nonvolatile memory element 20, and FIG. 4B shows an enlarged cross-sectional view of a portion B in FIG. 4A.
不揮発性記憶素子 2 0 は、 例えば、 フラッ シュメモリ用 として 利用される F G型の不揮発性記憶素子であり、 主に、 ベースとな る半導体基板である S i 基板 2 1 、 素子分離層 2 2 、 S i 基板 2 1 内に構成された閾値電圧調整のための埋め込み層 2 3、 S 〖 基 板 2 1上に形成された トンネル酸化膜 2 4、 トンネル酸化膜 2 4 上に、 表面に凹凸形状を有するように形成されたフローティ ング ゲー ト電極 3 0、 フローティ ングゲート電極 3 0上に形成された 層間絶緣膜 3 1、 層間絶縁膜 3 1 上に構成された制御電極 3 2、 S i 基板 2 1表面に形成された低濃度ドレイン 2 6 a、 2 6 b、 ソース 2 8 a、 ドレイン 2 8 b、 S i 基板 2 1上面に形成された ゲー ト側壁 2 7、 層間膜 2 9及びプラグ 3 3によって構成される ここで、 フローティ ングゲ一ト電極 3 0及び層間絶縁膜 3 1 は 制御電極 3 2の底面及び側面を取り囲むように形成されており、 この点が第 1 の実施の形態と相違する点である。 これにより、 第 1 の実施の形態に比べ、 フロ一ティ ングゲート電極 3 0の全静電 容量に対する、 制御電極 3 2 とフローティ ングゲ一ト電極 3 0 と の静電容量の比 （カップリ ング比） を向上させることが可能とな る。 The non-volatile memory element 20 is, for example, an FG type non-volatile memory element used for flash memory, and mainly includes a Si substrate 21 serving as a base semiconductor substrate, an element isolation layer 22, Si substrate 2 The embedded layer 23 for adjusting the threshold voltage, which is formed in 1, the tunnel oxide film 24 formed on the S 〖substrate 21 and the tunnel oxide film 24 Floating gate electrode 30 formed, interlayer insulating film 31 formed on floating gate electrode 30, control electrode 32 formed on interlayer insulating film 31, formed on surface of Si substrate 21 Low-concentration drains 26a, 26b, source 28a, drain 28b, gate sidewall 27 formed on the upper surface of Si substrate 21, interlayer film 29, and plug 33. Here, the floating gate electrode 30 and the interlayer insulating film 31 are formed so as to surround the bottom and side surfaces of the control electrode 32, which is different from the first embodiment. . Thus, as compared with the first embodiment, the ratio (coupling ratio) of the capacitance of the control electrode 32 to the floating gate electrode 30 with respect to the total capacitance of the floating gate electrode 30. Can be improved.
第 4 B図に示すように、 不揮発性記憶素子 2 0 のフローティ ン グゲート電極 3 0は、 凹凸形状を有するように形成されており、 これにより、 フローティ ングゲート電極 3 0の表面積を拡大させ フローティ ングゲー ト電極 3 0 と制御電極 3 2 との間の静電容 量を大きく とることができる構成となっている。 ここでの凹凸形 状は、 きのこ型のような略半球状、 波形等、 特にどのような凹凸 形状であってもよいが、 形成されたフローティ ングゲート電極 3 0の表面積が一定の精度を保って形成できる形状が望ましい。  As shown in FIG. 4B, the floating gate electrode 30 of the nonvolatile memory element 20 is formed to have an uneven shape, thereby increasing the surface area of the floating gate electrode 30 to increase the floating gate electrode. In this configuration, the capacitance between the gate electrode 30 and the control electrode 32 can be increased. The concavo-convex shape here may be any shape such as a substantially hemispherical shape such as a mushroom shape, a waveform, etc., but the surface area of the formed floating gate electrode 30 can be maintained at a certain accuracy. A shape that can be formed is desirable.
次に、 不揮発性記憶素子 2 0の製造プロセスについて説明する, 第 5 A〜 5 C図及び第 7 A〜 7 C図は、 不揮発性記憶素子 2 0 の製造プロセスを説明するための断面構造図である。 不揮発性記憶素子 2 0 の製造プロセスは、 主に、 ベースとなる 半導体基板である S i 基板 2 1 上に ト ンネル酸化膜 2 4 を形成 する トンネル酸化膜形成工程、 トンネル酸化膜 2 4上にダミーゲ — ト電極 2 5 を形成するダミーゲー ト電極形成工程、 ダミーゲー ト電極 2 5 をエッチングするダミ一ゲー ト電極エッチング工程、 低濃度 ドレイ ン 2 6 a、 2 6 bを形成する低濃度ド レイン形成ェ 程、 ダミーゲー ト電極 2 5の側面をゲー ト側壁 2 7 で覆うゲー ト 側壁形成工程、 ソース 2 8 a、 ドレイ ン 2 8 bを形成するソース、 ドレイ ン形成工程、 層間膜 2 9 を形成する層間膜形成工程、 ダミ ーゲー ト電極 2 5 を除去するダミーゲー ト電極除去工程、 表面に 凹凸形状を有するフ ローティ ングゲー ト電極 3 0 を形成するフ ローティ ングゲ一ト輋極形成工程、 フローティ ングゲ一 ト電極 3 0上に層間絶縁膜 3 1 を形成する層間絶縁膜形成工程、 層間絶縁 膜 3 1 上に制御電極 3 2 を形成する制御電極形成工程、 ゲー ト部 以外のフローティ ングゲート電極 3 0 、 層間絶縁膜 3 1 、 制御電 極 3 2 を取り除く平坦化工程、 及びプラグ 3 3 を形成するプラグ 形成工程によって構成されている。 Next, the manufacturing process of the nonvolatile memory element 20 will be described. FIGS. 5A to 5C and FIGS. 7A to 7C are cross-sectional structural views for explaining the manufacturing process of the nonvolatile memory element 20. It is. The manufacturing process of the nonvolatile memory element 20 mainly includes a tunnel oxide film forming step of forming a tunnel oxide film 24 on a Si substrate 21 as a base semiconductor substrate, and a tunnel oxide film 24 Dummy gate electrode forming step to form dummy gate electrode 25, dummy gate electrode etching step to etch dummy gate electrode 25, low concentration drain formation to form low concentration drains 26a and 26b In the process, a gate side wall forming step of covering the side surface of the dummy gate electrode 25 with a gate side wall 27, a source forming a source 28a and a drain 28b, a drain forming step, and an interlayer film 29 are formed. Forming the interlayer film, removing the dummy gate electrode 25, removing the dummy gate electrode 25, and forming the floating gate electrode 30 having an uneven surface on the surface. Forming step, an interlayer insulating film forming step of forming an interlayer insulating film 31 on the floating gate electrode 30, a control electrode forming step of forming a control electrode 32 on the interlayer insulating film 31, and a portion other than the gate portion. It is composed of a flattening step for removing the floating gate electrode 30, the interlayer insulating film 31, and the control electrode 32, and a plug forming step for forming the plug 33.
以下、 これらの各工程を順次説明していく。  Hereinafter, each of these steps will be sequentially described.
不揮発性記憶素子 2 0 を製造する場合、 まず、 第 5 A図に示す よう に、 S i 基板 2 1 にシヤロー ト レンチ等によって素子分離層 2 2 を形成し、 さ らに、 通常のイオン注入法を用い、 閾値電圧調 整のための埋め込み層 2 3 を形成する。  In the case of manufacturing the nonvolatile memory element 20, first, as shown in FIG. 5A, an element isolation layer 22 is formed on the Si substrate 21 by a shear wrench or the like, and then a normal ion implantation is performed. The buried layer 23 for adjusting the threshold voltage is formed by using the method.
次に、 この S i 基板 2 1 を 8 0 0 °C程度の温度で 1 5分程度熱 酸化させ、 第 5 B図に示すよう に、 S i 基板 2 1 の表面に 8 n m 程度の トンネル酸化膜 2 4 を形成する （ トンネル酸化膜形成ェ 程）。 さ らに、 通常の L P— C V D等の方法を用いて多結晶 S i 膜を 6 0 0 n m程度堆積させ、 ダミーゲート電極 2 5を形成する (ダミーゲート電極形成工程）。 Next, the Si substrate 21 is thermally oxidized at a temperature of about 800 ° C. for about 15 minutes, and a tunnel oxidation of about 8 nm is formed on the surface of the Si substrate 21 as shown in FIG. 5B. Film 24 is formed (tunnel oxide film formation process). In addition, the polycrystalline Si A film is deposited to a thickness of about 600 nm to form a dummy gate electrode 25 (dummy gate electrode forming step).
次に、 この積層構造に対し、 通常のリソグラフィー技術、 及び R I E技術を用い、 第 5 C図に示すようなダミーゲート電極 2 5 のパターン形成を行う （ダミーゲー ト電極エッチング工程）。 ダ ミ一ゲート電極 2 5 のパターン形成後、 このダミーゲート電極 2 5 をマスクとし、 燐、 砒素等の不純物を、 例えば 5 X 1 0 1 3ノ c m 2程度の濃度でイオン注入し、 低濃度ドレイ ン 2 6 a、 2 6 を形成する （低濃度ドレイン形成工程）。 Next, a pattern of a dummy gate electrode 25 as shown in FIG. 5C is formed on the laminated structure by using a usual lithography technique and an RIE technique (dummy gate electrode etching step). After the dummy gate electrode 25 pattern is formed, impurities such as phosphorus and arsenic are ion-implanted using the dummy gate electrode 25 as a mask, for example, at a concentration of about 5 × 10 13 cm 2 , and a low concentration is formed. Drains 26a and 26 are formed (low concentration drain formation step).
さらに、 通常の C V Dとエッチバック法を用い、 第 6 A図に示 すようなゲー ト側壁 2 7 を形成し （ゲー ト側壁形成工程）、 この ゲート側壁 2 7 をマスクとして、 例えば、 5 X 1 0 1 5 / c m 2程度 の燐、 砒素等の不純物をイオン注入し、 ソース 2 8 a、 ドレイン 2 8 bを形成する (ソース、 ドレイン形成工程）。 Further, a gate sidewall 27 as shown in FIG. 6A is formed using a normal CVD and an etch-back method (gate sidewall formation step), and the gate sidewall 27 is used as a mask, for example, 5X A source 28a and a drain 28b are formed by ion implantation of impurities such as phosphorus and arsenic of about 10 15 / cm 2 (source / drain formation step).
注入した不純物を活性化させるため、 通常の電気加熱炉による 9 0 0 °C程度で 3 0分程度の熱処理、 或いは、 急速熱処理 （R T P ) による 1 0 5 0 °C程度で 1 0秒程度の熱処理を行い、 第 6 B 図に示すように、 S i 酸化膜等の層間膜 2 9を堆積させる （層間 膜形成工程）。  In order to activate the implanted impurities, heat treatment for about 30 minutes at about 900 ° C using a normal electric heating furnace, or about 10 seconds at about 150 ° C by rapid heat treatment (RTP) Heat treatment is performed to deposit an interlayer film 29 such as a Si oxide film as shown in FIG. 6B (interlayer film forming step).
次に、 第 6 C図に示すように、 通常の絶縁膜に対する C M P等 の平坦化技術を用いて、 層間膜 2 9の表面を平坦化させるととも に、 ダミーゲー ト電極 2 5を表面に露出させ、 通常のエッチング 法によってダミーゲート電極 2 5 を除去する （ダミーゲート電極 除去工程）。  Next, as shown in FIG. 6C, the surface of the interlayer film 29 is flattened by using a flattening technique such as CMP for an ordinary insulating film, and the dummy gate electrode 25 is exposed to the surface. Then, the dummy gate electrode 25 is removed by an ordinary etching method (dummy gate electrode removal step).
その後、 第 7 A図に示すように、 気密性の高い C V D装置にお いて酸素を排除した状態で行われる化学的気相成長法等により、 ト ンネル酸化膜 2 4の表面及びゲ一 ト側壁 2 7 の側面に多結晶 S i 等を堆積させ、 第 4 B図に示したような表面に略半円状の凹 凸形状 （半球状ポリ シコ ン ： Hemispherical Grain) を有するフ 口一ティ ングゲー ト.電極 3 0を形成する （フローティ ングゲー ト 形成工程）。 Then, as shown in Fig. 7A, chemical vapor deposition, etc., performed in a highly airtight CVD device with oxygen removed, Polycrystalline Si or the like is deposited on the surface of the tunnel oxide film 24 and the side surface of the gate side wall 27, and the surface as shown in FIG. Silicon: Hinged gate having hemispherical grain. Electrode 30 is formed (floating gate forming step).
ここでのフローティ ングゲ一 ト電極 3 0の形成は、 ゲ一 ト側壁 2 7 の内壁面、 及び層間膜 2 9の上面に沿って行われ、 また、 こ のような半球状ポリ シコ ンの形成は、 例えば、 超高真空対応の C V D装置内でのシラン （ S i H4) を用いた化学的気相成長法等 により、 5 5 0 °C程度の温度で 4 0分程度、 アモルファスシリ コ ンを トンネル酸化膜 2 4の表面に体積させ、 1 0 0 n m程度のァ モルファスシリ コ ン膜を形成し、 さ らに、 1 0分程度のァニール を行い、 粒径 1 0 n m〜 2 0 n m程度の半球状ポリ シコンを成長 させることによって行われる。 The formation of the floating gate electrode 30 here is performed along the inner wall surface of the gate side wall 27 and the upper surface of the interlayer film 29, and the formation of such a hemispherical polysilicon is performed. is, for example, by ultra high vacuum compatible silane in a CVD device (S i H 4) chemical vapor deposition using such, 5 5 0 ° 4 0 minutes to at a temperature of about C, amorphous silicon co Is deposited on the surface of the tunnel oxide film 24 to form an amorphous silicon film of about 100 nm, and is further annealed for about 10 minutes to obtain a particle diameter of 10 nm to 20 nm. This is done by growing a hemispherical polysilicon of about nm.
フローティ ングゲー ト電極 3 0が形成される と、 次に、 4 0 0 °c程度の温度による原子層化学的気相成長法によ り、 フローテ イ ングゲ一 ト電極 3 0の表面 （内壁面） に沿って、 高均一な S i 〇2、 S i 3N4等の信頼性の高い層間絶縁膜 3 1 を 1 5 nm程度堆 積させ （層間絶縁膜形成工程）、 さ らに、 その表面に、 燐等を添 加した多結晶 S i を堆積させ、 制御電極 3 2 を形成する （制御電 極形成工程）。 なお、 ここで層間絶縁膜 3 1 のうち S i 02の形成 は、 原子層化学的気相成長法ではなく、 フローティ ングゲー ト電 極 3 0の半球状ポリ シコ ンを熱酸化させた後、 その表面に原子層 化学的気相成長法等によ り S i 3N4を堆積させ、 'さ らにその S i 3N4を再酸化させることによって構成することとしてもよい。 After the floating gate electrode 30 is formed, the surface (inner wall surface) of the floating gate electrode 30 is then formed by atomic layer chemical vapor deposition at a temperature of about 400 ° C. along the high uniform S i 〇 2, S i 3 N 4 or the like of reliable interlayer insulating film 3 1 to 1 5 nm about sedimentary (interlayer insulating film forming step), and et to, the surface Then, polycrystalline Si to which phosphorus or the like is added is deposited to form a control electrode 32 (control electrode forming step). Here, the interlayer insulating film 3 formed of S i 0 2 of 1, rather than the atomic layer chemical vapor deposition, after thermally oxidizing the hemispherical poly Chico emissions of Floating Nguge preparative electrodes 3 0, It may be configured by depositing Si 3 N 4 on the surface by atomic layer chemical vapor deposition or the like, and re-oxidizing the Si 3 N 4 .
その後、 第 7 B図に示すように、 これらを平坦化し、 ゲー ト部 以外のフローティ ングゲ一ト電極 3 0、 層間絶緣膜 3 1、 制御電 極 3 2 を取り除き （平坦化工程）、 最後に、 第 7 C図に示すよう に、 ソ一ス 2 8 a、 ドレイン 2 8 bの接続部となる多結晶 S i 等 のプラグ 3 3を形成する （プラグ形成工程）。 Thereafter, as shown in FIG. 7B, these are flattened and the gate section is formed. Other than the floating gate electrode 30, interlayer insulating film 31, and control electrode 32 are removed (planarization step). Finally, as shown in FIG. 7C, the source 28 a and the drain 2 are removed. A plug 33 of polycrystalline Si or the like to be a connection portion of 8b is formed (plug forming step).
以上のように表面に半球状ポリ シコンが形成されたフローテ ィ ングゲ一ト電極 3 0及び層間絶縁膜 3 1が、 制御電極 3 2 の底 面及び側面を取り囲むように不揮発性記憶素子 2 0 を構成する ことにより、 第 1 の実施の形態の場合に比べ、 さ らに、 制御電極 3 2 とフローティ ングゲー ト電極 3 0 との静電容量を大きく と ることが可能となる。  As described above, the floating gate electrode 30 and the interlayer insulating film 31 each having a hemispherical polysilicon formed on the surface are used to cover the non-volatile memory element 20 so as to surround the bottom and side surfaces of the control electrode 32. With this configuration, it is possible to further increase the capacitance between the control electrode 32 and the floating gate electrode 30 as compared with the case of the first embodiment.
このように、 本形態では、 表面に半球状ポリシコンを有するフ ローテイ ングゲート電極 3 0が、 制御電極 3 2の底面及び側面を 取り囲むように形成され、 不揮発性記憶素子 2 0 を構成すること としたため、 フローティ ングゲート電極 3 0 の全静電容量に対す る、 制御電極 3 2 とフローティ ングゲート電極 3 0 との静電容量 の比 （カップリ ング比） を大幅に増加させることが可能となり、 不揮発性記憶素子 2 0全体への印加電圧を増加させることなく、 S i 基板 2 1—フローティ ングゲ一 卜電極 3 0 間への印加電圧 を大きくすることができ、 不揮発性記憶素子 2 0全体への印加電 圧の低減を図ることが可能となる。  As described above, in the present embodiment, the floating gate electrode 30 having a hemispherical polysilicon on the surface is formed so as to surround the bottom surface and the side surface of the control electrode 32, thereby constituting the nonvolatile memory element 20. The ratio of the capacitance between the control electrode 32 and the floating gate electrode 30 (coupling ratio) with respect to the total capacitance of the floating gate electrode 30 can be greatly increased. The voltage applied between the Si substrate 21 and the floating gate electrode 30 can be increased without increasing the voltage applied to the entire element 20, and the voltage applied to the entire nonvolatile memory element 20 can be increased. The pressure can be reduced.
また、 これにより、 ドレインに要求される ドレイン耐圧を低減 させることができ、 素子の小型化を図ることが可能となる。  In addition, with this, the drain withstand voltage required for the drain can be reduced, and the size of the element can be reduced.
さ らに、 不揮発性記憶素子 2 0は F G型の構成をとるため、 十 分な蓄積電荷密度、 データ保持時間、 及び書き込み 消去繰り返 し耐性を確保することもできる。  Further, since the nonvolatile memory element 20 has an FG type configuration, it is possible to ensure a sufficient accumulated charge density, data retention time, and write / erase repetition resistance.
一例として、 ゲート長 0 . 1 8 m、 ゲート幅 1 . 0 m、 ゲ —ト高さ 0 . 6 111の 0 . 1 8 m世代の典型的な F G型の不揮 発性記憶素子で比較を行った場合、 従来構成における F G型の不 揮発性記憶素子では、 力ップリ ング比が 0 . 3 6程度となるのに 対し、 本形態における不揮発性記憶素子 2 0では、 カップリ ング 比が 0 . 9程度となり、 2 . 5倍近いカップリ ング比の向上を図 ることができる。 そのため、 例えば、 従来構成において 2 0 Vの 書き込み電圧を必要としていた場合、 本形態では、 8 . 7 V程度 の書き込み電圧での書き込みが可能となる。 As an example, the gate length is 0.18 m, the gate width is 1.0 m, -When comparing the typical FG nonvolatile memory element of 0.18 m generation with a height of 0.6111, the FG nonvolatile memory element in the conventional configuration shows the power ripple. While the coupling ratio is about 0.36, the coupling ratio of the nonvolatile memory element 20 of this embodiment is about 0.9, and it is possible to improve the coupling ratio by about 2.5 times. it can. Therefore, for example, when a writing voltage of 20 V is required in the conventional configuration, writing can be performed with a writing voltage of about 8.7 V in this embodiment.
なお、 本発明は上述の実施形態に拘束されるものではない。 例 えば、 第 1 の実施の形態、 及び第 2の実施の形態では、 原子層化 学的気相成長法を用い、 半球状ポリ シコンを有するフローテイ ン グゲー ト電極表面に高均一な層間絶縁膜を形成することとした が、 ほぼコンフォーマルに超薄膜を形成できる製造方法であれば 原子層化学的気相成長法以外の方法によって、 層間絶縁膜を形成 することとしてもよい.。  Note that the present invention is not limited to the above embodiment. For example, in the first embodiment and the second embodiment, a highly uniform interlayer insulating film is formed on the surface of a floating gate electrode having a hemispherical polysilicon by using atomic layer chemical vapor deposition. However, any method other than atomic layer chemical vapor deposition may be used to form an interlayer insulating film as long as it is a manufacturing method capable of forming an ultrathin film almost conformally.
以上説明したように本発明では、 ベースとなる半導体基板上に トンネル酸化膜を形成し、 トンネル酸化膜上に、 表面に凹凸形状 を有するように形成されたフローティ ングゲー ト電極を形成し、 凹凸形状を有するフ ローティ ングゲ一 ト電極上に高均一に層間 絶縁膜を形成し、 層間絶縁膜上に制御電極を形成することにより F G型の不揮発性記憶素子を構成することとしたため、 十分な蓄 積電荷密度、 データ保持時間、 及び書き込み/消去繰り返し耐性 を確保しつつ、 書き込み電圧の低減、 素子の小型化を図ることが 可能となる。  As described above, according to the present invention, a tunnel oxide film is formed on a semiconductor substrate serving as a base, and a floating gate electrode formed so as to have an uneven shape on the surface is formed on the tunnel oxide film. The FG type non-volatile memory element was constructed by forming an interlayer insulating film on the floating gate electrode with high uniformity and forming a control electrode on the interlayer insulating film. It is possible to reduce the write voltage and reduce the size of the element while ensuring the charge density, the data retention time, and the write / erase repetition resistance.

Claims

請求の範囲 The scope of the claims
1 . 素子電源のオン · オフに関係なくデータの保持を行う不揮発 性記憶素子において、 ベースとなる半導体基板と、 前記半導体基 板上に形成されたトンネル酸化膜と、 前記トンネル酸化膜上に、 表面に凹凸形状を有するように形成されたフローティ ングゲ一 ト電極と、 前記フローティ ングゲート電極上に形成された層間絶 縁膜と、 前記層間絶縁膜上に構成された制御電極と、 を有するこ とを特徴とする不揮発性記憶素子。 1. In a nonvolatile memory element that retains data irrespective of ON / OFF of an element power supply, a semiconductor substrate serving as a base, a tunnel oxide film formed on the semiconductor substrate, and a It has a floating gate electrode formed so as to have an uneven shape on the surface, an interlayer insulating film formed on the floating gate electrode, and a control electrode formed on the interlayer insulating film. A nonvolatile storage element characterized by the above-mentioned.
2 . 前記凹凸形状は、 略半球上の凹凸形状であることを特徴とす る請求の範囲第 1項記載の不揮発性記憶素子。 2. The nonvolatile memory element according to claim 1, wherein the uneven shape is a substantially hemispherical uneven shape.
3 . 前記凹凸形状の粒径は、 1 0 n m〜 2 0 n mであることを特 徴とする請求の範囲第 2項記載の不揮発性記憶素子。  3. The nonvolatile memory element according to claim 2, wherein a particle size of the concave-convex shape is 10 nm to 20 nm.
4 . 前記層間絶縁膜は、 原子層化学的気相成長法を用いて形成さ れる ことを特徴とする請求の範囲第 1項記載の不揮発性記憶素 子。  4. The nonvolatile memory element according to claim 1, wherein the interlayer insulating film is formed by using an atomic layer chemical vapor deposition method.
5 . 前記フローティ ングゲ一 ト電極及び前記層間絶縁膜は、 前記 制御電極の底面及び側面を取り囲むように形成されることを特 徵とする請求の範囲第 1項記載の不揮発性記憶素子。  5. The nonvolatile memory element according to claim 1, wherein the floating gate electrode and the interlayer insulating film are formed so as to surround a bottom surface and a side surface of the control electrode.
6 . フラッシュメモリ用であることを特徴とする請求の範囲第 1 項記載の不揮発性記憶素子。 6. The nonvolatile memory element according to claim 1, wherein the nonvolatile memory element is used for a flash memory.
7 . 素子電源のオン ' オフに関係なくデ一夕の保持を行う不揮発 性記憶素子の製造方法において、 ベ一スとなる半導体基板上にト ンネル酸化膜を形成する トンネル酸化膜形成工程と、 前記トンネ ル酸化膜上に、 表面に凹凸形状を有するフローティ ングゲート電 極を形成するフローティ ングゲート電極形成工程と、 前記フロ一 ティ ングゲ一ト電極上に層間絶縁膜を形成する層間絶縁膜形成 工程と、 前記層間絶縁膜上に制御電極を形成する制御電極形成ェ 程と、 を有する こ とを特徴とする不揮発性記憶素子の製造方法'。7. In a method for manufacturing a nonvolatile memory element that retains the data irrespective of whether the element power is on or off, a tunnel oxide film forming step of forming a tunnel oxide film on a base semiconductor substrate; A floating gate electrode forming step of forming a floating gate electrode having an uneven surface on the tunnel oxide film; A non-volatile memory element, comprising: an inter-layer insulating film forming step of forming an inter-layer insulating film on the tinting gate electrode; and a control electrode forming step of forming a control electrode on the inter-layer insulating film. Manufacturing method.
8 . 前記層間絶縁膜形成工程は、 原子層化学的気相成長法を用い て前記層間絶縁膜の形成を行う こ とを特徴とする請求の範囲第8. The inter-layer insulating film forming step, wherein the inter-layer insulating film is formed using an atomic layer chemical vapor deposition method.
7項記載の不揮発性記憶素子の製造方法。 8. The method for manufacturing a nonvolatile memory element according to claim 7.
9 . 前記 トンネル酸化膜形成工程、 前記フローティ ングゲー ト電 極形成工程、 前記層間絶縁膜形成工程及び前記制御電極形成ェ程 によって形成された前記トンネル酸化膜、 前記フローティ ングゲ ー ト電極、 前記層間絶縁膜及び前記制御電極をエッチングし、 ゲ 9. The tunnel oxide film forming step, the floating gate electrode forming step, the interlayer insulating film forming step and the tunnel oxide film formed by the control electrode forming step, the floating gate electrode, the interlayer insulating film Etching the film and the control electrode;
― ト電極の形成を行うゲー 卜電極エッチング工程をさ ら に有す る こ とを特徴とする請求の範囲第 7項記載の不揮発性記憶素子 の製造方法。 8. The method for manufacturing a nonvolatile memory element according to claim 7, further comprising a gate electrode etching step of forming a gate electrode.
1 0 . 前記 ト ンネル酸化膜形成工程の後、 前記 トンネル酸化膜上 にダミーゲー ト電極を形成するダミーゲー ト電極形成工程と、 前 記ダミーゲー ト電極をエッチングするダミーゲー ト電極エッチ ング工程と、 前記ダミーゲー ト電極の側面をゲー ト側壁で葰ぅゲ ー ト側壁形成工程と、 前記ゲー ト側壁の形成後、 前記ダミーゲー ト電極を除去するダミーゲー ト電極除去工程と、 をさ らに有し、 前 f己フローティ ングゲー ト電極形成工程は、 前記ゲー ト側壁の内 壁面に沿って、 前記フローティ ングゲー ト電極の形成を行い、 前 記層間絶縁膜形成工程は、 前記フローティ ングゲー ト電極の内壁 面に沿って、 前記層間絶縁膜の形成を行う ことを特徴とする請求 の範囲第 7項記載の不揮発性記憶素子の製造方法。  10. After the tunnel oxide film forming step, a dummy gate electrode forming step of forming a dummy gate electrode on the tunnel oxide film; a dummy gate electrode etching step of etching the dummy gate electrode; Forming a gate side wall on the side surface of the gate electrode with a gate side wall, and a dummy gate electrode removing step of removing the dummy gate electrode after the formation of the gate side wall. In the self-floating gate electrode forming step, the floating gate electrode is formed along the inner wall surface of the gate side wall, and the interlayer insulating film forming step is performed along the inner wall surface of the floating gate electrode. The method for manufacturing a nonvolatile memory element according to claim 7, wherein the interlayer insulating film is formed.
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