JP2002217881A - ゲーテッドクロック回復回路 - Google Patents

ゲーテッドクロック回復回路

Info

Publication number
JP2002217881A
JP2002217881A JP2001353920A JP2001353920A JP2002217881A JP 2002217881 A JP2002217881 A JP 2002217881A JP 2001353920 A JP2001353920 A JP 2001353920A JP 2001353920 A JP2001353920 A JP 2001353920A JP 2002217881 A JP2002217881 A JP 2002217881A
Authority
JP
Japan
Prior art keywords
clock
pll
signal
clock recovery
recovery circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001353920A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002217881A5 (https=
Inventor
Alfred Earl Dunlop
アール ダンロップ アルフレッド
Wilhelm C Fischer
カール フィッシャー ウィルヘルム
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agere Systems LLC
Original Assignee
Agere Systems Guardian Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems Guardian Corp filed Critical Agere Systems Guardian Corp
Publication of JP2002217881A publication Critical patent/JP2002217881A/ja
Publication of JP2002217881A5 publication Critical patent/JP2002217881A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0004—Initialisation of the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Transceivers (AREA)
JP2001353920A 2000-11-20 2001-11-20 ゲーテッドクロック回復回路 Pending JP2002217881A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/716977 2000-11-20
US09/716,977 US7010077B1 (en) 2000-11-20 2000-11-20 Gated clock recovery circuit

Publications (2)

Publication Number Publication Date
JP2002217881A true JP2002217881A (ja) 2002-08-02
JP2002217881A5 JP2002217881A5 (https=) 2004-11-25

Family

ID=24880209

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001353920A Pending JP2002217881A (ja) 2000-11-20 2001-11-20 ゲーテッドクロック回復回路

Country Status (5)

Country Link
US (1) US7010077B1 (https=)
EP (1) EP1207623B1 (https=)
JP (1) JP2002217881A (https=)
KR (1) KR100852570B1 (https=)
TW (1) TW532017B (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6920540B2 (en) 2001-10-22 2005-07-19 Rambus Inc. Timing calibration apparatus and method for a memory device signaling system
KR100603180B1 (ko) * 2004-08-06 2006-07-20 학교법인 포항공과대학교 주파수 트래킹 기법을 이용한 씨모오스 버스트 모드 클럭데이터 복원 회로
US7102403B2 (en) * 2005-02-03 2006-09-05 Mediatek Incorporation Clock recovering circuit utilizing a delay locked loop for generating an output clock locked to an analog input signal and related method thereof
US9025713B2 (en) * 2013-10-04 2015-05-05 M31 Technology Corporation Method for portable device processing data based on clock extracted from data from host

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5157355A (en) * 1988-09-13 1992-10-20 Canon Kabushiki Kaisha Phase-locked loop device having stability over wide frequency range
US5072195A (en) * 1990-04-05 1991-12-10 Gazelle Microcircuits, Inc. Phase-locked loop with clamped voltage-controlled oscillator
US5319680A (en) 1991-09-03 1994-06-07 The Whitaker Corporation Phase locked loop synchronization system for use in data communications
US5237290A (en) 1992-05-08 1993-08-17 At&T Bell Laboratories Method and apparatus for clock recovery
US5329251A (en) * 1993-04-28 1994-07-12 National Semiconductor Corporation Multiple biasing phase-lock-loops controlling center frequency of phase-lock-loop clock recovery circuit
FR2713034B1 (fr) * 1993-11-23 1996-01-26 Matra Mhs Circuit de récupération d'horloge à oscillateurs appariés.
KR950011625B1 (ko) 1993-12-14 1995-10-06 재단법인한국전자통신연구소 데이타 및 클럭 복원회로
US5463351A (en) * 1994-09-29 1995-10-31 Motorola, Inc. Nested digital phase lock loop
US5675620A (en) * 1994-10-26 1997-10-07 At&T Global Information Solutions Company High-frequency phase locked loop circuit
JPH08186490A (ja) 1994-11-04 1996-07-16 Fujitsu Ltd 位相同期回路及びデータ再生装置
US5757872A (en) 1994-11-30 1998-05-26 Lucent Technologies Inc. Clock recovery circuit
US5610558A (en) * 1995-11-03 1997-03-11 Motorola, Inc. Controlled tracking of oscillators in a circuit with multiple frequency sensitive elements
US6215835B1 (en) * 1997-08-22 2001-04-10 Lsi Logic Corporation Dual-loop clock and data recovery for serial data communication
US5952892A (en) 1997-09-29 1999-09-14 Lsi Logic Corporation Low-gain, low-jitter voltage controlled oscillator circuit
KR100669403B1 (ko) * 2000-05-04 2007-01-15 삼성전자주식회사 브이에스비/큐에이엠 공용 수신기 및 수신방법

Also Published As

Publication number Publication date
US7010077B1 (en) 2006-03-07
EP1207623B1 (en) 2009-08-12
KR20020039247A (ko) 2002-05-25
KR100852570B1 (ko) 2008-08-18
EP1207623A3 (en) 2004-11-17
TW532017B (en) 2003-05-11
EP1207623A2 (en) 2002-05-22

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