KR100852570B1 - 클록 복원 회로 및 클록 신호 복원 방법 - Google Patents
클록 복원 회로 및 클록 신호 복원 방법 Download PDFInfo
- Publication number
- KR100852570B1 KR100852570B1 KR1020010071737A KR20010071737A KR100852570B1 KR 100852570 B1 KR100852570 B1 KR 100852570B1 KR 1020010071737 A KR1020010071737 A KR 1020010071737A KR 20010071737 A KR20010071737 A KR 20010071737A KR 100852570 B1 KR100852570 B1 KR 100852570B1
- Authority
- KR
- South Korea
- Prior art keywords
- pll
- delete delete
- clock
- signal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0004—Initialisation of the receiver
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Transceivers (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/716,977 US7010077B1 (en) | 2000-11-20 | 2000-11-20 | Gated clock recovery circuit |
| US09/716,977 | 2000-11-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020039247A KR20020039247A (ko) | 2002-05-25 |
| KR100852570B1 true KR100852570B1 (ko) | 2008-08-18 |
Family
ID=24880209
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010071737A Expired - Fee Related KR100852570B1 (ko) | 2000-11-20 | 2001-11-19 | 클록 복원 회로 및 클록 신호 복원 방법 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7010077B1 (https=) |
| EP (1) | EP1207623B1 (https=) |
| JP (1) | JP2002217881A (https=) |
| KR (1) | KR100852570B1 (https=) |
| TW (1) | TW532017B (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6920540B2 (en) | 2001-10-22 | 2005-07-19 | Rambus Inc. | Timing calibration apparatus and method for a memory device signaling system |
| KR100603180B1 (ko) * | 2004-08-06 | 2006-07-20 | 학교법인 포항공과대학교 | 주파수 트래킹 기법을 이용한 씨모오스 버스트 모드 클럭데이터 복원 회로 |
| US7102403B2 (en) * | 2005-02-03 | 2006-09-05 | Mediatek Incorporation | Clock recovering circuit utilizing a delay locked loop for generating an output clock locked to an analog input signal and related method thereof |
| US9025713B2 (en) * | 2013-10-04 | 2015-05-05 | M31 Technology Corporation | Method for portable device processing data based on clock extracted from data from host |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0530775A2 (en) * | 1991-09-03 | 1993-03-10 | Fischer & Porter Company | Phase locked loop synchronization system for use in data communications |
| US5483180A (en) | 1993-12-14 | 1996-01-09 | Chai; Sang-Hoon | Data and clock recovery circuit |
| KR960702233A (ko) * | 1993-04-28 | 1996-03-28 | 존 엠. 클락 3세 | 다중 위상 동기 클럭 복원 회로(a multiple phase-lock-loop clock recovery circuit) |
| KR960012812A (ko) * | 1994-09-29 | 1996-04-20 | 조나단 피. 메이어 | 중첩형 디지탈 위상 동기 루프 회로 및 센터 비트 샘플링 방법 |
| US5952892A (en) | 1997-09-29 | 1999-09-14 | Lsi Logic Corporation | Low-gain, low-jitter voltage controlled oscillator circuit |
| US5982836A (en) | 1994-11-04 | 1999-11-09 | Fujitsu Limited | Phase synchronizer and data reproducing apparatus |
| KR20010100620A (ko) * | 2000-05-04 | 2001-11-14 | 윤종용 | 브이에스비/큐에이엠 공용 수신기 및 수신방법 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5157355A (en) * | 1988-09-13 | 1992-10-20 | Canon Kabushiki Kaisha | Phase-locked loop device having stability over wide frequency range |
| US5072195A (en) * | 1990-04-05 | 1991-12-10 | Gazelle Microcircuits, Inc. | Phase-locked loop with clamped voltage-controlled oscillator |
| US5237290A (en) | 1992-05-08 | 1993-08-17 | At&T Bell Laboratories | Method and apparatus for clock recovery |
| FR2713034B1 (fr) * | 1993-11-23 | 1996-01-26 | Matra Mhs | Circuit de récupération d'horloge à oscillateurs appariés. |
| US5675620A (en) * | 1994-10-26 | 1997-10-07 | At&T Global Information Solutions Company | High-frequency phase locked loop circuit |
| US5757872A (en) | 1994-11-30 | 1998-05-26 | Lucent Technologies Inc. | Clock recovery circuit |
| US5610558A (en) * | 1995-11-03 | 1997-03-11 | Motorola, Inc. | Controlled tracking of oscillators in a circuit with multiple frequency sensitive elements |
| US6215835B1 (en) * | 1997-08-22 | 2001-04-10 | Lsi Logic Corporation | Dual-loop clock and data recovery for serial data communication |
-
2000
- 2000-11-20 US US09/716,977 patent/US7010077B1/en not_active Expired - Fee Related
-
2001
- 2001-10-18 TW TW090125775A patent/TW532017B/zh not_active IP Right Cessation
- 2001-11-19 KR KR1020010071737A patent/KR100852570B1/ko not_active Expired - Fee Related
- 2001-11-20 EP EP01309756A patent/EP1207623B1/en not_active Expired - Lifetime
- 2001-11-20 JP JP2001353920A patent/JP2002217881A/ja active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0530775A2 (en) * | 1991-09-03 | 1993-03-10 | Fischer & Porter Company | Phase locked loop synchronization system for use in data communications |
| KR960702233A (ko) * | 1993-04-28 | 1996-03-28 | 존 엠. 클락 3세 | 다중 위상 동기 클럭 복원 회로(a multiple phase-lock-loop clock recovery circuit) |
| US5483180A (en) | 1993-12-14 | 1996-01-09 | Chai; Sang-Hoon | Data and clock recovery circuit |
| KR960012812A (ko) * | 1994-09-29 | 1996-04-20 | 조나단 피. 메이어 | 중첩형 디지탈 위상 동기 루프 회로 및 센터 비트 샘플링 방법 |
| US5982836A (en) | 1994-11-04 | 1999-11-09 | Fujitsu Limited | Phase synchronizer and data reproducing apparatus |
| US5952892A (en) | 1997-09-29 | 1999-09-14 | Lsi Logic Corporation | Low-gain, low-jitter voltage controlled oscillator circuit |
| KR20010100620A (ko) * | 2000-05-04 | 2001-11-14 | 윤종용 | 브이에스비/큐에이엠 공용 수신기 및 수신방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| US7010077B1 (en) | 2006-03-07 |
| EP1207623B1 (en) | 2009-08-12 |
| KR20020039247A (ko) | 2002-05-25 |
| JP2002217881A (ja) | 2002-08-02 |
| EP1207623A3 (en) | 2004-11-17 |
| TW532017B (en) | 2003-05-11 |
| EP1207623A2 (en) | 2002-05-22 |
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| JP2002217881A5 (https=) |
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