KR100852570B1 - 클록 복원 회로 및 클록 신호 복원 방법 - Google Patents

클록 복원 회로 및 클록 신호 복원 방법 Download PDF

Info

Publication number
KR100852570B1
KR100852570B1 KR1020010071737A KR20010071737A KR100852570B1 KR 100852570 B1 KR100852570 B1 KR 100852570B1 KR 1020010071737 A KR1020010071737 A KR 1020010071737A KR 20010071737 A KR20010071737 A KR 20010071737A KR 100852570 B1 KR100852570 B1 KR 100852570B1
Authority
KR
South Korea
Prior art keywords
pll
delete delete
clock
signal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020010071737A
Other languages
English (en)
Korean (ko)
Other versions
KR20020039247A (ko
Inventor
던롭알프레드얼
피셔윌헬름칼
Original Assignee
에이저 시스템즈 가디언 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에이저 시스템즈 가디언 코포레이션 filed Critical 에이저 시스템즈 가디언 코포레이션
Publication of KR20020039247A publication Critical patent/KR20020039247A/ko
Application granted granted Critical
Publication of KR100852570B1 publication Critical patent/KR100852570B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/0805Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/14Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0004Initialisation of the receiver
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Transceivers (AREA)
KR1020010071737A 2000-11-20 2001-11-19 클록 복원 회로 및 클록 신호 복원 방법 Expired - Fee Related KR100852570B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/716,977 US7010077B1 (en) 2000-11-20 2000-11-20 Gated clock recovery circuit
US09/716,977 2000-11-20

Publications (2)

Publication Number Publication Date
KR20020039247A KR20020039247A (ko) 2002-05-25
KR100852570B1 true KR100852570B1 (ko) 2008-08-18

Family

ID=24880209

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010071737A Expired - Fee Related KR100852570B1 (ko) 2000-11-20 2001-11-19 클록 복원 회로 및 클록 신호 복원 방법

Country Status (5)

Country Link
US (1) US7010077B1 (https=)
EP (1) EP1207623B1 (https=)
JP (1) JP2002217881A (https=)
KR (1) KR100852570B1 (https=)
TW (1) TW532017B (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6920540B2 (en) 2001-10-22 2005-07-19 Rambus Inc. Timing calibration apparatus and method for a memory device signaling system
KR100603180B1 (ko) * 2004-08-06 2006-07-20 학교법인 포항공과대학교 주파수 트래킹 기법을 이용한 씨모오스 버스트 모드 클럭데이터 복원 회로
US7102403B2 (en) * 2005-02-03 2006-09-05 Mediatek Incorporation Clock recovering circuit utilizing a delay locked loop for generating an output clock locked to an analog input signal and related method thereof
US9025713B2 (en) * 2013-10-04 2015-05-05 M31 Technology Corporation Method for portable device processing data based on clock extracted from data from host

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0530775A2 (en) * 1991-09-03 1993-03-10 Fischer & Porter Company Phase locked loop synchronization system for use in data communications
US5483180A (en) 1993-12-14 1996-01-09 Chai; Sang-Hoon Data and clock recovery circuit
KR960702233A (ko) * 1993-04-28 1996-03-28 존 엠. 클락 3세 다중 위상 동기 클럭 복원 회로(a multiple phase-lock-loop clock recovery circuit)
KR960012812A (ko) * 1994-09-29 1996-04-20 조나단 피. 메이어 중첩형 디지탈 위상 동기 루프 회로 및 센터 비트 샘플링 방법
US5952892A (en) 1997-09-29 1999-09-14 Lsi Logic Corporation Low-gain, low-jitter voltage controlled oscillator circuit
US5982836A (en) 1994-11-04 1999-11-09 Fujitsu Limited Phase synchronizer and data reproducing apparatus
KR20010100620A (ko) * 2000-05-04 2001-11-14 윤종용 브이에스비/큐에이엠 공용 수신기 및 수신방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5157355A (en) * 1988-09-13 1992-10-20 Canon Kabushiki Kaisha Phase-locked loop device having stability over wide frequency range
US5072195A (en) * 1990-04-05 1991-12-10 Gazelle Microcircuits, Inc. Phase-locked loop with clamped voltage-controlled oscillator
US5237290A (en) 1992-05-08 1993-08-17 At&T Bell Laboratories Method and apparatus for clock recovery
FR2713034B1 (fr) * 1993-11-23 1996-01-26 Matra Mhs Circuit de récupération d'horloge à oscillateurs appariés.
US5675620A (en) * 1994-10-26 1997-10-07 At&T Global Information Solutions Company High-frequency phase locked loop circuit
US5757872A (en) 1994-11-30 1998-05-26 Lucent Technologies Inc. Clock recovery circuit
US5610558A (en) * 1995-11-03 1997-03-11 Motorola, Inc. Controlled tracking of oscillators in a circuit with multiple frequency sensitive elements
US6215835B1 (en) * 1997-08-22 2001-04-10 Lsi Logic Corporation Dual-loop clock and data recovery for serial data communication

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0530775A2 (en) * 1991-09-03 1993-03-10 Fischer & Porter Company Phase locked loop synchronization system for use in data communications
KR960702233A (ko) * 1993-04-28 1996-03-28 존 엠. 클락 3세 다중 위상 동기 클럭 복원 회로(a multiple phase-lock-loop clock recovery circuit)
US5483180A (en) 1993-12-14 1996-01-09 Chai; Sang-Hoon Data and clock recovery circuit
KR960012812A (ko) * 1994-09-29 1996-04-20 조나단 피. 메이어 중첩형 디지탈 위상 동기 루프 회로 및 센터 비트 샘플링 방법
US5982836A (en) 1994-11-04 1999-11-09 Fujitsu Limited Phase synchronizer and data reproducing apparatus
US5952892A (en) 1997-09-29 1999-09-14 Lsi Logic Corporation Low-gain, low-jitter voltage controlled oscillator circuit
KR20010100620A (ko) * 2000-05-04 2001-11-14 윤종용 브이에스비/큐에이엠 공용 수신기 및 수신방법

Also Published As

Publication number Publication date
US7010077B1 (en) 2006-03-07
EP1207623B1 (en) 2009-08-12
KR20020039247A (ko) 2002-05-25
JP2002217881A (ja) 2002-08-02
EP1207623A3 (en) 2004-11-17
TW532017B (en) 2003-05-11
EP1207623A2 (en) 2002-05-22

Similar Documents

Publication Publication Date Title
US6215835B1 (en) Dual-loop clock and data recovery for serial data communication
US5059925A (en) Method and apparatus for transparently switching clock sources
US5301196A (en) Half-speed clock recovery and demultiplexer circuit
US6359945B1 (en) Phase locked loop and method that provide fail-over redundant clocking
US5373254A (en) Method and apparatus for controlling phase of a system clock signal for switching the system clock signal
US5237290A (en) Method and apparatus for clock recovery
US7027544B2 (en) Data clocked recovery circuit
US5734301A (en) Dual phase-locked loop clock synthesizer
JPH08237240A (ja) クロックパルスの発生方法、クロックパルス発生装置及びクロック再生回路
US7170964B2 (en) Transition insensitive timing recovery method and apparatus
US7734000B2 (en) Clock and data recovery circuits
JPH08510366A (ja) 多重位相ロックループのクロック回復回路
KR100852570B1 (ko) 클록 복원 회로 및 클록 신호 복원 방법
KR20080044977A (ko) 위상 동기 루프 및 위상 동기 루프의 동작 방법
CN100450230C (zh) 一种射频远端模块中时钟恢复方法和装置
EP1006660A2 (en) Clock reproduction and identification apparatus
US6771729B1 (en) Clock recovery circuit and transmitter-receiver therewith
US6218907B1 (en) Frequency comparator and PLL circuit using the same
US20060193417A1 (en) Systems and methods for switching between redundant clock signals
US6058151A (en) Digital phase shift phase-locked loop for data and clock recovery
KR100272524B1 (ko) 전하펌프위상동기루프
EP1701443B1 (en) Voltage controlled oscillator with additional phase control
US20050018692A1 (en) Integrated circuit with on-chip clock frequency matching to upstream head end equipment
KR19990087197A (ko) 디지털 수신기를 동기화하는 장치
JP2002217881A5 (https=)

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
AMND Amendment
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

D13-X000 Search requested

St.27 status event code: A-1-2-D10-D13-srh-X000

D14-X000 Search report completed

St.27 status event code: A-1-2-D10-D14-srh-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

AMND Amendment
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E601 Decision to refuse application
PE0601 Decision on rejection of patent

St.27 status event code: N-2-6-B10-B15-exm-PE0601

J201 Request for trial against refusal decision
PJ0201 Trial against decision of rejection

St.27 status event code: A-3-3-V10-V11-apl-PJ0201

AMND Amendment
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PB0901 Examination by re-examination before a trial

St.27 status event code: A-6-3-E10-E12-rex-PB0901

B701 Decision to grant
PB0701 Decision of registration after re-examination before a trial

St.27 status event code: A-3-4-F10-F13-rex-PB0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20120727

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20130723

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

FPAY Annual fee payment

Payment date: 20140722

Year of fee payment: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20150809

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20150809