JP2002217354A5 - - Google Patents
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- Publication number
- JP2002217354A5 JP2002217354A5 JP2001006917A JP2001006917A JP2002217354A5 JP 2002217354 A5 JP2002217354 A5 JP 2002217354A5 JP 2001006917 A JP2001006917 A JP 2001006917A JP 2001006917 A JP2001006917 A JP 2001006917A JP 2002217354 A5 JP2002217354 A5 JP 2002217354A5
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- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001006917A JP2002217354A (ja) | 2001-01-15 | 2001-01-15 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001006917A JP2002217354A (ja) | 2001-01-15 | 2001-01-15 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002217354A JP2002217354A (ja) | 2002-08-02 |
| JP2002217354A5 true JP2002217354A5 (https=) | 2007-03-08 |
Family
ID=18874741
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001006917A Pending JP2002217354A (ja) | 2001-01-15 | 2001-01-15 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002217354A (https=) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7064426B2 (en) | 2002-09-17 | 2006-06-20 | Chippac, Inc. | Semiconductor multi-package module having wire bond interconnect between stacked packages |
| KR101166575B1 (ko) * | 2002-09-17 | 2012-07-18 | 스태츠 칩팩, 엘티디. | 적층형 패키지들 간 도선연결에 의한 상호연결을 이용한반도체 멀티-패키지 모듈 및 그 제작 방법 |
| JP4615189B2 (ja) | 2003-01-29 | 2011-01-19 | シャープ株式会社 | 半導体装置およびインターポーザチップ |
| JP2006186053A (ja) * | 2004-12-27 | 2006-07-13 | Shinko Electric Ind Co Ltd | 積層型半導体装置 |
| JP4707548B2 (ja) * | 2005-12-08 | 2011-06-22 | 富士通セミコンダクター株式会社 | 半導体装置、及び半導体装置の製造方法 |
| JP5092284B2 (ja) * | 2006-05-31 | 2012-12-05 | 凸版印刷株式会社 | Ｉｃチップ貼り合わせ用ｔｏｃ用構造体 |
| KR100800149B1 (ko) * | 2006-06-30 | 2008-02-01 | 주식회사 하이닉스반도체 | 스택 패키지 |
| JP2008091396A (ja) * | 2006-09-29 | 2008-04-17 | Sanyo Electric Co Ltd | 半導体モジュールおよび半導体装置 |
| JP2007214582A (ja) * | 2007-03-29 | 2007-08-23 | Sharp Corp | 半導体装置およびインターポーザチップ |
| JP2007180587A (ja) * | 2007-03-29 | 2007-07-12 | Sharp Corp | 半導体装置 |
| JP5166903B2 (ja) * | 2008-02-08 | 2013-03-21 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP4536808B2 (ja) * | 2008-09-08 | 2010-09-01 | シャープ株式会社 | 半導体装置およびインターポーザチップ |
| JP5099714B2 (ja) * | 2009-04-27 | 2012-12-19 | ルネサスエレクトロニクス株式会社 | マルチチップモジュール |
| KR20110137926A (ko) * | 2010-06-18 | 2011-12-26 | (주)에프씨아이 | 적층 다중 칩 패키지 구조 |
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2001
- 2001-01-15 JP JP2001006917A patent/JP2002217354A/ja active Pending