JP2002190572A - 半導体装置、レイアウトデータ設計装置、及び記録媒体 - Google Patents

半導体装置、レイアウトデータ設計装置、及び記録媒体

Info

Publication number
JP2002190572A
JP2002190572A JP2000387264A JP2000387264A JP2002190572A JP 2002190572 A JP2002190572 A JP 2002190572A JP 2000387264 A JP2000387264 A JP 2000387264A JP 2000387264 A JP2000387264 A JP 2000387264A JP 2002190572 A JP2002190572 A JP 2002190572A
Authority
JP
Japan
Prior art keywords
power supply
cell
level converter
blocks
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000387264A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002190572A5 (enExample
Inventor
Shinji Fukazawa
真治 深澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP2000387264A priority Critical patent/JP2002190572A/ja
Priority to US09/877,033 priority patent/US6941534B2/en
Publication of JP2002190572A publication Critical patent/JP2002190572A/ja
Publication of JP2002190572A5 publication Critical patent/JP2002190572A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2000387264A 2000-12-20 2000-12-20 半導体装置、レイアウトデータ設計装置、及び記録媒体 Pending JP2002190572A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000387264A JP2002190572A (ja) 2000-12-20 2000-12-20 半導体装置、レイアウトデータ設計装置、及び記録媒体
US09/877,033 US6941534B2 (en) 2000-12-20 2001-06-11 Semiconductor device and layout data generation apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000387264A JP2002190572A (ja) 2000-12-20 2000-12-20 半導体装置、レイアウトデータ設計装置、及び記録媒体

Publications (2)

Publication Number Publication Date
JP2002190572A true JP2002190572A (ja) 2002-07-05
JP2002190572A5 JP2002190572A5 (enExample) 2005-03-17

Family

ID=18854231

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000387264A Pending JP2002190572A (ja) 2000-12-20 2000-12-20 半導体装置、レイアウトデータ設計装置、及び記録媒体

Country Status (2)

Country Link
US (1) US6941534B2 (enExample)
JP (1) JP2002190572A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004335843A (ja) * 2003-05-09 2004-11-25 Nec Electronics Corp 半導体回路装置の設計方法、設計された半導体回路装置、設計システム、及び記録媒体
US6849906B2 (en) 2002-08-14 2005-02-01 Kabushiki Kaisha Toshiba Standard-cell type semiconductor integrated circuit device with a mixed arrangement of standard cells differing in height
US11728795B2 (en) 2021-02-22 2023-08-15 Samsung Electronics Co., Ltd. Voltage level shifter cell and integrated circuit including the same

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100486274B1 (ko) * 2002-10-24 2005-04-29 삼성전자주식회사 집적회로 장치 설계용 네트리스트 작성 방법
US7111266B2 (en) * 2003-11-24 2006-09-19 International Business Machines Corp. Multiple voltage integrated circuit and design method therefor
US7089510B2 (en) * 2003-11-24 2006-08-08 International Business Machines Corp. Method and program product of level converter optimization
JP2007164427A (ja) * 2005-12-13 2007-06-28 Matsushita Electric Ind Co Ltd 多電源集積回路のレイアウト設計方法
JP5057350B2 (ja) * 2008-02-27 2012-10-24 パナソニック株式会社 半導体集積回路、およびこれを備えた各種装置
US11764201B2 (en) 2020-04-02 2023-09-19 Samsung Electronics Co., Ltd. Integrated circuit including standard cells

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3335700B2 (ja) * 1993-03-30 2002-10-21 富士通株式会社 レベルコンバータ及び半導体集積回路
EP0862127B1 (en) * 1994-01-19 2002-09-04 Matsushita Electric Industrial Co., Ltd. Method of designing semiconductor integrated circuit
JP3705880B2 (ja) * 1996-11-28 2005-10-12 富士通株式会社 レベルコンバータ及び半導体装置
JPH10163843A (ja) * 1996-12-04 1998-06-19 Toshiba Corp 組み合わせ論理回路及びその設計方法
JPH11328238A (ja) * 1998-05-12 1999-11-30 Toshiba Corp 多電源集積回路の評価装置及び多電源集積回路の評価方法
US6232818B1 (en) * 1998-05-20 2001-05-15 Xilinx, Inc. Voltage translator
IT1304060B1 (it) * 1998-12-29 2001-03-07 St Microelectronics Srl Variatore di livello per circuiteria a tensione d'alimentazionemultipla
JP2000305961A (ja) * 1999-04-16 2000-11-02 Matsushita Electric Ind Co Ltd セルライブラリデータベースおよび設計支援装置
JP3270427B2 (ja) * 1999-07-27 2002-04-02 エヌイーシーマイクロシステム株式会社 半導体装置の設計方法
JP2002015018A (ja) * 2000-06-30 2002-01-18 Fujitsu Ltd 半導体装置の設計方法及び記録媒体
JP3433731B2 (ja) * 2000-11-10 2003-08-04 セイコーエプソン株式会社 Ｉ／ｏセル配置方法及び半導体装置
US6792582B1 (en) * 2000-11-15 2004-09-14 International Business Machines Corporation Concurrent logical and physical construction of voltage islands for mixed supply voltage designs
DE10100168A1 (de) * 2001-01-04 2002-07-18 Infineon Technologies Ag Entwurf von Schaltungen mit Abschnitten unterschiedlicher Versorgungsspannung

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6849906B2 (en) 2002-08-14 2005-02-01 Kabushiki Kaisha Toshiba Standard-cell type semiconductor integrated circuit device with a mixed arrangement of standard cells differing in height
JP2004335843A (ja) * 2003-05-09 2004-11-25 Nec Electronics Corp 半導体回路装置の設計方法、設計された半導体回路装置、設計システム、及び記録媒体
US11728795B2 (en) 2021-02-22 2023-08-15 Samsung Electronics Co., Ltd. Voltage level shifter cell and integrated circuit including the same

Also Published As

Publication number Publication date
US6941534B2 (en) 2005-09-06
US20020074571A1 (en) 2002-06-20

Similar Documents

Publication Publication Date Title
US5883814A (en) System-on-chip layout compilation
CN101187957B (zh) 设计集成电路的公共时钟域中的多个锁存器的布图的系统和方法
US7016794B2 (en) Floor plan development electromigration and voltage drop analysis tool
US6083271A (en) Method and apparatus for specifying multiple power domains in electronic circuit designs
EP0844576A2 (en) Computer system and method for performing design automation in a distributed computing environment
US20250209249A1 (en) Systems and methods for integrated circuit layout
US8397190B2 (en) Method for manipulating and repartitioning a hierarchical integrated circuit design
US8037432B2 (en) Method and apparatus for mapping design memories to integrated circuit layout
JPH0731695B2 (ja) 半導体集積回路装置のマスクパターンのコンパクション処理方法
US20050034095A1 (en) Method for providing a cell-based ASIC device with multiple power supply voltages
JP2002190572A (ja) 半導体装置、レイアウトデータ設計装置、及び記録媒体
JP2002157291A (ja) 半導体集積回路装置の設計方法
JP2002015018A (ja) 半導体装置の設計方法及び記録媒体
JP3629250B2 (ja) 半導体集積回路のレイアウト方法及び半導体集積回路
US7543249B2 (en) Embedded switchable power ring
JPH113366A (ja) 遅延時間算出方法、遅延時間算出装置、テーブル作成方法及び記憶媒体
US7260804B1 (en) Method for circuit block routing based on switching activity
JP3071617B2 (ja) 半導体設計方法及び半導体設計装置
JP3476688B2 (ja) ネットリスト生成方法及びネットリスト生成装置
JP3851771B2 (ja) 電圧降下解析システム
JPH06260557A (ja) 半導体設計支援装置
US20250068811A1 (en) Systems and Methods for Implementing Design of Semiconductor Packages
JP3080077B2 (ja) 半導体集積回路のレイアウト設計方法及び設計システム
US7404166B2 (en) Method and system for mapping netlist of integrated circuit to design
JPH09321142A (ja) 半導体集積回路装置の設計装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040420

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040420

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050124

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20050830

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070717

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20070719

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070918

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20071127