JP2002151820A - Printed wiring board and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a pat-on-via structure using a simple process. SOLUTION: A conductive project 4 is formed on the surfaces of an insulating substrate 1, and a conductive project 6 is also formed on a copper foil. The conductive projects 4 and 6 are made to pass through an insulating resin layer 7, to interconnect each other via heterogeneous metal layers 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board and a method for manufacturing a printed wiring board, and more particularly, to a printed wiring board suitable for application to a build-up multilayer printed wiring board.

[0002]

2. Description of the Related Art With the advent of the multimedia era, portable electronic devices such as mobile phones, Internet portable terminals, and portable personal computers have become widespread, and printed wiring has been promoted in order to promote the spread of these portable electronic devices. There is an increasing demand for boards to be smaller, lighter, thinner, denser, and less costly.

[0003] In response to this request for printed wiring boards,
Build-up multilayer printed wiring boards are receiving attention. In a build-up multilayer printed wiring board, a method using a laser and a method using photo-etching are known as methods for connecting layers.

In the method using a laser, resin sheets with copper foil are arranged above and below an insulating substrate on which an inner wiring layer is formed, and these are mounted on a press jig and heated and pressed to be integrally laminated. You. Then, after the outermost copper foil at the via-hole forming position is removed by selective etching, the via-hole forming position is irradiated with a laser beam, so that the resin sheet is perforated. Thereafter, by forming a metal plating layer on the inner wall surface of the hole, interlayer connection of the wiring layer is performed.

In the method using photoetching, a photosensitive resin is applied to the upper and lower surfaces of an insulating substrate on which an inner wiring layer is formed, and the photosensitive resin at a via hole forming position is selectively exposed and developed to form a via hole. The photosensitive resin at the formation position is removed, and a non-through via hole for interlayer connection is formed. Thereafter, chemical plating is performed on the entire inner wall surface of the via hole, and then a metal plating layer is formed by electroplating, whereby interlayer connection of the wiring layer is performed.

On the other hand, CSP mounting has become widespread in response to demands for downsizing, lightening, thinning, and high density of electronic devices. In the CSP mounting, as the degree of integration increases, the number of electrode pins per unit area increases, and the number of solder bumps also increases accordingly. For this reason, in order to support CSP mounting, it is indispensable to miniaturize the LSI land pattern portion of the printed wiring board and to adopt a pad-on-via structure.

[0007]

However, in a conventional printed wiring board, laser processing or photoetching is used to perform interlayer connection. here,
In the method using laser processing, the man-hour for laser drilling increases as the number of holes increases. On the other hand, in the method using photoetching, it is necessary to perform chemical plating on the entire inner wall surface of the via hole, and thus there is a limit to miniaturization. Also, realizing a put-on-via structure by laser processing or photo-etching complicates the process and causes an increase in cost.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a printed wiring board and a method for manufacturing a printed wiring board which can realize a pad-on-via structure with a simple process and can make a via hole finer.

[0009]

According to the first aspect of the present invention, there is provided a first wiring layer having copper projections formed thereon, and an insulating layer having the copper projections embedded therein. A second wiring layer formed via the insulating layer; and a dissimilar metal layer electrically connecting the first and second wiring layers via the copper protrusion. It is characterized by.

Here, the dissimilar metal layer can act so as to improve the adhesiveness of the copper projection when performing interlayer connection.

Thus, it is possible to electrically connect the first wiring layer and the second wiring layer only by penetrating the interlayer insulating layer with the copper protrusion formed on the first wiring layer. At the same time, embedding in the via hole is not required, and the put-on via structure can be realized with a simple process.

Furthermore, even when the copper projection is miniaturized, the strength of the copper projection can be maintained, so that the copper projection can reliably penetrate the interlayer insulating layer, and the copper The connection of the protrusions can be stably performed by the dissimilar metal layer, and the interlayer connection region can be miniaturized without impairing the reliability of the interlayer connection.

According to the second aspect of the present invention, the first
Forming a copper protrusion on the wiring layer, laminating an insulating layer penetrating the copper protrusion on the first wiring layer, forming a dissimilar metal on the second wiring layer, Laminating the second wiring layer on the insulating layer such that the position of the copper projection corresponds to the formation region of the dissimilar metal.

Thus, when the copper protrusion formed on the first wiring layer is penetrated into the interlayer insulating layer to electrically connect the first wiring layer and the second wiring layer, the copper protrusion is formed. Adhesiveness can be ensured, and a pad-on-via structure can be realized by a simple process while miniaturizing an interlayer connection region.

According to the third aspect of the present invention, the first
Forming a copper protrusion on the wiring layer, forming a dissimilar metal layer on the copper protrusion, laminating an insulating layer penetrating the copper protrusion on the first wiring layer, Laminating two wiring layers on the insulating layer.

Thus, it is possible to easily form a dissimilar metal layer corresponding to the copper protrusion formed on the first wiring layer, and only by penetrating the copper protrusion into the interlayer insulating layer,
It is possible to electrically connect the first wiring layer and the second wiring layer.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer printed wiring board according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing the structure of a printed wiring board according to the first embodiment of the present invention. In FIG. 1, conductor patterns 2 and 3 are formed on both surfaces of an insulating substrate 1, and a copper foil 8 is formed on the conductor pattern 3 via an insulating resin layer 7. Here, the conductor protrusions 4 and 6 are embedded in the insulating resin layer 7, and the conductor protrusions 4 are
The conductor protrusions 6 are connected to the copper foil 8, and the conductor protrusions 4 and 6 are connected to each other via the dissimilar metal layer 5.

Thus, by patterning the copper foil 8 on the conductor protrusions 4 and 6, an outer wiring layer can be formed, and a pad-on-via structure can be realized by a simple process.

Further, a dissimilar metal layer 5 is provided between the conductor protrusions 4 and 6.
, The adhesiveness between the conductor protrusions 4 and 6 can be improved. Even when the conductor protrusions 4 and 6 are made of copper or the like and the adhesion between the conductor protrusions 4 and 6 is poor, the electrical Connection can be stably performed.

Here, as the dissimilar metal layer 5, for example,
A conductive metal such as gold, silver, solder, tin, and lead can be used. Also, for example, conductive powders of gold, silver, solder, etc., alloy powders of these metals, or mixed powders of these metals, polycarbonate resin, polysulfone resin, polyester resin, phenoxy resin, phenol resin, polyimide resin, etc. A conductive composition mixed with a binder component may be used. The dissimilar metal layer 5 can be formed by, for example, a printing method, a dispenser, dry plating, or wet plating.

The conductor protrusions 4 and 6 may be formed by, for example, a method of etching out a copper foil provided on an insulator by panel plating, a method of etching out a copper foil having a thickness of about 70 to 105 μm, An opening corresponding to the conductor protrusions 4 and 6 may be formed in the plating resist applied thereon, and a plating layer may be deposited in the opening to form the opening.

The insulating resin layer 7 can be made of, for example, an epoxy resin, a polyimide resin, or a modified resin thereof alone or in combination. In addition, an inorganic or organic filler may be contained in the resin, or a prepreg obtained by impregnating a resin into a glass cloth may be used. Further, a resin formed into a film shape may be laminated, or a liquid resin may be coated.

Hereinafter, a method for manufacturing a printed wiring board according to an embodiment of the present invention will be described.

FIGS. 2 and 3 are cross-sectional views showing the steps of manufacturing a printed wiring board according to the second embodiment of the present invention.

First, in FIG. 2A, a plating resist 12 is applied on the processed surface of the copper foil 11. Then, by exposing and developing using the pattern corresponding to the copper protrusion 14 as a mask, the plating resist 12 in the portion corresponding to the copper protrusion 14 is selectively removed, and the opening 13 is formed.

Next, in FIG. 2B, the copper foil 11 on which the plating resist 12 is formed is subjected to electrolytic copper plating, and the copper
A copper projection 14 is formed on the upper surface.

Next, in FIG. 2C, the plating resist 12 is peeled from the copper foil 11 on which the copper protrusions 14 are formed by immersing the copper foil 11 on which the copper protrusions 14 are formed in a stripping solution. Then, the copper foil 11 on which the copper protrusions 14 are formed is laminated with the prepreg 15 under heat and pressure, whereby the prepreg 15 is penetrated by the copper protrusions 14.

On the other hand, in FIG. 2D, the inner wiring layer 1 is formed on both surfaces of the insulating substrate 16 in which the through holes 19 are formed.
7, 17 'are formed. Then, the inner wiring layers 17, 17
'Ag pastes 18 and 18' are applied to the region where interlayer connection is performed and dried.

After that, the copper foils 11, 11 'through which the prepregs 15, 15' have been penetrated by the copper projections 14, 14 'are
The g pastes 18 and 18 'are arranged on both surfaces of the insulating substrate 16 to which the pastes 18 and 18' are applied. Here, positioning is performed so that the copper projections 14 and 14 'face the positions of the Ag pastes 18 and 18'.

Next, referring to FIG.
The copper foils 11, 11 'through which the prepregs 15, 15' have penetrated by 14 'and the insulating substrate 16 to which the Ag pastes 18, 18' have been applied are laminated under heat and pressure. Thereby, the inner wiring layers 17, 17 'and the copper foils 11, 11' are insulated from each other by the prepregs 15, 15 ',
4 and 14 ′ are in close contact with the inner wiring layers 17 and 17 ′ via the Ag pastes 18 and 18 ′, and the inner wiring layers 17 and 17 ′ are electrically connected to the copper foils 11 and 11 ′.

Next, in FIG. 3 (f), the copper foils 11, 1
By performing patterning 1 ′, outer wiring layers 20 and 20 ′ having a pad-on-via structure are formed.

As described above, by performing interlayer connection using different kinds of metals, it is possible to form projections penetrating the prepregs 15 and 15 ′ with a hard metal such as copper.
Even when the protrusions are miniaturized, the prepreg 1
5, 15 'can be surely penetrated, and the adhesion of the protrusions penetrating the prepregs 15, 15' can be improved, and a fine pad-on-via structure can be stably formed in a simple process. It can be manufactured.

FIGS. 4 and 5 are cross-sectional views showing steps of manufacturing a printed wiring board according to the third embodiment of the present invention.

First, in FIG. 4A, a plating resist 22 is applied on the processed surface of the copper foil 21. Then, by exposing and developing using the pattern corresponding to the copper protrusion 24 as a mask, the plating resist 22 in the portion corresponding to the copper protrusion 24 is selectively removed, and the opening 23 is formed.

Next, in FIG. 4B, the copper foil 21 on which the plating resist 22 is formed is subjected to electrolytic copper plating, and the copper
A copper projection 24 is formed thereon. After that, gold plating layer 25 is formed on copper protrusions 24 by performing electrogold plating on copper foil 21 on which copper protrusions 24 are formed.

Next, in FIG. 4C, the plating resist 2 is peeled off from the copper foil 21 on which the gold plating layer 25 is formed on the copper projections 24. Then, the copper foil 21 having the gold plating layer 25 formed on the copper projections 24 is heated and pressed under the pressure of the prepreg 2.
6, the prepreg 26 is penetrated by the copper protrusion 24 on which the gold plating layer 25 is formed.

On the other hand, in FIG. 4D, the inner wiring layers 2 are formed on both sides of the insulating substrate 27 in which the through holes 29 are formed.
8, 28 'are formed. Here, as the insulating substrate 27, for example, a glass epoxy substrate or the like can be used.

Thereafter, the prepregs 26, 26 'are formed by the copper projections 24, 24' on which the gold plating layers 25, 25 'are formed.
Are disposed on both surfaces of the insulating substrate 27. Here, the copper protrusions 24, 24 'on which the gold plating layers 25, 25' are formed are connected to the inner wiring layers 28, 28 '.
Positioning is performed so as to face the position of the connection land.

Next, in FIG. 5E, the copper projections 24,
The copper foils 21 and 21 ′ having the prepregs 26 and 26 ′ penetrated by 24 ′ and the insulating substrate 27 on which the inner wiring layers 28 and 28 ′ are formed are laminated under heat and pressure. As a result, the inner wiring layers 28 and 28 'and the copper foils 21 and 21' are insulated from each other by the prepregs 26 and 26 '.
4 and 24 'are in close contact with the connection lands of the inner wiring layers 28 and 28' via the gold plating layers 25 and 25 ', and the inner wiring layer 2
8, 28 'and the copper foils 21, 21' are electrically connected. Note that the gold plating layers 25 and 25 ′ are connected to the inner wiring layer 2.
Ultrasonic pressure bonding, diffusion bonding, or the like may be performed to adhere to the connection lands 8 and 28 '.

Next, referring to FIG.
By performing patterning 1 ′, outer wiring layers 30 and 30 ′ having a pad-on-via structure are formed.

As described above, by forming the gold plating layer 25 on the copper protrusions 24 by electrolytic plating, the gold plating layer 25 can be formed on the copper protrusions 24 in a self-aligned manner. Even in the case of miniaturization, the gold plating layer 25 can be accurately formed only in the portion of the copper protrusion 24, and a fine pad-on-via structure can be realized by a simple process.

In the second and third embodiments described above,
Although the method of forming the copper protrusions 14 and 24 by electrolytic plating has been described, the copper protrusions may be formed by etching. Hereinafter, a method of forming a copper protrusion by etching will be described.

FIGS. 6 and 7 are sectional views showing the steps of manufacturing a printed wiring board according to the fourth embodiment of the present invention.

First, in FIG. 6A, copper foil 3
Drilling is performed on the insulating substrate 31 on which the 2a and 33a are formed to form the through holes 34. Here, as the insulating substrate 31, for example, a glass epoxy substrate or the like can be used.

Next, in FIG. 6B, copper plating layers 32b and 33b are formed by performing through-hole plating on the insulating substrate 31 in which the through-holes 34 are formed.

Next, in FIG. 6C, the copper plating layer 3
A first plating resist is applied on the insulating substrate 31 on which the layers 2b and 33b are formed. Then, the copper projections 32c, 33
The first plating resist other than the portions corresponding to the copper projections 32c and 33c is selectively removed by exposing and developing using the pattern corresponding to the copper projection 32c as a mask.
Only the regions corresponding to c and 33c are covered with the first plating resist. The copper plating layers 32b and 33b are partially etched by using the first plating resist that covers only the regions corresponding to the copper protrusions 32c and 33c as a mask, so that the portions corresponding to the copper protrusions 32c and 33c protrude. A step is formed.

Next, in FIG. 6D, after the first plating resist is removed, a second plating resist is applied on the insulating substrate 31 on which the copper protrusions 32c and 33c are formed. Then, by exposing and developing using the pattern corresponding to the inner wiring layers 32d and 33d as a mask, the second plating resist other than the portion corresponding to the inner wiring layers 32d and 33d is selectively removed. , 33d
Is covered only with the second plating resist. Then, the copper plating layer 32 is formed using the second plating resist covering the regions corresponding to the inner wiring layers 32d and 33d as a mask.
By performing etching on b and 33b, inner wiring layers 32d and 33d are formed on the insulating substrate 31.

On the other hand, in FIG. 6E, the same processing is performed on the insulating substrate 36 in which the through holes 41 are formed, so that copper projections 37 are formed on both surfaces of the insulating substrate 36.
a, 38a and the inner wiring layers 37b, 38b are formed. Then, an insulating resin is applied on the insulating substrate 36 on which the copper protrusions 37a and the inner wiring layers 37b are formed, and preliminarily dried to form an insulating resin layer 39 on the insulating substrate 36.

Thereafter, the insulating substrate 31 on which the copper protrusions 32c, 33c and the inner wiring layers 32d, 33d are formed, the copper protrusions 37a, 38a, and the inner wiring layers 37b, 38
b are formed on the insulating substrate 36, and the prepregs 44, 44 'are formed by the copper projections 43, 43'.
Are disposed above and below the insulating substrates 31 and 36, respectively.

Here, Ag pastes 45, 35, and 40 are applied on the copper protrusions 43, 33c, and 38a, and the copper protrusions 43 face the copper protrusions 32c, and the copper protrusions 33c face the copper protrusions 37a. The projection 38a is positioned so as to face the copper projection 43 '.

Next, in FIG. 7F, the prepreg 4
The copper foils 42, 42 'on which the 4, 4' are formed and the insulating substrates 31, 36 are laminated under heat and pressure. This allows
The inner wiring layers 32d, 33d, 37b, 38b and the copper foils 42, 42 'are insulated by the prepregs 44, 44' and the insulating resin layer 39.

The copper protrusions 43 and 32c adhere to each other via the Ag paste 45, and the copper protrusions 33c and 37a
g paste 35, the copper protrusions 38a,
43 'are in close contact with each other via the Ag paste 40. Thereby, the inner wiring layers 32d, 33d, 37b, 38b
And electrical connection with the copper foils 42, 42 '.

Next, in FIG. 7 (g), the copper foils 42, 4
By performing patterning of 2 ′, outer wiring layers 45 and 45 ′ having a pad-on-via structure are formed.

FIGS. 8 and 9 are sectional views showing the steps of manufacturing a printed wiring board according to the fifth embodiment of the present invention.

First, in FIG. 8A, copper foil 5
Drilling is performed on the insulating substrate 51 on which the 2a and 53a are formed to form the through holes 54.

Next, in FIG. 8 (b), copper plating is performed on the insulating substrate 51 in which the through holes 54 are formed to form copper plating layers 52b and 53b.
Then, the gold plating layer 55 is formed by performing gold plating on the insulating substrate 51 on which the copper plating layers 52b and 53b are formed.

Next, in FIG. 8C, the copper plating layer 5
A first plating resist is applied on the insulating substrate 51 on which the 2b, 53b and the gold plating layer 55 are formed. Then, exposure and development are performed using a pattern corresponding to the copper protrusions 56a and 56b as a mask, thereby forming the copper protrusions 56a and 56b.
The first plating resist other than the portion corresponding to b is selectively removed, and only the regions corresponding to the copper protrusions 56a and 56b are covered with the first plating resist. Then, the copper protrusion 56a,
The gold plating layer 55 is etched using the first plating resist covering only the region corresponding to the region 56b as a mask, and the copper plating layers 52b and 53b are etched halfway, thereby corresponding to the copper protrusions 56a and 56b. The step forms a protruding step, and the copper protrusion 56
The gold plating layers 55a and 55b are formed on a and 56b.

Next, in FIG. 8D, after the first plating resist is removed, a second plating resist is applied on the insulating substrate 51 on which the copper protrusions 56a and 56b are formed. Then, by exposing and developing using the pattern corresponding to the inner wiring layers 57a and 57b as a mask, the second plating resist other than the portion corresponding to the inner wiring layers 57a and 57b is selectively removed. , 57b
Is covered with a second plating resist. Then, the copper plating layer 52 is formed using the second plating resist covering the regions corresponding to the inner wiring layers 57a and 57b as a mask.
The inner wiring layers 57a and 57b are formed on the insulating substrate 51 by etching the layers b and 53b.

Next, referring to FIG.
Copper foils 58, 58 ′ having prepregs 60, 60 ′ penetrated by copper protrusions 59, 59 ′ are arranged above and below an insulating substrate 51 having gold plating layers 55 a, 55 b formed on a, 56 b.

Here, the positioning is performed so that the copper projection 59 faces the copper projection 56a and the copper projection 59 'faces the copper projection 56b.

Next, in FIG. 9F, the prepreg 6
Copper foils 58, 58 'on which 0, 60' are formed, and copper projections 5
The insulating substrate 51 having the gold plating layers 55a and 55b formed on 6a and 56b is laminated under heat and pressure. Thus, the inner wiring layers 57a, 57b and the copper foils 58, 58 'are insulated by the prepregs 60, 60', and the copper protrusions 59, 56
a are in close contact with each other via the gold plating layer 55a, and the copper protrusions 56b and 59 'are in close contact with each other via the gold plating layer 55b, so that the inner wiring layers 57a and 57b and the copper foil 5
8, 58 'electrical connections are made.

Next, in FIG. 9 (g), the copper foils 58, 5
By performing patterning of 8 ', outer wiring layers 61 and 61' having a pad-on-via structure are formed.

[0064]

As described above, according to the present invention,
The pad-on-via structure can be realized with a simple process while miniaturizing the via hole.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a printed wiring board according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a process for manufacturing a printed wiring board according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a process for manufacturing a printed wiring board according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a process of manufacturing a printed wiring board according to a third embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a process for manufacturing a printed wiring board according to the third embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a process of manufacturing a printed wiring board according to a fourth embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a process for manufacturing a printed wiring board according to a fourth embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating a process for manufacturing a printed wiring board according to a fifth embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a process for manufacturing a printed wiring board according to the fifth embodiment of the present invention.

[Explanation of symbols]

1, 16, 27, 31, 36, 51 Insulating substrate 2, 3 Conductive pattern 4, 6 Conductive protrusion 5 Dissimilar metal layer 7, 39 Insulating resin layer 8, 11, 11 ', 21, 21', 32a, 33a, 4
2, 42 ', 52a, 53a, 58, 58' Copper foil 12, 22 Plating resist 13, 23 Opening 14, 14 ', 24, 24', 32c, 33c, 37
a, 38a, 43, 43 ', 56a, 56b, 59, 5
9 'copper projections 15, 15', 26, 26 ', 44, 44', 60, 6
0 'prepreg 17, 17', 28, 28 ', 32d, 33d, 37
b, 38b, 57a, 57b Inner wiring layer 18, 18 ', 35, 40, 45 Ag paste 19, 29, 34, 41, 54 Through hole 20, 20', 30, 30 ', 45, 45', 61 6
1 'Outer wiring layer 25, 55, 55a, 55b Gold plating layer 32b, 33b, 52b, 53b Copper plating layer

Continued on the front page F term (reference) 5E317 AA24 BB01 BB11 BB12 CC53 CC60 CD15 CD18 GG16 5E346 AA43 CC04 CC09 CC10 CC31 CC32 CC33 CC38 CC40 DD12 DD23 DD24 DD32 DD33 DD47 DD48 EE09 FF24 GG22 HH26 HH32

Claims (3)

[Claims] A first wiring layer having copper protrusions formed thereon; an insulating layer having the copper protrusions embedded therein; a second wiring layer formed with the insulating layer interposed therebetween; and the first wiring A printed wiring board, comprising: a dissimilar metal layer that electrically connects the layer and a second wiring layer via the copper protrusion. A step of forming a copper protrusion on the first wiring layer; a step of laminating an insulating layer having the copper protrusion penetrated on the first wiring layer; and a step of forming a different metal on the second wiring layer. And a step of laminating the second wiring layer on the insulating layer so that the position of the copper projection corresponds to the formation region of the dissimilar metal. Manufacturing method. A step of forming a copper protrusion on the first wiring layer; a step of forming a dissimilar metal layer on the copper protrusion; and an insulating layer penetrating the copper protrusion in the first wiring layer. A method for manufacturing a printed wiring board, comprising: a step of laminating; and a step of laminating the second wiring layer on the insulating layer.