JP2002093175A - 半導体メモリ装置 - Google Patents

半導体メモリ装置

Info

Publication number
JP2002093175A
JP2002093175A JP2000273596A JP2000273596A JP2002093175A JP 2002093175 A JP2002093175 A JP 2002093175A JP 2000273596 A JP2000273596 A JP 2000273596A JP 2000273596 A JP2000273596 A JP 2000273596A JP 2002093175 A JP2002093175 A JP 2002093175A
Authority
JP
Japan
Prior art keywords
echo signal
cell array
data
memory cell
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000273596A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002093175A5 (enExample
Inventor
Takahiro Tsuruto
孝博 鶴戸
Takayuki Harima
高之 播磨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Priority to JP2000273596A priority Critical patent/JP2002093175A/ja
Priority to US09/946,189 priority patent/US6515938B2/en
Publication of JP2002093175A publication Critical patent/JP2002093175A/ja
Publication of JP2002093175A5 publication Critical patent/JP2002093175A5/ja
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Landscapes

  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
JP2000273596A 2000-09-08 2000-09-08 半導体メモリ装置 Pending JP2002093175A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000273596A JP2002093175A (ja) 2000-09-08 2000-09-08 半導体メモリ装置
US09/946,189 US6515938B2 (en) 2000-09-08 2001-09-04 Semiconductor memory device having an echo signal generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000273596A JP2002093175A (ja) 2000-09-08 2000-09-08 半導体メモリ装置

Publications (2)

Publication Number Publication Date
JP2002093175A true JP2002093175A (ja) 2002-03-29
JP2002093175A5 JP2002093175A5 (enExample) 2005-05-19

Family

ID=18759507

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000273596A Pending JP2002093175A (ja) 2000-09-08 2000-09-08 半導体メモリ装置

Country Status (2)

Country Link
US (1) US6515938B2 (enExample)
JP (1) JP2002093175A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010267326A (ja) * 2009-05-14 2010-11-25 Renesas Electronics Corp 不揮発性半導体記憶装置
JP2011528154A (ja) * 2008-07-01 2011-11-10 エルエスアイ コーポレーション フラッシュ・メモリ・コントローラとフラッシュ・メモリ・アレイの間でインタフェースをとるための方法および装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6842395B2 (en) * 2001-11-05 2005-01-11 Matsushira Electric Industrial Co., Ltd. Semiconductor memory card, method of controlling the same and interface apparatus for semiconductor memory card
KR100915811B1 (ko) * 2006-12-07 2009-09-07 주식회사 하이닉스반도체 반도체 메모리 장치의 데이터 입출력 제어 신호 생성 회로
US9281024B2 (en) 2014-04-17 2016-03-08 International Business Machines Corporation Write/read priority blocking scheme using parallel static address decode path
CN112542193B (zh) * 2020-12-30 2023-07-25 芯天下技术股份有限公司 一种高速读取数据的spi接口的flash存储器

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0214490A (ja) * 1988-06-30 1990-01-18 Ricoh Co Ltd 半導体メモリ装置
JP2000228084A (ja) * 1999-02-05 2000-08-15 Mitsubishi Electric Corp 電圧発生回路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5724288A (en) 1995-08-30 1998-03-03 Micron Technology, Inc. Data communication for memory
KR20010031212A (ko) * 1997-10-20 2001-04-16 우에하라 아끼라 2-페녹시아닐린 유도체
US5920511A (en) 1997-12-22 1999-07-06 Samsung Electronics Co., Ltd. High-speed data input circuit for a synchronous memory device
KR100306966B1 (ko) * 1998-08-04 2001-11-30 윤종용 동기형버스트반도체메모리장치

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0214490A (ja) * 1988-06-30 1990-01-18 Ricoh Co Ltd 半導体メモリ装置
JP2000228084A (ja) * 1999-02-05 2000-08-15 Mitsubishi Electric Corp 電圧発生回路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011528154A (ja) * 2008-07-01 2011-11-10 エルエスアイ コーポレーション フラッシュ・メモリ・コントローラとフラッシュ・メモリ・アレイの間でインタフェースをとるための方法および装置
JP2010267326A (ja) * 2009-05-14 2010-11-25 Renesas Electronics Corp 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
US6515938B2 (en) 2003-02-04
US20020031043A1 (en) 2002-03-14

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