JP2001520824A - 多重i/oスタンダードをサポートする入力/出力バッファ - Google Patents
多重i/oスタンダードをサポートする入力/出力バッファInfo
- Publication number
- JP2001520824A JP2001520824A JP54385098A JP54385098A JP2001520824A JP 2001520824 A JP2001520824 A JP 2001520824A JP 54385098 A JP54385098 A JP 54385098A JP 54385098 A JP54385098 A JP 54385098A JP 2001520824 A JP2001520824 A JP 2001520824A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- buffer
- output buffer
- pull
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000872 buffer Substances 0.000 title claims abstract description 98
- 230000004044 response Effects 0.000 claims 1
- 230000005540 biological transmission Effects 0.000 description 17
- 230000000295 complement effect Effects 0.000 description 12
- 230000006870 function Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000007792 addition Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 101100007418 Caenorhabditis elegans cox-5A gene Proteins 0.000 description 1
- 101000806846 Homo sapiens DNA-(apurinic or apyrimidinic site) endonuclease Proteins 0.000 description 1
- 101000835083 Homo sapiens Tissue factor pathway inhibitor 2 Proteins 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 102100026134 Tissue factor pathway inhibitor 2 Human genes 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002420 orchard Substances 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017581—Coupling arrangements; Interface arrangements programmable
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.入力/出力バッファにおいて、 パッド線によって駆動される入力バッファ、 前記パッド線を駆動する出力バッファであって、複数個の形態特定可能なプル アップ及び複数個のプルダウンを有している出力バッファ、 複数個の供給電圧のうちの1つを前記出力バッファへ形態特定可能に接続する 手段、 を有しており、前記出力バッファを複数個のI/Oスタンダードに従って形態特 定することが可能である入力/出力バッファ。 2.フィールドプログラマブルゲートアレイにおける入力/出力バッファに おいて、前記入力/出力バッファが、 複数個の入力経路を具備している形態特定可能な入力バッファであってパッド 線によって駆動される形態特定可能な入力バッファ、 前記パッド線を形態特定可能に駆動する出力バッファ、 前記入力バッファが複数個のI/Oスタンダードに従って形態特定することが 可能であるように前記複数個の入力経路のうちの1つを選択するために前記入力 バッファを形態特定するコンフィギュレーションメモリセル、 を有している入力/出力バッファ。 3.形態特定可能な出力バッファにおいて、 前記出力バッファによって駆動されるパッド線、 前記パッド線を高電圧レベルへプルする複数個のプルアップ、 前記パッド線を低電圧レベルへプルする複数個のプルダウン、 前記複数個のプルアップのうちの選択したものをイネーブル及びディスエーブ ルさせる手段、 前記複数個のプルダウンのうちの選択したものをイネーブル及びディスエーブ ルさせる手段、 を有している形態特定可能な出力バッファ。 4.請求項3の形態特定可能な出力バッファにおいて、前記複数個のプルア ップのうちの選択したものをイネーブル及びディスエーブルさせる前記手段及び 前記複数個のプルダウンのうちの選択したものをイネーブル及びディスエーブル させる前記手段の各々が1個又はそれ以上のコンフィギュレーションメモリセル によって制御される形態特定論理を有していることを特徴とする形態特定可能な 出力バッファ。 5.複数個の供給電圧レベルと適合性を有する フィールドプログラマブルゲートアレイ入力/出力ブロックにおいて、 パッド、 入力信号線、 複数個の入力経路を具備する入力バッファであって、前記パッド上の電圧に応 答して前記入力信号線へ入力電圧を供給し、1つ又はそれ以上のコンフィギュレ ーションメモリセル内に格納されているデータに基づいて前記複数個の入力経路 のうちの選択した1つに対して形態特定することの可能な入力バッファ、 少なくとも1つのこのような経路上において、前記入力電圧を前記パッド上の 電圧と関連付けるために高及び低電圧レベルの間のトリップ点を設定するために 前記IC外部から供給される入力基準電圧に応答するレベル選択手段、 を有しているフィールドプログラマブルゲートアレイ入力/出力ブロック。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/837,022 | 1997-04-11 | ||
US08/837,022 US5958026A (en) | 1997-04-11 | 1997-04-11 | Input/output buffer supporting multiple I/O standards |
PCT/US1997/015369 WO1998047230A1 (en) | 1997-04-11 | 1997-08-28 | Input/output buffer supporting multiple i/o standards |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001520824A true JP2001520824A (ja) | 2001-10-30 |
JP3948496B2 JP3948496B2 (ja) | 2007-07-25 |
Family
ID=25273292
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54385098A Expired - Lifetime JP3948496B2 (ja) | 1997-04-11 | 1997-08-28 | 多重i/oスタンダードをサポートする入力/出力バッファ |
Country Status (5)
Country | Link |
---|---|
US (1) | US5958026A (ja) |
EP (2) | EP0974195A1 (ja) |
JP (1) | JP3948496B2 (ja) |
DE (1) | DE69739903D1 (ja) |
WO (1) | WO1998047230A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009536491A (ja) * | 2006-05-05 | 2009-10-08 | エヌエックスピー ビー ヴィ | 電子回路及びそのための方法 |
Families Citing this family (55)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6239612B1 (en) * | 1997-08-20 | 2001-05-29 | Altera Corporation | Programmable I/O cells with multiple drivers |
US6870419B1 (en) * | 1997-08-29 | 2005-03-22 | Rambus Inc. | Memory system including a memory device having a controlled output driver characteristic |
DE19856690A1 (de) * | 1997-12-30 | 1999-07-01 | Samsung Electronics Co Ltd | Ausgangstreiberschaltung und eine solche enthaltendes integriertes Speicherschaltkreisbauelement |
US6625795B1 (en) | 1998-06-29 | 2003-09-23 | Xilinx, Inc. | Method and apparatus for placement of input-output design objects into a programmable gate array |
US6289496B1 (en) * | 1998-06-29 | 2001-09-11 | Xilinx, Inc. | Placement of input-output design objects into a programmable gate array supporting multiple voltage standards |
US6433579B1 (en) | 1998-07-02 | 2002-08-13 | Altera Corporation | Programmable logic integrated circuit devices with differential signaling capabilities |
US6346827B1 (en) | 1998-09-09 | 2002-02-12 | Altera Corporation | Programmable logic device input/output circuit configurable as reference voltage input circuit |
US6472903B1 (en) * | 1999-01-08 | 2002-10-29 | Altera Corporation | Programmable logic device input/output architecture with power bus segmentation for multiple I/O standards |
US6271679B1 (en) | 1999-03-24 | 2001-08-07 | Altera Corporation | I/O cell configuration for multiple I/O standards |
US6836151B1 (en) | 1999-03-24 | 2004-12-28 | Altera Corporation | I/O cell configuration for multiple I/O standards |
US6646953B1 (en) | 2000-07-06 | 2003-11-11 | Rambus Inc. | Single-clock, strobeless signaling system |
US6342802B1 (en) | 1999-10-28 | 2002-01-29 | Seagate Technology Llc | Multi-voltage power-up stable input/output buffer circuit in a disc drive |
US6452428B1 (en) * | 1999-11-23 | 2002-09-17 | Intel Corporation | Slew rate control circuit |
US6366128B1 (en) | 2000-09-05 | 2002-04-02 | Xilinx, Inc. | Circuit for producing low-voltage differential signals |
US6426649B1 (en) * | 2000-12-29 | 2002-07-30 | Quicklogic Corporation | Architecture for field programmable gate array |
DE10142679A1 (de) * | 2001-08-31 | 2003-04-03 | Infineon Technologies Ag | Treiberschaltung |
US6696856B1 (en) * | 2001-10-30 | 2004-02-24 | Lightspeed Semiconductor Corporation | Function block architecture with variable drive strengths |
US6911860B1 (en) | 2001-11-09 | 2005-06-28 | Altera Corporation | On/off reference voltage switch for multiple I/O standards |
US6831480B1 (en) | 2003-01-07 | 2004-12-14 | Altera Corporation | Programmable logic device multispeed I/O circuitry |
US7307446B1 (en) | 2003-01-07 | 2007-12-11 | Altera Corporation | Integrated circuit output driver circuitry with programmable preemphasis |
US6940302B1 (en) * | 2003-01-07 | 2005-09-06 | Altera Corporation | Integrated circuit output driver circuitry with programmable preemphasis |
US6963219B1 (en) * | 2003-04-08 | 2005-11-08 | Xilinx, Inc. | Programmable differential internal termination for a low voltage differential signal input or output buffer |
US6924660B2 (en) | 2003-09-08 | 2005-08-02 | Rambus Inc. | Calibration methods and circuits for optimized on-die termination |
US7504854B1 (en) | 2003-09-19 | 2009-03-17 | Xilinx, Inc. | Regulating unused/inactive resources in programmable logic devices for static power reduction |
US7098689B1 (en) | 2003-09-19 | 2006-08-29 | Xilinx, Inc. | Disabling unused/inactive resources in programmable logic devices for static power reduction |
US7498836B1 (en) | 2003-09-19 | 2009-03-03 | Xilinx, Inc. | Programmable low power modes for embedded memory blocks |
US7549139B1 (en) | 2003-09-19 | 2009-06-16 | Xilinx, Inc. | Tuning programmable logic devices for low-power design implementation |
US7581124B1 (en) | 2003-09-19 | 2009-08-25 | Xilinx, Inc. | Method and mechanism for controlling power consumption of an integrated circuit |
US7154318B2 (en) * | 2003-11-18 | 2006-12-26 | Stmicroelectronics Pvt. Ltd. | Input/output block with programmable hysteresis |
US6980020B2 (en) * | 2003-12-19 | 2005-12-27 | Rambus Inc. | Calibration methods and circuits for optimized on-die termination |
DE102004001434B4 (de) * | 2004-01-09 | 2013-07-11 | Qimonda Ag | Speicherbauelement |
US7132847B1 (en) | 2004-02-24 | 2006-11-07 | Altera Corporation | Programmable slew rate control for differential output |
DE102004063926B4 (de) * | 2004-03-24 | 2017-10-19 | Infineon Technologies Ag | Konfigurierbare Treiberzelle eines logischen Zellenfeldes |
US7598779B1 (en) | 2004-10-08 | 2009-10-06 | Altera Corporation | Dual-mode LVDS/CML transmitter methods and apparatus |
US7498839B1 (en) | 2004-10-22 | 2009-03-03 | Xilinx, Inc. | Low power zones for programmable logic devices |
JP4620771B2 (ja) * | 2005-03-16 | 2011-01-26 | ゲートロケット・インコーポレーテッド | Fpgaエミュレーションシステム |
US7365570B2 (en) * | 2005-05-25 | 2008-04-29 | Micron Technology, Inc. | Pseudo-differential output driver with high immunity to noise and jitter |
US7265587B1 (en) | 2005-07-26 | 2007-09-04 | Altera Corporation | LVDS output buffer pre-emphasis methods and apparatus |
US7307863B2 (en) * | 2005-08-02 | 2007-12-11 | Inphi Corporation | Programmable strength output buffer for RDIMM address register |
US7498835B1 (en) | 2005-11-04 | 2009-03-03 | Xilinx, Inc. | Implementation of low power standby modes for integrated circuits |
US7345944B1 (en) | 2006-01-11 | 2008-03-18 | Xilinx, Inc. | Programmable detection of power failure in an integrated circuit |
US7953162B2 (en) * | 2006-11-17 | 2011-05-31 | Intersil Americas Inc. | Use of differential pair as single-ended data paths to transport low speed data |
US7844764B2 (en) * | 2007-10-01 | 2010-11-30 | Honeywell International Inc. | Unitary control module with adjustable input/output mapping |
US7839016B2 (en) * | 2007-12-13 | 2010-11-23 | Arm Limited | Maintaining output I/O signals within an integrated circuit with multiple power domains |
US8347251B2 (en) * | 2007-12-31 | 2013-01-01 | Sandisk Corporation | Integrated circuit and manufacturing process facilitating selective configuration for electromagnetic compatibility |
US7733118B2 (en) * | 2008-03-06 | 2010-06-08 | Micron Technology, Inc. | Devices and methods for driving a signal off an integrated circuit |
US8271810B1 (en) | 2009-07-24 | 2012-09-18 | Cypress Semiconductor Corporation | Method and apparatus for dynamically detecting environmental conditions and adjusting drive strength in response to the detecting |
US8072242B2 (en) * | 2009-12-18 | 2011-12-06 | Meta Systems | Merged programmable output driver |
FR2960720A1 (fr) * | 2010-05-25 | 2011-12-02 | St Microelectronics Sa | Procede de protection d'un circuit logique contre des radiations externes et dispositif electronique associe. |
US8823405B1 (en) | 2010-09-10 | 2014-09-02 | Xilinx, Inc. | Integrated circuit with power gating |
US8621377B2 (en) | 2011-03-24 | 2013-12-31 | Honeywell International Inc. | Configurable HVAC controller terminal labeling |
US8638120B2 (en) | 2011-09-27 | 2014-01-28 | International Business Machines Corporation | Programmable gate array as drivers for data ports of spare latches |
US9000800B1 (en) | 2012-09-17 | 2015-04-07 | Xilinx, Inc. | System and method of eliminating on-board calibration resistor for on-die termination |
US8786322B2 (en) | 2012-12-21 | 2014-07-22 | Samsung Electro-Mechanics Co., Ltd. | Gate driver circuit and operating method thereof |
US10353457B1 (en) | 2015-03-04 | 2019-07-16 | Altera Corporation | Systems and methods for sleep mode power savings in integrated circuit devices |
Family Cites Families (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US34808A (en) * | 1862-04-01 | Improvement in machines for splitting kindling-wood | ||
JPS6050940A (ja) * | 1983-08-31 | 1985-03-22 | Toshiba Corp | 半導体集積回路 |
US4860244A (en) * | 1983-11-07 | 1989-08-22 | Digital Equipment Corporation | Buffer system for input/output portion of digital data processing system |
JPS6153827A (ja) * | 1984-08-23 | 1986-03-17 | Fujitsu Ltd | 閾値可変型入力回路 |
US4821185A (en) * | 1986-05-19 | 1989-04-11 | American Telephone And Telegraph Company | I/O interface system using plural buffers sized smaller than non-overlapping contiguous computer memory portions dedicated to each buffer |
JPH0728214B2 (ja) * | 1987-02-06 | 1995-03-29 | 株式会社日立製作所 | 半導体集積回路装置 |
KR900001817B1 (ko) * | 1987-08-01 | 1990-03-24 | 삼성전자 주식회사 | 저항 수단을 이용한 씨 모스 티티엘 인푸트 버퍼 |
JPH02146815A (ja) * | 1988-11-28 | 1990-06-06 | Mitsubishi Electric Corp | 半導体集積回路の入力回路 |
US5005173A (en) * | 1988-12-07 | 1991-04-02 | Texas Instruments Incorporated | Parallel module testing |
US5075885A (en) * | 1988-12-21 | 1991-12-24 | National Semiconductor Corporation | Ecl eprom with cmos programming |
JP3453757B2 (ja) * | 1989-05-29 | 2003-10-06 | 株式会社日立製作所 | バッファ管理方法 |
JPH03117020A (ja) * | 1989-09-28 | 1991-05-17 | Nec Corp | 集積回路の出力バッファ回路 |
JPH04158627A (ja) * | 1990-10-23 | 1992-06-01 | Nec Corp | 半導体集積回路用出力バッファ |
JP2609756B2 (ja) * | 1990-10-26 | 1997-05-14 | 株式会社東芝 | 半導体集積回路の使用方法 |
US5155392A (en) * | 1990-11-05 | 1992-10-13 | Motorola, Inc. | Low di/dt BiCMOS output buffer with improved speed |
JP3079515B2 (ja) * | 1991-01-29 | 2000-08-21 | 株式会社東芝 | ゲ−トアレイ装置及び入力回路及び出力回路及び降圧回路 |
JPH05252025A (ja) * | 1991-10-28 | 1993-09-28 | Texas Instr Inc <Ti> | 論理モジュールおよび集積回路 |
US5298807A (en) * | 1991-12-23 | 1994-03-29 | Intel Corporation | Buffer circuitry for transferring signals from TTL circuitry to dual range CMOS circuitry |
JP3253389B2 (ja) * | 1992-03-31 | 2002-02-04 | 株式会社東芝 | 半導体集積回路装置 |
DE69330219T2 (de) * | 1992-06-15 | 2001-08-30 | Fujitsu Ltd | Integrierte Halbleiterschaltung mit für einen Betrieb mit geringer Amplitude angepasster Eingangs/Ausgangs-Schnittstelle |
DE4224804C1 (de) * | 1992-07-27 | 1994-01-13 | Siemens Ag | Programmierbare logische Schaltungsanordnung |
JPH0653827A (ja) * | 1992-08-03 | 1994-02-25 | Mitsubishi Electric Corp | Pll回路 |
JPH06209252A (ja) * | 1992-09-29 | 1994-07-26 | Siemens Ag | Cmos入力段 |
US5300835A (en) * | 1993-02-10 | 1994-04-05 | Cirrus Logic, Inc. | CMOS low power mixed voltage bidirectional I/O buffer |
US5550839A (en) * | 1993-03-12 | 1996-08-27 | Xilinx, Inc. | Mask-programmed integrated circuits having timing and logic compatibility to user-configured logic arrays |
JPH07142983A (ja) * | 1993-06-22 | 1995-06-02 | Kawasaki Steel Corp | 半導体集積回路の入力回路 |
US5521530A (en) * | 1994-08-31 | 1996-05-28 | Oki Semiconductor America, Inc. | Efficient method and resulting structure for integrated circuits with flexible I/O interface and power supply voltages |
US5629636A (en) * | 1994-10-19 | 1997-05-13 | Crosspoint Solutions, Inc. | Ram-logic tile for field programmable gate arrays |
JP3031195B2 (ja) * | 1995-02-28 | 2000-04-10 | 株式会社日立製作所 | 入出力バッファ回路装置 |
US5606275A (en) * | 1995-09-05 | 1997-02-25 | Motorola, Inc. | Buffer circuit having variable output impedance |
TW331599B (en) * | 1995-09-26 | 1998-05-11 | Toshiba Co Ltd | Array substrate for LCD and method of making same |
US5583454A (en) * | 1995-12-01 | 1996-12-10 | Advanced Micro Devices, Inc. | Programmable input/output driver circuit capable of operating at a variety of voltage levels and having a programmable pullup/pulldown function |
JPH09181594A (ja) * | 1995-12-26 | 1997-07-11 | Mitsubishi Electric Corp | 入力回路 |
US5862390A (en) * | 1996-03-15 | 1999-01-19 | S3 Incorporated | Mixed voltage, multi-rail, high drive, low noise, adjustable slew rate input/output buffer |
US5801548A (en) * | 1996-04-11 | 1998-09-01 | Xilinx Inc | Configurable performance-optimized programmable logic device |
US5777488A (en) * | 1996-04-19 | 1998-07-07 | Seeq Technology, Inc. | Integrated circuit I/O node useable for configuration input at reset and normal output at other times |
-
1997
- 1997-04-11 US US08/837,022 patent/US5958026A/en not_active Expired - Lifetime
- 1997-08-28 EP EP97940729A patent/EP0974195A1/en not_active Withdrawn
- 1997-08-28 DE DE69739903T patent/DE69739903D1/de not_active Expired - Lifetime
- 1997-08-28 JP JP54385098A patent/JP3948496B2/ja not_active Expired - Lifetime
- 1997-08-28 WO PCT/US1997/015369 patent/WO1998047230A1/en not_active Application Discontinuation
- 1997-08-28 EP EP02027043A patent/EP1294097B1/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009536491A (ja) * | 2006-05-05 | 2009-10-08 | エヌエックスピー ビー ヴィ | 電子回路及びそのための方法 |
US8106705B2 (en) | 2006-05-05 | 2012-01-31 | Synopsys, Inc. | Control circuit for PVT conditions of a module |
Also Published As
Publication number | Publication date |
---|---|
US5958026A (en) | 1999-09-28 |
EP1294097B1 (en) | 2010-06-02 |
EP1294097A2 (en) | 2003-03-19 |
JP3948496B2 (ja) | 2007-07-25 |
WO1998047230A1 (en) | 1998-10-22 |
EP0974195A1 (en) | 2000-01-26 |
DE69739903D1 (de) | 2010-07-15 |
EP1294097A3 (en) | 2004-11-03 |
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Legal Events
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A621 | Written request for application examination |
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