JP2001501774A - 装着SiCダイ及びSiC用ダイ装着方法 - Google Patents
装着SiCダイ及びSiC用ダイ装着方法Info
- Publication number
- JP2001501774A JP2001501774A JP09529385A JP52938597A JP2001501774A JP 2001501774 A JP2001501774 A JP 2001501774A JP 09529385 A JP09529385 A JP 09529385A JP 52938597 A JP52938597 A JP 52938597A JP 2001501774 A JP2001501774 A JP 2001501774A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- die
- sic
- mounting
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29155—Nickel [Ni] as principal constituent
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
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- H01L2924/01006—Carbon [C]
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- H01L2924/01032—Germanium [Ge]
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- H01L2924/0105—Tin [Sn]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1027—IV
- H01L2924/10272—Silicon Carbide [SiC]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.(a)上面がめっきされたパッケージを準備し、 (b)SiCダイを準備し、 (c)前記SiCダイ上に、SiCダイに結合する第1層を形成し、 (d)前記第1層上に、第1層に結合する第2層を形成し、 (e)前記第2層がパッケージに装着されるように該パッケージ上にSiCダイ をスクラビングすることからなるSiC用ダイ装着方法。 2.工程(c)で、上面が金めっきされたパッケージを準備する請求項1記載の 方法。 3.工程(c)で、SiCダイ上に第1層としてニッケル層を形成する請求項1 記載の方法。 4.工程(c)で、2000〜10000A(ここで、Aはオングストロームを 示す)の厚さのニッケル層を形成する請求項3記載の方法。 5.工程(d)で、第1層上に第2層としてアモルファスシリコン層を形成する 請求項1記載の方法。 6.工程(d)で、5000〜30000A(ここで、Aはオングストロームを 示す)の厚さのアモルファスシリコン層を形成する請求項5記載の方法。 7.工程(d)で、第1層上に第2層としてアモルファスシリコン層を形成し、 工程(e)で、Au−Si共晶を形成するように前記パッ ケージ上にSiCダイをスクラビングする請求項2記載の方法。 8.工程(c)で、SiCダイ上に第1層としてニッケル層を形成する請求項7 記載の方法。 9.工程(e)で、めっき及び第1層が共晶を形成するようにパッケージ上にS iCダイをスクラビングする請求項7記載の方法。 10.上面がめっきされたパッケージ、 SiCダイ、 SiCダイに結合した第1層、 第1層及びめっきに結合した第2層からなる装着SiCダイ。 11.めっきが金めっきである請求項10記載の装着SiCダイ。 12.第1層がニッケル層である請求項10記載の装着SiCダイ。 13.ニッケル層が2000〜10000A(ここで、Aはオングストロームを 示す)の厚さである請求項12記載の装着SiCダイ。 14.第2層がアモルファスシリコン層である請求項10記載の装着SiCダイ 。 15.アモルファスシリコン層が5000〜30000A(ここで、Aはオング ストロームを示す)の厚さである請求項14記載の装着SiCダイ。 16.第2層がアモルファスシリコン層であり、アモルファスシリコン層と金め っきとがAu−Si共晶を形成する請求項1 1記載の装着SiCダイ。 17.第1層がニッケル層である請求項16記載の装着SiCダイ。 18.第2層がめっきと共晶を形成する請求項10記載の装着SiCダイ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/600,777 US5851852A (en) | 1996-02-13 | 1996-02-13 | Die attached process for SiC |
US08/600,777 | 1996-02-13 | ||
PCT/US1997/001790 WO1997030474A1 (en) | 1996-02-13 | 1997-01-31 | DIE ATTACHED SiC AND DIE ATTACH PROCEDURE FOR SiC |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2001501774A true JP2001501774A (ja) | 2001-02-06 |
JP2001501774A5 JP2001501774A5 (ja) | 2004-10-28 |
JP3971456B2 JP3971456B2 (ja) | 2007-09-05 |
Family
ID=24404995
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52938597A Expired - Lifetime JP3971456B2 (ja) | 1996-02-13 | 1997-01-31 | 装着SiCダイ及びSiC用ダイ装着方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5851852A (ja) |
EP (1) | EP0880801B1 (ja) |
JP (1) | JP3971456B2 (ja) |
DE (1) | DE69711852T2 (ja) |
WO (1) | WO1997030474A1 (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6613978B2 (en) | 1993-06-18 | 2003-09-02 | Maxwell Technologies, Inc. | Radiation shielding of three dimensional multi-chip modules |
US5880403A (en) | 1994-04-01 | 1999-03-09 | Space Electronics, Inc. | Radiation shielding of three dimensional multi-chip modules |
US6261508B1 (en) | 1994-04-01 | 2001-07-17 | Maxwell Electronic Components Group, Inc. | Method for making a shielding composition |
US6455864B1 (en) | 1994-04-01 | 2002-09-24 | Maxwell Electronic Components Group, Inc. | Methods and compositions for ionizing radiation shielding |
US6720493B1 (en) | 1994-04-01 | 2004-04-13 | Space Electronics, Inc. | Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages |
US5916513A (en) * | 1997-08-04 | 1999-06-29 | Motorola | Method and apparatus for affixing components to a substrate when a manufacturing line ceases operation |
KR100303446B1 (ko) * | 1998-10-29 | 2002-10-04 | 삼성전자 주식회사 | 액정표시장치용박막트랜지스터기판의제조방법 |
US7166320B1 (en) | 2000-02-14 | 2007-01-23 | Seagate Technology Llc | Post-deposition annealed recording media and method of manufacturing the same |
US6368899B1 (en) * | 2000-03-08 | 2002-04-09 | Maxwell Electronic Components Group, Inc. | Electronic device packaging |
US7382043B2 (en) | 2002-09-25 | 2008-06-03 | Maxwell Technologies, Inc. | Method and apparatus for shielding an integrated circuit from radiation |
US7191516B2 (en) | 2003-07-16 | 2007-03-20 | Maxwell Technologies, Inc. | Method for shielding integrated circuit devices |
DE102004015017B4 (de) * | 2004-03-26 | 2006-11-16 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Erzeugung von mechanischen und elektrischen Verbindungen zwischen den Oberflächen zweier Substrate |
US8318545B2 (en) * | 2010-01-28 | 2012-11-27 | Freescale Semiconductor, Inc. | Method of making a mounted gallium nitride device |
US20130330571A1 (en) * | 2012-06-06 | 2013-12-12 | Northrop Grumman Systems Corporation | Method and apparatus for providing improved backside metal contacts to silicon carbide |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3573568A (en) * | 1969-06-18 | 1971-04-06 | Gen Electric | Light emitting semiconductor chips mounted in a slotted substrate forming a display apparatus |
US4042951A (en) * | 1975-09-25 | 1977-08-16 | Texas Instruments Incorporated | Gold-germanium alloy contacts for a semiconductor device |
US4457976A (en) * | 1983-03-28 | 1984-07-03 | Rca Corporation | Method for mounting a sapphire chip on a metal base and article produced thereby |
US4657825A (en) * | 1984-12-24 | 1987-04-14 | Ngk Spark Plug Co., Ltd. | Electronic component using a silicon carbide substrate and a method of making it |
US4978052A (en) * | 1986-11-07 | 1990-12-18 | Olin Corporation | Semiconductor die attach system |
EP0277645A1 (en) * | 1987-02-02 | 1988-08-10 | Sumitomo Electric Industries Limited | Ceramics-metal jointed body |
US5368880A (en) * | 1989-12-06 | 1994-11-29 | Westinghouse Electric Corporation | Eutectic bond and method of gold/titanium eutectic bonding of cadmium telluride to sapphire |
US5008735A (en) * | 1989-12-07 | 1991-04-16 | General Instrument Corporation | Packaged diode for high temperature operation |
JP3293966B2 (ja) * | 1993-07-05 | 2002-06-17 | 太平洋セメント株式会社 | セラミックスとシリコン板との接合方法 |
-
1996
- 1996-02-13 US US08/600,777 patent/US5851852A/en not_active Expired - Lifetime
-
1997
- 1997-01-31 EP EP97905753A patent/EP0880801B1/en not_active Expired - Lifetime
- 1997-01-31 WO PCT/US1997/001790 patent/WO1997030474A1/en active IP Right Grant
- 1997-01-31 DE DE69711852T patent/DE69711852T2/de not_active Expired - Lifetime
- 1997-01-31 JP JP52938597A patent/JP3971456B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69711852D1 (de) | 2002-05-16 |
WO1997030474A1 (en) | 1997-08-21 |
US5851852A (en) | 1998-12-22 |
EP0880801A1 (en) | 1998-12-02 |
JP3971456B2 (ja) | 2007-09-05 |
DE69711852T2 (de) | 2002-10-10 |
EP0880801B1 (en) | 2002-04-10 |
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