JP2001298112A - 電子部品と、この電子部品の実装構造 - Google Patents

電子部品と、この電子部品の実装構造

Info

Publication number
JP2001298112A
JP2001298112A JP2000110527A JP2000110527A JP2001298112A JP 2001298112 A JP2001298112 A JP 2001298112A JP 2000110527 A JP2000110527 A JP 2000110527A JP 2000110527 A JP2000110527 A JP 2000110527A JP 2001298112 A JP2001298112 A JP 2001298112A
Authority
JP
Japan
Prior art keywords
electronic component
chip
interposer
solder
solder bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000110527A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001298112A5 (https=
Inventor
Hirokazu Tanaka
宏和 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Corp
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Corp, Omron Tateisi Electronics Co filed Critical Omron Corp
Priority to JP2000110527A priority Critical patent/JP2001298112A/ja
Publication of JP2001298112A publication Critical patent/JP2001298112A/ja
Publication of JP2001298112A5 publication Critical patent/JP2001298112A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
JP2000110527A 2000-04-12 2000-04-12 電子部品と、この電子部品の実装構造 Pending JP2001298112A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000110527A JP2001298112A (ja) 2000-04-12 2000-04-12 電子部品と、この電子部品の実装構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000110527A JP2001298112A (ja) 2000-04-12 2000-04-12 電子部品と、この電子部品の実装構造

Publications (2)

Publication Number Publication Date
JP2001298112A true JP2001298112A (ja) 2001-10-26
JP2001298112A5 JP2001298112A5 (https=) 2005-04-21

Family

ID=18623021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000110527A Pending JP2001298112A (ja) 2000-04-12 2000-04-12 電子部品と、この電子部品の実装構造

Country Status (1)

Country Link
JP (1) JP2001298112A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009116517A1 (ja) * 2008-03-17 2009-09-24 日本電気株式会社 電子装置及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009116517A1 (ja) * 2008-03-17 2009-09-24 日本電気株式会社 電子装置及びその製造方法
US8525333B2 (en) 2008-03-17 2013-09-03 Renesas Electronics Corporation Electronic device and manufacturing method therefor

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