JP2001291792A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2001291792A JP2001291792A JP2000104339A JP2000104339A JP2001291792A JP 2001291792 A JP2001291792 A JP 2001291792A JP 2000104339 A JP2000104339 A JP 2000104339A JP 2000104339 A JP2000104339 A JP 2000104339A JP 2001291792 A JP2001291792 A JP 2001291792A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor element
- recess
- cut
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に関
し、特に多層配線基板に形成された凹部内に半導体素子
を搭載した実装構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a mounting structure in which a semiconductor element is mounted in a recess formed in a multilayer wiring board.
【０００２】[0002]
【従来の技術】半導体素子の実装構造の薄型化のため
に、誘電体基板に凹部を形成しその中に半導体素子を搭
載する方式が用いられている。この実装構造は、ＣＩＢ
（chip in board ）構造と呼ばれるが、この構造の半導
体装置では、半導体素子はポッティング樹脂などを用い
て凹部内に封止される。2. Description of the Related Art In order to reduce the thickness of a semiconductor device mounting structure, a method of forming a concave portion in a dielectric substrate and mounting the semiconductor device therein has been used. This mounting structure is CIB
Although called a (chip in board) structure, in a semiconductor device having this structure, a semiconductor element is sealed in a recess using a potting resin or the like.
【０００３】図９は、ＣＩＢ構造の半導体装置に用いら
れる多層配線基板の一例を示す斜視図である。同図に示
されるように、第１金属層２１０、第２金属層２１１、
第３金属層２１２、第４金属層２１３が、第１誘電体層
２０１、第２誘電体層２０２および第３誘電体層２０３
を挟んで積層されている。第３誘電体層２０３、第２誘
電体層２０２には、半導体素子を搭載するための凹部２
０８が、第２金属層２１１の表面を露出させるように、
ザグリ加工等により形成されている。FIG. 9 is a perspective view showing an example of a multilayer wiring board used for a semiconductor device having a CIB structure. As shown in the figure, a first metal layer 210, a second metal layer 211,
The third metal layer 212 and the fourth metal layer 213 are composed of the first dielectric layer 201, the second dielectric layer 202, and the third dielectric layer 203.
Are laminated. The third dielectric layer 203 and the second dielectric layer 202 have concave portions 2 for mounting a semiconductor element.
08 exposes the surface of the second metal layer 211,
It is formed by counterboring or the like.
【０００４】図１０は、従来のＣＩＢ構造の半導体装置
の半導体素子の搭載部の部分を示す断面図である。通
常、第１金属層２１０と第３金属層２１２はグランド層
として用いられ、第２金属層２１１は電源層として用い
られる。そして、第４金属層２１３が信号配線層として
用いられる。第２金属層２１１、第３金属層２１２、第
４金属層２１３には、必要に応じてマイクロストリップ
線路または電源層が形成される。各層の金属層間はスル
ーホールを介して接続されている。凹部内に露出した第
２金属層２１１には、半導体素子を搭載するダイパッド
とワイヤを接続するためのボンディングパッドが形成さ
れている。FIG. 10 is a sectional view showing a mounting portion of a semiconductor element of a conventional semiconductor device having a CIB structure. Usually, the first metal layer 210 and the third metal layer 212 are used as a ground layer, and the second metal layer 211 is used as a power supply layer. Then, the fourth metal layer 213 is used as a signal wiring layer. A microstrip line or a power supply layer is formed on the second metal layer 211, the third metal layer 212, and the fourth metal layer 213 as necessary. The metal layers of each layer are connected via through holes. A bonding pad for connecting a wire to a die pad on which the semiconductor element is mounted is formed on the second metal layer 211 exposed in the recess.
【０００５】この多層配線基板を用いて、半導体装置は
以下のように組み立てられる。第２金属層２１１に形成
されたダイパッド上にはんだ等の接着剤２０７を用いて
半導体素子２０６を固着する（ダイボンド）。そして、
ボンディングワイヤ２０４を用いて、半導体素子２０６
の電極とボンディングパッド間を接続する。次に、搭載
された半導体素子２０６が外部からの機械的な衝撃やゴ
ミ、湿気の影響を受けないようにするために、ポッティ
ング樹脂２０５を凹部２０８内に充填することにより半
導体素子２０６を封止する。その後、第４金属層２１３
上に、チップコンデンサ、チップ抵抗、チップインダク
タ等の部品がはんだペースト等の接着剤を介して載置さ
れ、リフロー炉等を経由することにより、チップ部品を
第４金属層２１３上に固着される。これにより、一つの
有機的な電子回路が構成される。なお、このようにして
組み立てられたＣＩＢ構造の半導体装置の外部回路との
接続は、多層配線基板の周辺に引き出された配線に接続
された外部端子またはスルーホール内に取り付けられた
外部端子を用いて行われる。Using this multilayer wiring board, a semiconductor device is assembled as follows. The semiconductor element 206 is fixed on the die pad formed on the second metal layer 211 using an adhesive 207 such as solder (die bonding). And
The semiconductor element 206 is formed by using the bonding wire 204.
And the bonding pad are connected. Next, the semiconductor element 206 is sealed by filling the potting resin 205 into the recess 208 so that the mounted semiconductor element 206 is not affected by external mechanical shock, dust, or moisture. I do. Then, the fourth metal layer 213
Components such as a chip capacitor, a chip resistor, and a chip inductor are placed thereon via an adhesive such as a solder paste, and the chip component is fixed on the fourth metal layer 213 by passing through a reflow furnace or the like. . This constitutes one organic electronic circuit. The connection of the CIB-structured semiconductor device assembled as described above to an external circuit is performed by using an external terminal connected to a wiring drawn around the multilayer wiring board or an external terminal mounted in a through hole. Done.
【０００６】[0006]
【発明が解決しようとする課題】上述した従来のＣＩＢ
構造の半導体装置の製造工程において、第４金属層２１
３上にチップ部品を搭載するためにリフロー炉により加
熱された場合、半導体素子２０６を固着する接着剤２０
７に含まれる空気が膨張する。その際、接着剤２０７の
周囲はポッティング樹脂２０５が充填されているため、
膨張した空気は逃げ道がなく、第２金属層２１１−半導
体素子２０６間、および、第２、第３誘電体層２０２、
２０３−ポッティング樹脂２０５間を剥離させる力が生
じる。しかし、従来構造では、ポッティング樹脂２０５
が、凹部に搭載されている半導体素子２０６を埋め込む
ように充填してあるだけで、特に剥離に耐え得る構造は
備えていない。そのため、接着剤２０７に含まれる空気
が加熱により膨張すると、ポッティング樹脂２０５およ
び半導体素子２０６は、膨張力に抗しきれず剥離してし
まう可能性が高かった。本発明の課題は、上述した従来
技術の問題点を解決することであって、その目的は、配
線基板からの半導体素子の剥離および配線基板からのポ
ッティング樹脂の剥離を防止するための配線基板構造を
提供することである。The above-described conventional CIB
In the manufacturing process of the semiconductor device having the structure, the fourth metal layer 21
When heated by a reflow furnace to mount the chip component on the adhesive 3, the adhesive 20 for fixing the semiconductor element 206
The air contained in 7 expands. At this time, since the potting resin 205 is filled around the adhesive 207,
The inflated air has no escape route, and is provided between the second metal layer 211 and the semiconductor element 206 and between the second and third dielectric layers 202 and 202.
A force for peeling between 203 and the potting resin 205 is generated. However, in the conventional structure, the potting resin 205
However, only the semiconductor element 206 mounted in the recess is filled so as to be buried, and no structure capable of withstanding peeling is provided. Therefore, when the air contained in the adhesive 207 expands due to heating, the potting resin 205 and the semiconductor element 206 have a high possibility of peeling without being able to withstand the expansion force. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a wiring board structure for preventing peeling of a semiconductor element from a wiring board and peeling of a potting resin from the wiring board. It is to provide.
【０００７】[0007]
【課題を解決するための手段】上記の目的を達成するた
め、本発明によれば、多層配線基板に形成された凹部内
に封止樹脂にて封止された半導体素子が搭載されている
半導体装置において、前記凹部の底面、および／また
は、側面には前記封止樹脂の剥離を防止する切り込みが
形成されていることを特徴とする半導体装置、が提供さ
れる。According to the present invention, there is provided a semiconductor device in which a semiconductor element sealed with a sealing resin is mounted in a recess formed in a multilayer wiring board. In the device, there is provided a semiconductor device, wherein a cut is formed on a bottom surface and / or a side surface of the concave portion to prevent peeling of the sealing resin.
【０００８】そして、好ましくは、前記切り込みは、少
なくとも前記半導体素子の対向する２辺を挟むように、
前記半導体素子に対し対称的に形成される。また、好ま
しくは、前記半導体素子の辺に沿って連続的に若しくは
不連続的に形成される。さらに、一層好ましくは、前記
切り込みは、ザグリ加工によって形成される。[0008] Preferably, the notch is formed so as to sandwich at least two opposing sides of the semiconductor element.
It is formed symmetrically with respect to the semiconductor element. Preferably, the semiconductor device is formed continuously or discontinuously along the side of the semiconductor element. Still more preferably, the cut is formed by counterboring.
【０００９】[0009]
【発明の実施の形態】次に、図面を参照して本発明の実
施の形態について説明する。図１（ａ）は、本発明の第
１の実施の形態を示す断面図であり、図１（ｂ）は、図
１（ａ）の部分拡大図である。図１において、図９、図
１０に示した従来例の部分と同等の部分には下２桁が共
通する参照番号が付せられているので重複する説明は省
略する。本実施の形態の図１０に示した従来例と相違す
る点は、本実施の形態においては、凹部１０８の底面
の、半導体素子１０６の搭載部とボンディングパッドと
の間に、テーパ角のついたザグリ１１４が形成されてい
る点である。そして、このザグリ１１４の内部にもポッ
ティング樹脂１０５が充填されている。このように構成
された半導体装置においては、リフロー炉等においては
んだ等の接着剤１０７が加熱されこの中に含まれる空気
が膨張して半導体素子１０６を剥離しようとしても、ポ
ッティング樹脂１０５が第１誘電体層１０１（または第
２金属層１１１を埋め込むように形成された第２誘電体
層）内に食い込んでいるため、ポッティング樹脂１０５
は剥離することがなく、半導体素子１０６を押さえ込
み、その剥離を防止する。Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a sectional view showing a first embodiment of the present invention, and FIG. 1B is a partially enlarged view of FIG. 1A. In FIG. 1, the same parts as those of the conventional example shown in FIG. 9 and FIG. The difference between the present embodiment and the conventional example shown in FIG. 10 is that, in the present embodiment, a taper angle is provided between the mounting portion of the semiconductor element 106 and the bonding pad on the bottom surface of the concave portion 108. This is the point where the counterbore 114 is formed. The inside of the counterbore 114 is also filled with the potting resin 105. In the semiconductor device configured as described above, even if the adhesive 107 such as solder is heated in a reflow oven or the like and the air contained therein expands to separate the semiconductor element 106, the potting resin 105 is removed by the first dielectric. Since the body layer 101 (or the second dielectric layer formed so as to bury the second metal layer 111) is cut into the body layer 101, the potting resin 105
Does not peel off, but holds down the semiconductor element 106 to prevent the peeling.
【００１０】図１（ｂ）に示すように、テーパ角のつい
たザグリ１１４は、基板の平面に対してθのテーパ角を
有している。このテーパ角θは、４５°≦θ＜９０°の
範囲で任意に設定される。また、反対側のザグリのテー
パ角θは、９０°＜θ≦１３５°に設定される。このよ
うなクサビ形の形状にすることにより、ポッティング樹
脂１０５の上方向のズレに対して強度が増し、半導体素
子１０６の金属層から剥離を効果的に防止することがで
きる。図１には、ザグリ１１４は第２金属層１１１にか
からないように形成されているが、ボンディングパッド
やダイパッドの第２金属層をザグリ形成領域にまで引き
延ばし、第２金属層１１１にザグリを入れるようにして
もよい。また、ザグリは、第１誘電体層１０１を貫通す
る深さにまで形成してもよいが、第１金属層１１０は貫
通しない深さとする。As shown in FIG. 1B, the counterbore 114 having a taper angle has a taper angle of θ with respect to the plane of the substrate. The taper angle θ is arbitrarily set within a range of 45 ° ≦ θ <90 °. The taper angle θ of the counterbore on the opposite side is set to 90 ° <θ ≦ 135 °. With such a wedge-shaped shape, the strength against the upward displacement of the potting resin 105 is increased, and peeling from the metal layer of the semiconductor element 106 can be effectively prevented. In FIG. 1, the counterbore 114 is formed so as not to cover the second metal layer 111. It may be. The counterbore may be formed to a depth that penetrates the first dielectric layer 101, but is set to a depth that does not penetrate the first metal layer 110.
【００１１】図２は、本発明の第２の実施の形態を示す
断面図である。本実施の形態の図１に示した第１の実施
の形態と相違する点は、テーパ角のついたザグリの形状
が異なる点である。つまり、前記図１のクサビ形の形状
に対して、外側に向いたザグリが入れられている。強度
的にはクサビ形とほとんど差異がなく、また工程的にも
単純であり、作業時間を短縮することが可能である。FIG. 2 is a sectional view showing a second embodiment of the present invention. The present embodiment differs from the first embodiment shown in FIG. 1 in that the shape of a counterbore with a taper angle is different. That is, a counterbore facing outward is inserted in the wedge-shaped shape of FIG. There is almost no difference from the wedge shape in the strength, and the process is simple, and the working time can be reduced.
【００１２】図３は、本発明の第３の実施の形態を示す
断面図である。本実施の形態の図２に示した第２の実施
の形態と相違する点は、テーパ角のついたザグリの向き
が反対に内側になっている点である。第２、第３の実施
の形態において、ザグリ角の基板表面とのなす角度は、
第１の実施の形態と同様に設定される。FIG. 3 is a sectional view showing a third embodiment of the present invention. The present embodiment is different from the second embodiment shown in FIG. 2 in that the direction of the counterbore having a taper angle is opposite to the inside. In the second and third embodiments, the angle formed by the counterbore angle with the substrate surface is:
The settings are made in the same manner as in the first embodiment.
【００１３】図４は、本発明の第１から第３の実施の形
態の半導体装置基板のザグリの位置を明確にするための
図である。前記ザグリの位置は、図４のようにザグリ１
１７と１１８あるいはザグリ１１９と１２２のように、
相対向する位置に形成してもよいし、ザグリ１１７〜１
２０のように半導体素子１０６を囲むようにその４辺に
形成してもよい。また、ザグリの形状は例えば飛び飛び
の穴状であってもよくあるいは連続した溝状であっても
よい。ザグリの位置と個数等の構成については、強度と
作業性の兼ね合いにより決定される。FIG. 4 is a view for clarifying the position of the spot on the semiconductor device substrate according to the first to third embodiments of the present invention. The position of the counterbore is counterbore 1 as shown in FIG.
Like 17 and 118 or counterbore 119 and 122,
It may be formed at a position facing each other, or the counterbore 117-1
The semiconductor device 106 may be formed on four sides thereof so as to surround the semiconductor device 106 as shown in FIG. Further, the shape of the counterbore may be, for example, a discrete hole shape or a continuous groove shape. The configuration such as the position and the number of the counterbores is determined based on a balance between strength and workability.
【００１４】図５は、本発明の第４の実施の形態を示す
断面図である。本実施の形態の図１から図３に示した実
施の形態と相違する点は、第３誘電体層１０３の基板面
方向にザグリを入れ、そこにポッティング樹脂１０５を
充填した点である。この方法によれば、ザグリを第２金
属層１１１の形成面に開設しないため、該第２金属層１
１１に形成するパターンの制約を回避でき、しかもボン
ディングパッドの搭載位置の制約がゆるくなるという利
点がある。FIG. 5 is a sectional view showing a fourth embodiment of the present invention. The difference between the present embodiment and the embodiment shown in FIGS. 1 to 3 is that a counterbore is formed in the third dielectric layer 103 in the substrate surface direction and the potting resin 105 is filled therein. According to this method, since the counterbore is not formed on the surface on which the second metal layer 111 is formed, the second metal layer 1
There is an advantage that the restrictions on the pattern formed on the substrate 11 can be avoided, and the restrictions on the mounting positions of the bonding pads are relaxed.
【００１５】図６は、本発明の第５の実施の形態を示す
断面図である。本実施の形態の図５に示した第４の実施
の形態と相違する点は、凹部を形成する過程で、逆テー
パ形に凹部を形成して、そこにポッティング樹脂１０５
を充填した点である。この方法によれば、図５の第４の
実施の形態で説明した利点以外に、基板面方向のザグリ
を省略でき、工程的に有利となる。FIG. 6 is a sectional view showing a fifth embodiment of the present invention. The present embodiment is different from the fourth embodiment shown in FIG. 5 in that, in the process of forming the concave portion, a concave portion is formed in an inversely tapered shape, and the potting resin 105 is formed there.
Is filled. According to this method, besides the advantages described in the fourth embodiment of FIG. 5, the counterbore in the substrate surface direction can be omitted, which is advantageous in the process.
【００１６】図７、図８は、それぞれ本発明の第６、第
７の実施の形態を示す断面図である。本実施の形態の図
５に示した第４の実施の形態と相違する点は、第３誘電
体層１０３、第２誘電体層１０２に入れたザグリの断面
形状が三角形になっている点である。これら第４、第
６、第７の実施の形態を組み合わせて、凹部の一側面に
複数のザグリを入れるようにすることができる。なお、
第４〜第７の実施の形態においても、ザグリを飛び飛び
に穴状に形成するようにしてもよく、また溝状に連続し
て形成するようにしてもよい。また、これらの実施の形
態においても、ザグリは、凹部の相対向する２つの側面
または４つの側面に入れることができる。FIGS. 7 and 8 are cross-sectional views showing sixth and seventh embodiments of the present invention, respectively. The present embodiment is different from the fourth embodiment shown in FIG. 5 in that the cross section of the counterbore in the third dielectric layer 103 and the second dielectric layer 102 is triangular. is there. By combining these fourth, sixth, and seventh embodiments, a plurality of counterbores can be inserted into one side surface of the concave portion. In addition,
Also in the fourth to seventh embodiments, the counterbore may be formed in a hole shape at intervals, or may be formed continuously in a groove shape. Also in these embodiments, the counterbore can be placed on two or four opposite sides of the recess.
【００１７】以上好ましい実施の形態について説明した
が、本発明は、これら実施の形態に限定されるものでは
なく、本発明の要旨を変更しない範囲内において適宜の
変更が可能なものである。例えば、実施の形態では、凹
部や凹部内の切り込みはザグリによって形成していた
が、必ずしもこのようにする必要はなく、多層配線基板
をモールド法などにより形成してもよい。また、本発明
は、樹脂製基板に対しても無機製の配線基板に対しても
適用が可能なものである。また、樹脂と基板との密着強
度を一層向上させるために、凹部の底面に形成した切り
込みと側面に形成した切り込みとを併用することもでき
る。Although the preferred embodiments have been described above, the present invention is not limited to these embodiments, and appropriate changes can be made without departing from the gist of the present invention. For example, in the embodiment, the recesses and the cuts in the recesses are formed by counterbores. However, it is not always necessary to do so, and the multilayer wiring board may be formed by a molding method or the like. Further, the present invention can be applied to a resin substrate and an inorganic wiring substrate. Further, in order to further improve the adhesion strength between the resin and the substrate, the cut formed on the bottom surface of the concave portion and the cut formed on the side surface can be used in combination.
【００１８】[0018]
【発明の効果】以上説明したように、本発明の半導体装
置は、半導体素子を搭載し、ポッティング樹脂を充填す
る凹部に切り込みを設けたものであるので、基板とポッ
ティング樹脂との間の密着性を向上させることができ
る。従って、本発明によれば、はんだ等の接着剤のリフ
ロー時に基板と半導体素子の間のはんだ等の接着剤に含
まれる空気が膨張しようとしても、ポッティング樹脂は
この膨張圧力に抗してこれを押さえ込むことができる。
そのため、ポッティング樹脂および半導体素子の基板か
らの剥離を防止することができる。As described above, the semiconductor device of the present invention has a semiconductor element mounted thereon and a notch provided in a concave portion for filling the potting resin, so that the adhesion between the substrate and the potting resin is improved. Can be improved. Therefore, according to the present invention, even when the air contained in the adhesive such as solder between the substrate and the semiconductor element attempts to expand at the time of reflow of the adhesive such as solder, the potting resin resists the expansion pressure against the expansion pressure. Can be held down.
Therefore, peeling of the potting resin and the semiconductor element from the substrate can be prevented.
【図１】 本発明の第１の実施の形態を説明するための
半導体装置基板の断面図。FIG. 1 is a sectional view of a semiconductor device substrate for explaining a first embodiment of the present invention.
【図２】 本発明の第２の実施の形態を説明するための
半導体装置基板の断面図。FIG. 2 is a cross-sectional view of a semiconductor device substrate for illustrating a second embodiment of the present invention.
【図３】 本発明の第３の実施の形態を説明するための
半導体装置基板の断面図。FIG. 3 is a cross-sectional view of a semiconductor device substrate for describing a third embodiment of the present invention.
【図４】 本発明の第１から第３の実施の形態のザグリ
の配置を表す図。FIG. 4 is a diagram showing an arrangement of a counterbore according to the first to third embodiments of the present invention.
【図５】 本発明の第４の実施の形態を説明するための
半導体装置基板の断面図。FIG. 5 is a cross-sectional view of a semiconductor device substrate for illustrating a fourth embodiment of the present invention.
【図６】 本発明の第５の実施の形態を説明するための
半導体装置基板の断面図。FIG. 6 is a sectional view of a semiconductor device substrate for describing a fifth embodiment of the present invention.
【図７】 本発明の第６の実施の形態を説明するための
半導体装置基板の断面図。FIG. 7 is a cross-sectional view of a semiconductor device substrate for illustrating a sixth embodiment of the present invention.
【図８】 本発明の第７の実施の形態を説明するための
半導体装置基板の断面図。FIG. 8 is a sectional view of a semiconductor device substrate for illustrating a seventh embodiment of the present invention.
【図９】 従来の多層配線基板の斜視図。FIG. 9 is a perspective view of a conventional multilayer wiring board.
【図１０】 従来例の断面図。FIG. 10 is a sectional view of a conventional example.
１０１、２０１ 第１誘電体層 １０２、２０２ 第２誘電体層 １０３、２０３ 第３誘電体層 １０４、２０４ ボンディングワイヤ １０５、２０５ ポッティング樹脂 １０６、２０６ 半導体素子 １０７、２０７ 接着剤 １０８、２０８ 凹部 １１０、２１０ 第１金属層 １１１、２１１ 第２金属層 １１２、２１２ 第３金属層 １１３、２１３ 第４金属層 １１４、１１５、１１６、１１７、１１８、１１９、１
２０、１２１、１２２テーパ角のついたザグリ101, 201 first dielectric layer 102, 202 second dielectric layer 103, 203 third dielectric layer 104, 204 bonding wire 105, 205 potting resin 106, 206 semiconductor element 107, 207 adhesive 108, 208 recess 110 210 First metal layer 111, 211 Second metal layer 112, 212 Third metal layer 113, 213 Fourth metal layer 114, 115, 116, 117, 118, 119, 1
20, 121, 122 Counterbore with taper angle
Claims (8)
樹脂にて封止された半導体素子が搭載されている半導体
装置において、前記凹部の底面、および／または、側面
には前記封止樹脂の剥離を防止する切り込みが形成され
ていることを特徴とする半導体装置。1. A semiconductor device in which a semiconductor element sealed with a sealing resin is mounted in a recess formed in a multilayer wiring board, wherein the bottom and / or the side surface of the recess is provided with the sealing. A semiconductor device having a cut formed to prevent resin peeling.
素子の対向する２辺を挟むように前記半導体素子に対し
対称的に形成されていることを特徴とする請求項１記載
の半導体装置。2. The semiconductor device according to claim 1, wherein the cut is formed symmetrically with respect to the semiconductor element so as to sandwich at least two opposing sides of the semiconductor element.
沿って連続的に若しくは不連続的に形成されていること
を特徴とする請求項１または２記載の半導体装置。3. The semiconductor device according to claim 1, wherein the cut is formed continuously or discontinuously along a side of the semiconductor element.
みの断面形状は、四角形または三角形であることを特徴
とする請求項１〜３の何れかに記載の半導体装置。4. The semiconductor device according to claim 1, wherein a cross-section of a cut formed in said side surface of said recess is a quadrangle or a triangle.
みの断面形状は、三角形であって該切り込みは前記凹部
の側面の全深さに渡って形成されていることを特徴とす
る請求項１〜３の何れかに記載の半導体装置。5. A cross section of a cut formed on the side surface of the recess is triangular, and the cut is formed over the entire depth of the side surface of the recess. 4. The semiconductor device according to any one of claims 3 to 3.
搭載する半導体素子搭載部とワイヤがボンディングされ
るボンディングパッドとが形成されており、前記凹部底
面に形成された前記切り込みが、前記半導体素子搭載部
と前記ボンディングパッドとの間に形成されていること
を特徴とする請求項１〜３の何れかに記載の半導体装
置。6. A semiconductor element mounting portion for mounting the semiconductor element and a bonding pad to which a wire is bonded are formed on a bottom surface of the concave portion, and the notch formed on the bottom surface of the concave portion is formed by the semiconductor. 4. The semiconductor device according to claim 1, wherein the semiconductor device is formed between an element mounting portion and the bonding pad.
みの基板表面とのなす角度θは、４５°≦θ＜９０°ま
たは９０°＜θ≦１３５°であることを特徴とする請求
項１〜３または６の何れかに記載の半導体装置。7. An angle θ between the cut surface formed on the bottom surface of the concave portion and the substrate surface is 45 ° ≦ θ <90 ° or 90 ° <θ ≦ 135 °. 7. The semiconductor device according to any one of items 3 to 6.
成されたものであることを特徴とする請求項１〜７の何
れかに記載の半導体装置。8. The semiconductor device according to claim 1, wherein the cut is formed by counterboring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000104339A JP2001291792A (en) | 2000-04-06 | 2000-04-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000104339A JP2001291792A (en) | 2000-04-06 | 2000-04-06 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001291792A true JP2001291792A (en) | 2001-10-19 |
Family
ID=18617897
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000104339A Pending JP2001291792A (en) | 2000-04-06 | 2000-04-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001291792A (en) |
Cited By (6)
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|---|---|---|---|---|
| JP2008192413A (en) * | 2007-02-02 | 2008-08-21 | Nec Tokin Corp | Protection circuit module |
| US7700885B2 (en) | 2005-04-25 | 2010-04-20 | Ngk Spark Plug Co., Ltd. | Wiring board |
| EP2190040A2 (en) * | 2008-11-25 | 2010-05-26 | VisEra Technologies Company Limited | Light-emitting diode device and method for fabricating the same |
| JP2013077739A (en) * | 2011-09-30 | 2013-04-25 | Kyocera Corp | Wiring board, electronic device provided with the wiring board, and electronic module device |
| KR101829936B1 (en) * | 2013-05-22 | 2018-02-19 | 삼성전기주식회사 | Semiconductor package and manufacturing method threrof |
| JP2019046932A (en) * | 2017-08-31 | 2019-03-22 | 日亜化学工業株式会社 | Light-emitting device and manufacturing method thereof |
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