JPH0878457A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0878457A
JPH0878457A JP20780194A JP20780194A JPH0878457A JP H0878457 A JPH0878457 A JP H0878457A JP 20780194 A JP20780194 A JP 20780194A JP 20780194 A JP20780194 A JP 20780194A JP H0878457 A JPH0878457 A JP H0878457A
Authority
JP
Japan
Prior art keywords
conductor
plating
wire
solder resist
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20780194A
Other languages
Japanese (ja)
Other versions
JP3007800B2 (en
Inventor
Toshiaki Maeda
敏明 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP20780194A priority Critical patent/JP3007800B2/en
Publication of JPH0878457A publication Critical patent/JPH0878457A/en
Application granted granted Critical
Publication of JP3007800B2 publication Critical patent/JP3007800B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Abstract

PURPOSE: To enable improving connection strength of wire bonding. CONSTITUTION: In an optical coupler 35, when plating is performed on a substrate 36, a solder resist film is formed before the uppermost plating later is formed, and a surface solid plating wiring is formed on a region which is previously decided. Thereby the surface of the uppermost plating layer is not contaminated by gas generated when the solder resist film is cured, and strength is improved when a light emitting element 42 and a light receiving element 43 which are arranged in the recessed parts 38, 39 of the substrate 36 are wire bonded with the plating layer by using lead wires.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、光半導体装置などの半
導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device such as an optical semiconductor device.

【0002】[0002]

【従来の技術】図28は、従来の技術に基づく光結合装
置21の製造工程の順序を示す図である。光結合装置2
1は、MID(Molded Interconnection Device)であ
り、このMIDは、熱可塑性材料などによって形成され
る基体1にめっきを行って形成され、従来の電子部品で
使用されているリードフレームや端子などの金属部品を
省略し、部品設計の自由度を大幅に向上させ、また、部
品の信頼性を向上させたものである。
2. Description of the Related Art FIG. 28 is a diagram showing a sequence of steps for manufacturing an optical coupling device 21 based on a conventional technique. Optical coupling device 2
Reference numeral 1 denotes a MID (Molded Interconnection Device), which is formed by plating a base body 1 formed of a thermoplastic material or the like, and is used in conventional electronic components such as lead frames and terminals such as terminals. By omitting parts, the degree of freedom in part design is greatly improved, and the reliability of parts is improved.

【0003】図28(1)に示す工程では、成型体であ
る基体1が成型される。基体1は、高耐熱性の合成樹脂
など、たとえば液晶ポリマによって、図28の紙面に垂
直方向に、仕切り壁2を隔てて一対の凹所3が存在する
ように形成される。光結合装置21は、仕切り壁2を隔
てた一方の凹所3に発光素子11(後述の図28(8)
参照)を配置し、図示しない他方の凹所には受光素子が
発光素子11と同様に配置される。以後の説明は、発光
素子11についてのみ行うが、受光素子についても同様
の工程が行われる。次に図28(2)に示す工程では、
基体1にフォトレジスト等の回路形成用レジスト4a,
4b,4cによって配線を行わないところをマスクして
いる。
In the step shown in FIG. 28 (1), the base body 1 which is a molded body is molded. The base 1 is formed of a highly heat-resistant synthetic resin or the like, for example, a liquid crystal polymer so that a pair of recesses 3 are formed in the direction perpendicular to the paper surface of FIG. The optical coupling device 21 includes a light emitting element 11 (see FIG. 28 (8) described later) in one recess 3 that separates the partition wall 2.
(Refer to FIG. 3), and the light receiving element is arranged in the other recess not shown in the same manner as the light emitting element 11. Although the following description will be given only for the light emitting element 11, the same steps are performed for the light receiving element. Next, in the step shown in FIG. 28 (2),
A circuit forming resist 4a such as a photoresist is formed on the substrate 1.
The areas where wiring is not performed are masked by 4b and 4c.

【0004】次の図28(3)の工程では、基体1にお
いて回路形成用レジスト4a,4b,4cによってマス
クされていない領域に、銅、ニッケルなどによってめっ
き層が形成され、下地立体めっき配線5,6となる。下
地立体めっき層の形成が終了すると、図28(4)に示
す工程において回路形成用レジスト4a,4b,4cを
剥離し、除去する。
In the next step of FIG. 28 (3), a plating layer is formed of copper, nickel or the like on the area of the substrate 1 which is not masked by the circuit forming resists 4a, 4b and 4c, and the three-dimensional base plating wiring 5 is formed. , 6. When the formation of the underlying solid plating layer is completed, the circuit forming resists 4a, 4b, 4c are peeled and removed in the step shown in FIG. 28 (4).

【0005】図28(5)に示す工程では、金、銀など
を用いて、表面立体めっきが行われ、下地立体めっき配
線5,6の表面に金または銀によるめっき層が形成さ
れ、表面立体めっき配線7,8となる。表面立体めっき
が行われた基体1に対して、図28(6)に示す工程で
は、光漏れを防ぐために用いられる後述する保護用透光
性合成樹脂の流出を防止したり、また光結合装置を配線
基板に半田を用いて実装するときに、半田によって電極
となるめっき領域部分7a,8aがショートすることを
防止するために、ソルダレジスト膜9,10が塗布され
る。
In the step shown in FIG. 28 (5), surface three-dimensional plating is performed using gold, silver or the like to form a plated layer of gold or silver on the surfaces of the underlying three-dimensional plated wirings 5 and 6. The plated wirings 7 and 8 are formed. In the step shown in FIG. 28 (6), the protective translucent synthetic resin, which will be described later, used for preventing light leakage is prevented from flowing out from the substrate 1 on which the surface three-dimensional plating has been performed, and the optical coupling device is used. Solder resist films 9 and 10 are applied to prevent the plating area portions 7a and 8a serving as electrodes from being short-circuited by the solder when the wiring board is mounted on the wiring board using solder.

【0006】ソルダレジスト膜9,10は、エポキシ
系、フェノール系などの合成樹脂をシルクスクリーン印
刷することによって形成されており、前記合成樹脂は硬
化する際にガスを発生する。
The solder resist films 9 and 10 are formed by silk-screen printing a synthetic resin such as an epoxy resin or a phenol resin, and the synthetic resin generates a gas when it is cured.

【0007】ソルダレジスト膜9,10の硬化の際に発
生するガスについて説明する。ソルダレジスト膜9,1
0がフェノール系の合成樹脂から成る場合、フェノール
の硬化反応は脱水縮合反応であるので反応時には水が揮
発する。その他に低分子量のフェノール成分、残留ホル
マリン成分の揮発がある。また、前記合成樹脂の粘度を
調整するために、溶剤の成分がたとえばブチルカルビト
ールである有機溶剤を用いているので、硬化する際に前
記有機溶剤成分が揮発する。ソルダレジスト膜9,10
がエポキシ系の合成樹脂から成る場合、前記合成樹脂の
粘度を調整するとき、有機溶剤を使用する合成樹脂と反
応性モノマーを使用する合成樹脂とがある。有機溶剤を
用いて粘度を調整する合成樹脂が硬化する際には、前述
したフェノール系の合成樹脂から成る場合と同様に、有
機溶剤の成分が揮発する。反応性モノマーを用いて粘度
を調整する合成樹脂が硬化する際には、反応性モノマー
の構造がエポキシ樹脂とほぼ同一で分子量が小さいため
に、熱がかかることによって反応性モノマーが若干揮発
する。
The gas generated when the solder resist films 9 and 10 are cured will be described. Solder resist film 9,1
When 0 is composed of a phenolic synthetic resin, the curing reaction of phenol is a dehydration condensation reaction, so that water volatilizes during the reaction. In addition, there is volatilization of low molecular weight phenol components and residual formalin components. Further, since an organic solvent whose solvent component is, for example, butyl carbitol is used to adjust the viscosity of the synthetic resin, the organic solvent component is volatilized during curing. Solder resist film 9, 10
When is composed of an epoxy-based synthetic resin, when adjusting the viscosity of the synthetic resin, there are a synthetic resin using an organic solvent and a synthetic resin using a reactive monomer. When the synthetic resin whose viscosity is adjusted by using the organic solvent is cured, the components of the organic solvent are volatilized as in the case of using the phenolic synthetic resin described above. When the synthetic resin whose viscosity is adjusted by using the reactive monomer is cured, the reactive monomer has a structure similar to that of the epoxy resin and a small molecular weight, so that the reactive monomer is slightly volatilized by applying heat.

【0008】上述のように発生するガスがめっき表面に
付着すると、めっき表面が汚損され後述するワイヤボン
ディングの接続強度に悪影響を及ぼす。この問題を解決
するために、めっき表面の汚れを除去し、光結合装置の
品質を安定させるために、図28(7)に示す工程にお
いて表面立体めっき配線7,8の表面を硫酸などを用い
て洗浄している。
If the gas generated as described above adheres to the plating surface, the plating surface is contaminated and the connection strength of wire bonding described later is adversely affected. In order to solve this problem, in order to remove stains on the plated surface and stabilize the quality of the optical coupling device, sulfuric acid or the like is used on the surface of the surface three-dimensional plated wirings 7 and 8 in the step shown in FIG. 28 (7). Are washing.

【0009】図28(8)に示す工程では、仕切り壁2
を隔てた一方の凹所3に、発光素子11を導電性の接着
剤を用いて予め定められた位置に配置する。発光素子1
1および受光素子は、基体1の凹所に仕切り壁を隔てて
配置されるので、光が漏れることによって起こる受光素
子の誤動作を防止することができる。また凹所にあるた
め、各素子が直接、外力を受けることが少なくなる。図
28(9)に示す工程において、基体1の一方の凹所3
に配置された発光素子11と表面めっき配線8とを導線
12によって接続する。導線12には、金などの導線が
用いられる。
In the step shown in FIG. 28 (8), the partition wall 2 is
The light emitting element 11 is arranged at a predetermined position in one of the recesses 3 separated by using a conductive adhesive. Light emitting element 1
Since 1 and the light receiving element are arranged in the recess of the base body 1 with the partition wall therebetween, it is possible to prevent malfunction of the light receiving element caused by light leakage. In addition, since the recesses are provided, each element is less likely to receive an external force directly. In the step shown in FIG. 28 (9), one recess 3 of the base 1
The light emitting element 11 arranged in the above and the surface plated wiring 8 are connected by the conductive wire 12. A conductive wire such as gold is used for the conductive wire 12.

【0010】ワイヤボンディング終了後、図28(1
0)に示す工程において、基体1の凹所は発光素子11
を保護するための透光性合成樹脂から成る封止材13に
よって封止される。
After the wire bonding is completed, as shown in FIG.
In the step shown in 0), the recess of the base 1 is the light emitting element 11
It is sealed by a sealing material 13 made of a translucent synthetic resin for protecting.

【0011】[0011]

【発明が解決しようとする課題】上述のような光結合装
置21の製造方法では、金、銀などを用いて表面立体め
っき配線7,8を施した後、封止材13の流出防止、お
よび光結合装置21を基板に半田を用いて実装するとき
に半田によってめっき領域部分7a,8a同士がショー
トすることの防止等を目的として、ソルダレジスト膜
9,10を基体1の側面に設けられる実装用電極以外の
基体1表面に形成するので、樹脂が硬化する際に発生す
るガス等によってめっき表面に汚れが付着し、導線12
とめっき表面の接続部に接続不良が発生するおそれがあ
る。めっき表面の汚れを取除くために、光結合装置21
の製造工程において洗浄を行っているが、多数の装置を
洗浄することによる洗浄剤自身の汚れや、洗浄性のばら
つき等によって汚れが完全に除去されず、ワイヤボンデ
ィング強度が低下するという問題点がある。
In the method of manufacturing the optical coupling device 21 as described above, after the surface three-dimensional plated wirings 7 and 8 are formed using gold, silver or the like, the sealing material 13 is prevented from flowing out, and When the optical coupling device 21 is mounted on the substrate using solder, the solder resist films 9 and 10 are provided on the side surface of the base 1 for the purpose of preventing the plating region portions 7a and 8a from being short-circuited by the solder. Since it is formed on the surface of the substrate 1 other than the electrodes for the electrodes, dirt is attached to the surface of the plating by the gas generated when the resin is cured, and the conductor 12
There is a possibility that connection failure may occur at the connection part on the plating surface. Optical coupling device 21 to remove stains on the plating surface
Although the cleaning is performed in the manufacturing process of the above, there is a problem that the cleaning agent itself is contaminated by cleaning a large number of devices and the contamination is not completely removed due to variations in cleaning property, and the wire bonding strength is reduced. is there.

【0012】本発明の目的は、ワイヤボンディング強度
を向上させ、品質の向上を図るとともに、立体めっき配
線表面の洗浄工程を削除することができるようにした半
導体装置の製造方法を提供することである。
An object of the present invention is to provide a method of manufacturing a semiconductor device, which is capable of improving wire bonding strength and quality, and eliminating the step of cleaning the surface of a three-dimensional plated wiring. .

【0013】[0013]

【課題を解決するための手段】本発明は、合成樹脂製基
体上に複数層から成る導体をめっきによって形成し、基
体または導体の予め定める領域にソルダレジスト膜を形
成し、半導体素子と前記導体とを導線によってワイヤボ
ンディングする半導体装置の製造方法において、前記複
数層のうち少なくとも最も上の層を、めっきによって形
成する前に、ソルダレジスト膜を形成することを特徴と
する半導体装置の製造方法である。また本発明は、仕切
り壁を隔てて隣接する一対の凹所を有する合成樹脂製基
体を成形し、基体の各凹所の内周面と、基体の外周面と
にわたって複数層の導体をめっきによって形成し、前記
複数層のうち少なくとも最も上の層を、めっきによって
形成する前に、前記仕切り壁の端面を含む基体または導
体の予め定める領域にソルダレジスト膜を形成し、導体
の最も上の層を形成した後に、一方の凹所内で発光のた
めの半導体素子と導体とを導線によってワイヤボンディ
ングするとともに、他方の凹所内で受光のための半導体
素子と導体とを導線によってワイヤボンディングし、各
凹所内に透光性合成樹脂を充填することを特徴とする光
半導体装置の製造方法である。
According to the present invention, a conductor consisting of a plurality of layers is formed on a synthetic resin substrate by plating, and a solder resist film is formed on a predetermined region of the substrate or the conductor to form a semiconductor element and the conductor. In a method for manufacturing a semiconductor device in which wire bonding is performed with a conductive wire, a solder resist film is formed before forming at least the uppermost layer of the plurality of layers by plating. is there. Further, the present invention forms a synthetic resin base having a pair of recesses adjacent to each other with a partition wall therebetween, and plating a plurality of layers of conductors on the inner peripheral surface of each recess of the base and the outer peripheral surface of the base. Before forming at least the uppermost layer of the plurality of layers by plating, a solder resist film is formed on a predetermined region of the base or conductor including the end face of the partition wall, and the uppermost layer of the conductor is formed. After forming, the semiconductor element for emitting light and the conductor are wire-bonded with a conductor in one recess, and the semiconductor element for receiving light and the conductor are wire-bonded with a conductor in the other recess, and each recess is formed. A method for manufacturing an optical semiconductor device is characterized in that a transparent synthetic resin is filled in the place.

【0014】[0014]

【作用】本発明に従えば、半導体装置は、合成樹脂製基
体上に複数層から成る導体をめっきによって形成する際
に、複数層のうち、少なくとも最も上の層をめっきによ
って形成する前に、基体または導体の予め定める領域に
ソルダレジスト膜を形成し、半導体素子と前記導体とを
導線によってワイヤボンディングする。したがって、硬
化する際にガスを発生してめっき表面を汚す原因となる
ソルダレジスト膜を形成した後に、さらに少なくとも最
も上のめっき層を形成するので、最も上のめっき層の表
面に汚れが付着することがない。また最も上のめっき層
の表面に汚れが付着しないので、洗浄工程を設ける必要
がなくなる。
According to the present invention, in the semiconductor device, when the conductor made of a plurality of layers is formed on the synthetic resin substrate by plating, at least the uppermost layer of the plurality of layers is formed by the plating. A solder resist film is formed on a predetermined area of the base or conductor, and the semiconductor element and the conductor are wire-bonded by a conductive wire. Therefore, since at least the uppermost plating layer is formed after forming the solder resist film that causes gas to be generated during curing and stains the plating surface, dirt adheres to the surface of the uppermost plating layer. Never. Further, since the surface of the uppermost plating layer is not contaminated, it is not necessary to provide a cleaning step.

【0015】また本発明に従えば、光半導体装置の合成
樹脂製基体を、一対の凹所が仕切り壁を隔てて隣接する
ように成形し、基体の各凹所の内周面と、基体の外周面
とにわたって複数層の導体をめっきによって形成し、導
体を形成する複数層のうち、少なくとも最も上の層をめ
っきによって形成する前に、仕切り壁の端面を含む基体
または導体の予め定める領域にソルダレジスト膜を形成
し、最も上の層を形成した後に、基体の各凹所内で受光
および発光のための各半導体素子と導体とをそれぞれ導
線によってワイヤボンディングし、各凹所内に透光性合
成樹脂を充填して製造される。
Further, according to the present invention, the synthetic resin substrate of the optical semiconductor device is molded so that the pair of recesses are adjacent to each other with the partition wall interposed therebetween, and the inner peripheral surface of each recess of the substrate and the base A plurality of layers of conductors are formed over the outer peripheral surface by plating, and before forming at least the uppermost layer of the plurality of layers forming the conductors by plating, in a predetermined area of the base or conductor including the end surface of the partition wall. After forming the solder resist film and forming the uppermost layer, each semiconductor element for receiving and emitting light and each conductor are wire-bonded in the respective recesses of the substrate with conductive wires, and the transparent composite is formed in each recess. It is manufactured by filling with resin.

【0016】したがって、硬化する際にガスを発生して
最も上のめっき層の表面を汚す原因となるソルダレジス
ト膜を、仕切り壁の端面を含む基体または導体の予め定
める領域に形成した後、さらにめっきを行い、最も上の
めっき層を形成し、その後に基体の各凹所内で、受光お
よび発光のための各半導体素子と導体とをそれぞれ導線
によってワイヤボンディングしているので、最も上のめ
っき層の表面が汚れておらず、ワイヤボンディング強度
が向上する。また最も上のめっき層の表面に汚れが付着
しないので、洗浄工程を設ける必要がなくなる。
Therefore, after forming a solder resist film, which causes gas during curing to stain the surface of the uppermost plating layer, in a predetermined region of the substrate or conductor including the end face of the partition wall, Plating is performed to form the uppermost plating layer, and thereafter, in each recess of the substrate, each semiconductor element for receiving light and emitting light and each conductor are wire-bonded by a conductor wire, so the uppermost plating layer The surface of is clean and the wire bonding strength is improved. Further, since the surface of the uppermost plating layer is not contaminated, it is not necessary to provide a cleaning step.

【0017】[0017]

【実施例】図1は本発明の第1実施例である光結合装置
35を一方側から見た斜視図であり、図2はその光結合
装置35を他方側から見た斜視図である。光結合装置3
5は、前述したMIDである。光結合装置35は、遮光
性合成樹脂材料など、たとえば液晶ポリマから成る基体
36を有し、この基体36には、仕切り壁37を隔てて
一対の凹所38,39が隣接して形成される。この基体
36は、射出成型によって製造される。各凹所38,3
9の底40,41には、半導体素子である発光素子42
と受光素子43とが配置される。発光素子42からの光
は、被検出物体に照射され、その反射光が受光素子43
で受光され、検出される。基体36は、凹所38,39
を形成するために一対の端壁44,45と、一対の側壁
46,47とを有し、側壁46,47の長手方向の中央
位置で仕切り壁37が設けられる。凹所38,39に
は、図1において点線の斜線で示されるように、透光性
合成樹脂、たとえばエポキシなどから成る封止材79が
充填されて各半導体素子42,43を保護する。
1 is a perspective view of an optical coupling device 35 according to a first embodiment of the present invention viewed from one side, and FIG. 2 is a perspective view of the optical coupling device 35 viewed from the other side. Optical coupling device 3
5 is the above-mentioned MID. The optical coupling device 35 has a base 36 made of, for example, a liquid crystal polymer such as a light-shielding synthetic resin material, and a pair of recesses 38 and 39 are formed adjacent to the base 36 with a partition wall 37 therebetween. . The base 36 is manufactured by injection molding. Each recess 38,3
The bottoms 40 and 41 of the light emitting element 42 are semiconductor elements.
And the light receiving element 43 are arranged. The light from the light emitting element 42 is applied to the object to be detected, and the reflected light thereof is received by the light receiving element 43.
The light is received and detected by. The base 36 has recesses 38, 39.
Has a pair of end walls 44 and 45 and a pair of side walls 46 and 47, and the partition wall 37 is provided at the central position in the longitudinal direction of the side walls 46 and 47. As shown by the dotted diagonal lines in FIG. 1, the recesses 38 and 39 are filled with a sealing material 79 made of a translucent synthetic resin, such as epoxy, to protect the semiconductor elements 42 and 43.

【0018】基体36は、たとえば長さL1=4mm、
幅L2=3mm、高さH=1mmであるように形成され
る。発光素子42と受光素子43とに電気的に接続され
る導体48,49;50,51は、基体36の底面52
の参照符53,54;55,56に延び、後述の図12
に示される配線基板57の導体58,59に半田60,
61によって半田付けされる。
The base 36 has, for example, a length L1 = 4 mm,
The width L2 is 3 mm and the height H is 1 mm. The conductors 48, 49; 50, 51 electrically connected to the light emitting element 42 and the light receiving element 43 are the bottom surface 52 of the base 36.
12 of the drawings 53, 54;
To the conductors 58 and 59 of the wiring board 57 shown in FIG.
Soldered by 61.

【0019】図3〜図11にそれぞれ示される断面図を
参照して、光結合装置35の製造工程順序を説明する。
以下の各工程についての説明は、主として発光素子42
に関連して行われるけれども、受光素子43に関しても
同様の工程が行われる。
The manufacturing process sequence of the optical coupling device 35 will be described with reference to the sectional views shown in FIGS.
The description of each of the following steps will be mainly given to the light emitting element 42.
However, the same steps are performed for the light receiving element 43 as well.

【0020】図3に示されるように、基体36が射出成
型によって製造された後、図4では、フォトレジストが
シルクスクリーン印刷によって、凹所38の底40と、
仕切り壁37の端面58と、底52とに、参照符87,
88,89に示されように形成される。次に、無電解め
っきまたは電解めっきの手法で、銅、またはニッケルな
どのように比較的安価であり、かつ基体36に大きな密
着強度で付着する材料から成る下地めっき層71,72
を、図5に示されるように凹所38の底40と、側壁4
6,47の内側面62,63と、その側壁46,47の
端面64,65と、側壁46,47の外側面66,67
と、底面52とにそれぞれ形成する。凹所38の底40
と内側面62,63とは、凹所38の内周面を構成し、
また外側面66,67と底面52とは、基体36の外周
面を構成する。
After the substrate 36 has been manufactured by injection molding, as shown in FIG. 3, in FIG. 4 the photoresist is silk screen printed to the bottom 40 of the recess 38,
On the end surface 58 of the partition wall 37 and the bottom 52, reference numerals 87,
Formed as shown at 88,89. Next, the electroless plating or electrolytic plating technique is used to form the base plating layers 71 and 72 made of a material such as copper or nickel which is relatively inexpensive and adheres to the base 36 with high adhesion strength.
The bottom 40 of the recess 38 and the side wall 4 as shown in FIG.
6, 47 inner side surfaces 62, 63, their side walls 46, 47 end surfaces 64, 65, and side wall 46, 47 outer side surfaces 66, 67.
And the bottom surface 52. Bottom 40 of recess 38
And the inner side surfaces 62 and 63 form the inner peripheral surface of the recess 38,
The outer side surfaces 66, 67 and the bottom surface 52 form the outer peripheral surface of the base body 36.

【0021】めっき層形成後、図6に示すようにフォト
レジスト87,88,89を除去する。次に図7に示さ
れるように、ソルダレジスト膜を、図1において実線の
斜線で示す領域には参照符69で示されるように、また
図2の実線の斜線で示す領域、すなわち底面52には参
照符70で示されるように、シルクスクリーン印刷など
の手法で印刷して塗布する。このソルダレジスト膜6
9,70は、たとえばエポキシ系、フェノール系などの
材料から成る。そのためソルダレジスト膜69,70
は、半田が付着せずに、いわば弾く性質を有し、かつ凹
所38,39に充填される透光性合成樹脂材料が付着せ
ずに、弾く性質を有する。
After the plating layer is formed, the photoresists 87, 88 and 89 are removed as shown in FIG. Next, as shown in FIG. 7, a solder resist film is formed on the region shown by solid line diagonal lines in FIG. 1 as indicated by reference numeral 69, and on the region shown by solid line diagonal lines in FIG. Is applied by printing by a technique such as silk screen printing, as indicated by reference numeral 70. This solder resist film 6
9 and 70 are made of, for example, an epoxy-based material, a phenol-based material, or the like. Therefore, the solder resist films 69, 70
Has a so-called repelling property without solder attached, and has a repelling property without the translucent synthetic resin material filling the recesses 38 and 39 attached.

【0022】そこで次に図8に示されるように、無電解
めっきまたは電解めっきによって、下地めっき層71,
72上に、最も上のめっき層73,74を形成して、図
1に示した導体48,49を形成する。この最も上のめ
っき層73,74は、側壁46,47の端面64,65
上の下地めっき層71,72上には選択的に形成されな
い。したがって図1の実線の斜線を施して示す領域は、
前述のように、ソルダレジスト膜69が残存している。
めっき層73,74は、たとえば金、銀などの導電性が
良好な材料から成り、大気などの耐食性に優れており、
しかもワイヤボンディングの密着強度が大きい材料から
成る。こうして最も上のめっき層73,74は、ソルダ
レジスト膜69,70が付着せず、またソルダレジスト
膜69,70が原因となるめっき層73,74の汚損は
生じていない。さらにまた、これらのめっき層73,7
4は、下地めっき層71,72とは、大きな密着強度
で、電気的に接続された状態となっている。
Then, as shown in FIG. 8, the base plating layer 71,
The uppermost plating layers 73 and 74 are formed on 72, and the conductors 48 and 49 shown in FIG. 1 are formed. The uppermost plating layers 73, 74 are formed on the end faces 64, 65 of the side walls 46, 47.
It is not selectively formed on the upper base plating layers 71 and 72. Therefore, the shaded area shown by the solid line in FIG.
As described above, the solder resist film 69 remains.
The plating layers 73 and 74 are made of a material having good conductivity such as gold or silver, and have excellent corrosion resistance against the atmosphere,
Moreover, it is made of a material having a high adhesion strength for wire bonding. Thus, the solder resist films 69 and 70 are not attached to the uppermost plating layers 73 and 74, and the plating layers 73 and 74 are not contaminated due to the solder resist films 69 and 70. Furthermore, these plating layers 73, 7
No. 4 has a large adhesion strength with the base plating layers 71 and 72, and is in an electrically connected state.

【0023】次に図9に示されるように、導電性接着剤
75を用いて、半導体素子である発光素子42を凹所3
8の底40に形成されるめっき層73上に、電気的に接
続して固定する。その後、図10に示されるように、金
などの材料から成る導線76の一端部77を発光素子4
2にワイヤボンディングし、また他端部78を、もう1
つのめっき層74上にワイヤボンディングし、電気的に
接続する。
Next, as shown in FIG. 9, the light emitting element 42 which is a semiconductor element is formed in the recess 3 by using a conductive adhesive 75.
It is electrically connected and fixed on the plating layer 73 formed on the bottom 40 of No. 8. After that, as shown in FIG. 10, one end 77 of the conductive wire 76 made of a material such as gold is attached to the light emitting element 4.
2 and wire the other end 78 to the other
The two plated layers 74 are wire-bonded and electrically connected.

【0024】ワイヤボンディングを行った後、凹所38
内に、図11に示されるように透光性合成樹脂から成る
封止材79を充填し、発光素子42および導線76を保
護する。封止材79は、基体36の図1における点線の
斜線で示される端面に形成されており、ソルダレジスト
膜69によって封止材79がいわば弾かれて付着されな
いために、図1における仕切り壁37の上端面には、封
止材79が重ねられて存在することはない。そのため、
半導体素子である発光素子42から封止材79を経て半
導体素子である受光素子43に光が漏れることはなく、
これによって受光素子43が誤検出を生じることはな
い。
After wire bonding, the recess 38 is formed.
As shown in FIG. 11, a sealing material 79 made of translucent synthetic resin is filled inside to protect the light emitting element 42 and the conductive wire 76. The encapsulant 79 is formed on the end surface of the base 36 shown by the dotted diagonal lines in FIG. 1, and since the encapsulant 79 is repelled by the solder resist film 69, so to speak, and is not attached, the partition wall 37 in FIG. The sealing material 79 does not exist on the upper end surface of the sheet. for that reason,
Light does not leak from the light emitting element 42 which is a semiconductor element to the light receiving element 43 which is a semiconductor element through the sealing material 79.
As a result, the light receiving element 43 does not cause erroneous detection.

【0025】図12は、光結合装置35を配線基板57
上に配置した様子を示した図である。配線基板57は、
電気絶縁性基板22上に予め定められるパターンで導体
58,59が配線として設けられている。光結合装置3
5における導体53,54が、配線基板57上の導体5
8,59に半田60,61によってそれぞれ電気的に接
続される。
FIG. 12 shows the optical coupling device 35 and the wiring board 57.
It is the figure which showed the mode that it was arrange | positioned above. The wiring board 57 is
Conductors 58 and 59 are provided as wiring on the electrically insulating substrate 22 in a predetermined pattern. Optical coupling device 3
The conductors 53 and 54 in 5 are the conductors 5 on the wiring board 57.
It is electrically connected to 8 and 59 by solders 60 and 61, respectively.

【0026】ソルダレジスト膜70は、半田付けを行う
際に、半田60,61が溶解中に導体53と導体58も
しくは導体54と導体59の間に流れ込んで、導体5
3,58と導体54,59が電気的に接続されてしまう
のを防止している。
When soldering, the solder resist film 70 flows between the conductor 53 and the conductor 58 or between the conductor 54 and the conductor 59 while the solder 60 and 61 are being melted, so that the conductor 5
3, 58 and the conductors 54, 59 are prevented from being electrically connected.

【0027】図13は本発明の他の実施例である受光装
置91を一方側から見た斜視図であり、図14は受光装
置91を他方側から見た斜視図である。受光装置91に
おいて、前述の実施例の光結合装置35と同一の構成要
素には同一の参照符号を付して説明を省略する。受光装
置91において、基体36aは単一の凹所39を持つよ
うに形成される。基体36aの凹所39に形成されてい
る導体50の所定の位置に受光素子43が搭載されて、
導線76によって導体51と電気的に接続される。ワイ
ヤボンディングが終了すると、光結合装置35と同様に
凹所39が透光性合成樹脂から成る封止材79によって
封止される。
FIG. 13 is a perspective view of a light receiving device 91 according to another embodiment of the present invention viewed from one side, and FIG. 14 is a perspective view of the light receiving device 91 viewed from the other side. In the light receiving device 91, the same components as those of the optical coupling device 35 of the above-described embodiment are designated by the same reference numerals, and the description thereof will be omitted. In the light receiving device 91, the base body 36 a is formed to have a single recess 39. The light receiving element 43 is mounted at a predetermined position of the conductor 50 formed in the recess 39 of the base body 36a,
The conductor 76 electrically connects with the conductor 51. When the wire bonding is completed, the recess 39 is sealed with a sealing material 79 made of a translucent synthetic resin similarly to the optical coupling device 35.

【0028】図15は本発明のさらに他の実施例の発光
装置93を一方側から見た斜視図であり、図16は発光
装置93を他方側から見た斜視図である。発光装置93
において、前述の実施例の光結合装置35と同一の構成
要素には同一の参照符号を付して説明を省略する。発光
装置93において、基体36aは単一の凹所38を持つ
ように形成される。基体36aの凹所38に形成されて
いる導体48の所定の位置に発光素子42が搭載され
て、導線76によって導体49と電気的に接続される。
ワイヤボンディングが終了すると、光結合装置35と同
様に凹所38が透光性合成樹脂から成る封止材79によ
って封止される。
FIG. 15 is a perspective view of a light emitting device 93 of still another embodiment of the present invention viewed from one side, and FIG. 16 is a perspective view of the light emitting device 93 viewed from the other side. Light emitting device 93
In the above, the same components as those of the optical coupling device 35 of the above-described embodiment are designated by the same reference numerals and the description thereof will be omitted. In the light emitting device 93, the base 36a is formed to have a single recess 38. The light emitting element 42 is mounted at a predetermined position of the conductor 48 formed in the recess 38 of the base 36a, and is electrically connected to the conductor 49 by the conductor wire 76.
When the wire bonding is completed, the recess 38 is sealed with a sealing material 79 made of a translucent synthetic resin as in the optical coupling device 35.

【0029】図17は本発明のさらに他の実施例のレン
ズ付き受光装置95を一方側から見た斜視図であり、図
18はレンズ付き受光装置95を他方側から見た斜視図
である。レンズ付き受光装置95において、前述の実施
例の光結合装置35と同一の構成要素には同一の参照符
号を付して説明を省略する。レンズ付き受光装置95の
特徴は、集光のために大略的に半球状のレンズ96が設
けられていることである。レンズ96は、図17に示す
基体36aの上端面に固定される透光性の合成樹脂を材
料とする取付け板94上に固定される。
FIG. 17 is a perspective view of a light receiving device 95 with a lens according to still another embodiment of the present invention viewed from one side, and FIG. 18 is a perspective view of the light receiving device 95 with a lens viewed from the other side. In the light receiving device with lens 95, the same components as those of the optical coupling device 35 of the above-described embodiment are designated by the same reference numerals, and the description thereof will be omitted. The characteristic of the light receiving device with lens 95 is that a substantially hemispherical lens 96 is provided for condensing light. The lens 96 is fixed on a mounting plate 94 made of a translucent synthetic resin and fixed to the upper end surface of the base body 36a shown in FIG.

【0030】図19は本発明のさらに他の実施例である
レンズ付き発光装置97を一方側から見た斜視図であ
り、図20はレンズ付き発光装置97を他方側から見た
斜視図である。レンズ付き発光装置97において、前述
の実施例の光結合装置35と同一の構成要素には同一の
参照符号を付して説明を省略する。レンズ付き発光装置
97の特徴は、光を散乱するために大略的に半球状のレ
ンズ96が設けられていることである。レンズ96は、
レンズ付き受光装置97と同様に図19に示す基体36
aの上端面に固定される透光性の合成樹脂を材料とする
取付け板94上に固定される。
FIG. 19 is a perspective view of a light emitting device with lens 97 which is still another embodiment of the present invention as seen from one side, and FIG. 20 is a perspective view of the light emitting device with lens 97 as seen from the other side. . In the light emitting device with lens 97, the same components as those of the optical coupling device 35 of the above-described embodiment are designated by the same reference numerals, and the description thereof will be omitted. The light emitting device with a lens 97 is characterized in that a substantially hemispherical lens 96 is provided to scatter light. Lens 96
Similar to the light receiving device with lens 97, the base 36 shown in FIG.
It is fixed on a mounting plate 94 made of a translucent synthetic resin, which is fixed to the upper end surface of a.

【0031】図13〜図20の各実施例のその他の構
成、製造工程は、図1〜図11に示した第1実施例と同
様である。
Other configurations and manufacturing steps of the respective embodiments of FIGS. 13 to 20 are the same as those of the first embodiment shown in FIGS. 1 to 11.

【0032】本件発明者の実験結果を示す。図21は、
半導体素子42に導線76の一端部77をワイヤボンデ
ィングし、導体49に他端部78をワイヤボンディング
して電気的に接続した状態を示す斜視図である。本件発
明者によれば、この導線76における各端部77,78
のワイヤボンディングによる接着強度を測定するため
に、テンションゲージと呼ばれる引張り力測定手段80
に具備される大略的にJ字状の係止端81を導線76に
係止して引張り、その引張り力を測定した。
The experimental results of the present inventors will be shown. FIG. 21 shows
FIG. 6 is a perspective view showing a state in which one end 77 of a conducting wire 76 is wire-bonded to a semiconductor element 42 and the other end 78 is wire-bonded to a conductor 49 for electrical connection. According to the inventor of the present invention, the respective end portions 77, 78 of the lead wire 76 are
In order to measure the adhesive strength of the wire bonding of the above, a tensile force measuring means 80 called a tension gauge
The substantially J-shaped locking end 81 included in the above was locked to the conducting wire 76 and pulled, and the pulling force was measured.

【0033】図22は、導線76の端部78が、導体4
9の最も上のめっき層74にワイヤボンディングによっ
て接着された状態を示す約100倍に拡大した平面図で
ある。導体76の図22における外径D1は、約30μ
mである。
In FIG. 22, the end portion 78 of the conductor wire 76 is
9 is a plan view magnified about 100 times showing a state in which the uppermost plating layer 74 of No. 9 is bonded by wire bonding. FIG. The outer diameter D1 of the conductor 76 in FIG. 22 is about 30 μm.
m.

【0034】図23は、前述の図28に示される先行技
術において、導線12の端部98をめっき領域部分8a
にワイヤボンディングした状態を示す約200倍に拡大
した平面図である。この先行技術において、前述の図2
1に示される手法で、引張り力を計測したところ、導線
12の端部98がめっき領域部分8aから剥離し、図2
4に示すようにその剥離した後のめっき領域部分8aの
表面が、参照符99で示されるようになった。この顕微
鏡の観察の状態から、導線の端部と導体との接着領域で
は、充分な面状の固着はされておらず、ソルダレジスト
による悪影響が生じていることが判る。
FIG. 23 shows that in the prior art shown in FIG. 28, the end portion 98 of the lead wire 12 is replaced with the plated region portion 8a.
It is the top view which expanded the about 200 times which shows the state which wire-bonded to. In this prior art, FIG.
When the tensile force was measured by the method shown in FIG. 1, the end 98 of the conductive wire 12 was peeled off from the plated region portion 8a, and FIG.
As shown in FIG. 4, the surface of the plated region portion 8a after the peeling is indicated by reference numeral 99. From the state of this microscope observation, it can be seen that the area of adhesion between the end of the conductor and the conductor is not sufficiently adhered in a planar manner, and the solder resist has an adverse effect.

【0035】図25は、図23および図24に示される
先行技術において、ワイヤボンディングを行う前に、本
件発明者が導体上にピンセットの先端部で導体の表面を
参照符82で示されるようにけがき、その後、導線の端
部をけがいた導体表面にワイヤボンディングし、図21
に示される手法で引張り強度の試験を行った結果を示し
た図である。図25では、導線12が端部98との境界
付近で分断されている。これによって、導線12の端部
98とめっき領域部分8aとの密着強度は、導線12の
強度よりも強く図23に示した実験結果よりも密着強度
が充分に高くなることが確認された。
FIG. 25 shows the prior art shown in FIGS. 23 and 24, in which the inventor indicates the surface of the conductor with the tip of the tweezers on the conductor by reference numeral 82 before performing wire bonding. Scribing, and then wire-bonding the end of the conductor to the scribed conductor surface.
It is the figure which showed the result of having tested the tensile strength by the method shown in FIG. In FIG. 25, the conductive wire 12 is divided near the boundary with the end 98. As a result, it was confirmed that the adhesion strength between the end portion 98 of the conductive wire 12 and the plated area portion 8a was stronger than the strength of the conductive wire 12 and was sufficiently higher than the experimental result shown in FIG.

【0036】図26および図27は、図21〜図25に
関連する本件発明者の実験結果を示すグラフである。前
述の図28の先行技術では、参照符83で示される良品
では、引張り強度測定手段80によって導線12が分断
され、両端部は発光素子11およびめっき領域部分8a
に付着されたままである。また参照符84は、先行技術
における不良品において導線12がめっき領域部分8a
から剥離してしまった実験結果である。剥離時の引張り
強度は大きなばらつきを有していることが判る。
FIGS. 26 and 27 are graphs showing the experimental results of the present inventor related to FIGS. In the prior art of FIG. 28 described above, in the non-defective product indicated by reference numeral 83, the conductive wire 12 is divided by the tensile strength measuring means 80, and both ends are provided with the light emitting element 11 and the plated region portion 8a.
Remains attached to. Further, reference numeral 84 indicates that the conductive wire 12 is a plated region portion 8a in the defective product in the prior art.
It is the result of the experiment that peeled from the. It can be seen that the tensile strength at the time of peeling has large variations.

【0037】これに対して本発明によれば、図27の参
照符85で示されるように、導線76の両端部77,7
8の密着強度は充分に高いために剥離を生じず、導線7
6が分断された。こうして導線76の導体48の最も上
のめっき層73との密着強度が充分に高いことが確認さ
れた。
On the other hand, according to the present invention, as shown by reference numeral 85 in FIG.
Since the adhesion strength of 8 is sufficiently high, peeling does not occur and the conductor 7
6 was divided. Thus, it was confirmed that the adhesion strength of the conductor 76 to the uppermost plating layer 73 of the conductor 48 was sufficiently high.

【0038】基体36は、熱可塑性樹脂に限らず、ガラ
ス繊維を添加したエポキシ樹脂など、基体となり得る材
料全般を適用できる。
The substrate 36 is not limited to a thermoplastic resin, and any material that can serve as a substrate, such as an epoxy resin containing glass fiber, can be applied.

【0039】本発明は、発光素子および受光素子に関連
して実施されるだけでなく、その他の各種の半導体素子
に関連して広範囲に実施することができる。
The present invention can be widely applied not only to the light emitting element and the light receiving element, but also to various other semiconductor elements.

【0040】[0040]

【発明の効果】以上のように本発明によれば、複数のめ
っき層が形成される半導体装置を製造する際に、ソルダ
レジスト膜を形成した後に最も上のめっき層を形成して
いるので、最も上のめっき層の表面が、ソルダレジスト
膜の硬化時に発生するガスなどによって汚損されること
がない。そのため、半導体装置に配置される半導体素子
と、めっき層によって形成された導体とをワイヤボンデ
ィングする際、ワイヤボンディング強度が向上し、半導
体装置の品質の向上を図ることができる。また、最も上
のめっき層の表面が汚損されないので、洗浄のための工
程が不必要となり、半導体装置の製造コストを抑えるこ
とが可能となる。
As described above, according to the present invention, when a semiconductor device having a plurality of plating layers is formed, the uppermost plating layer is formed after the solder resist film is formed. The surface of the uppermost plating layer is not contaminated by gas generated when the solder resist film is cured. Therefore, when wire bonding the semiconductor element arranged in the semiconductor device and the conductor formed by the plating layer, the wire bonding strength is improved, and the quality of the semiconductor device can be improved. Moreover, since the surface of the uppermost plating layer is not contaminated, the step for cleaning is unnecessary, and the manufacturing cost of the semiconductor device can be suppressed.

【0041】また本発明によれば、仕切り壁を隔てて隣
接する一対の凹所を有し、複数のめっき層が形成される
光半導体装置を製造する際に、ソルダレジスト膜を仕切
り壁の端面を含む基体または導体の予め定める領域に形
成した後に、最も上のめっき層を形成しているので、最
も上のめっき層の表面がソルダレジスト膜の硬化時に発
生するガスなどによって汚損されることがない。そのた
めに光半導体装置の凹所内において、受光および発光の
ための各半導体素子と導体とをワイヤボンディングする
際、ワイヤボンディング強度が向上し、光半導体装置の
品質の向上を図ることができる。また最も上のめっき層
の表面が汚損されないので、洗浄のための工程が不必要
となり、光半導体装置の製造コストを抑えることが可能
となる。
Further, according to the present invention, when manufacturing an optical semiconductor device having a pair of recesses adjacent to each other with a partition wall interposed therebetween and a plurality of plating layers are formed, the solder resist film is used as an end surface of the partition wall. Since the uppermost plating layer is formed after it is formed on the predetermined area of the base or conductor containing the metal, the surface of the uppermost plating layer may be contaminated by the gas generated when the solder resist film is cured. Absent. Therefore, when wire bonding each semiconductor element for receiving and emitting light to the conductor in the recess of the optical semiconductor device, the wire bonding strength is improved and the quality of the optical semiconductor device can be improved. In addition, since the surface of the uppermost plating layer is not contaminated, the process for cleaning is unnecessary and the manufacturing cost of the optical semiconductor device can be suppressed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例である光結合装置51を一方
側から見た斜視図である。
FIG. 1 is a perspective view of an optical coupling device 51 according to an embodiment of the present invention as viewed from one side.

【図2】本発明の一実施例である光結合装置51を他方
側から見た斜視図である。
FIG. 2 is a perspective view of an optical coupling device 51 according to an embodiment of the present invention viewed from the other side.

【図3】基体1の断面図である。FIG. 3 is a cross-sectional view of a base body 1.

【図4】フォトレジスト59,60,61が形成された
基体1の断面図である。
FIG. 4 is a cross-sectional view of the base body 1 on which photoresists 59, 60, 61 are formed.

【図5】下地めっき層71,72が形成された基体1の
断面図である。
FIG. 5 is a cross-sectional view of the base body 1 on which base plating layers 71 and 72 are formed.

【図6】フォトレジスト87,88,89が除去された
基体1の断面図である。
FIG. 6 is a cross-sectional view of the base body 1 from which photoresists 87, 88 and 89 have been removed.

【図7】ソルダレジスト膜69,70が形成された基体
1の断面図である。
FIG. 7 is a cross-sectional view of the base body 1 on which solder resist films 69 and 70 are formed.

【図8】最も上のめっき層73,74が形成された基体
1の断面図である。
FIG. 8 is a cross-sectional view of the base body 1 on which the uppermost plating layers 73 and 74 are formed.

【図9】発光素子42が配置された基体1の断面図であ
る。
FIG. 9 is a cross-sectional view of the base body 1 on which the light emitting element 42 is arranged.

【図10】発光素子42とめっき層74とをワイヤボン
ディングした基体1の断面図である。
FIG. 10 is a cross-sectional view of the base 1 on which the light emitting element 42 and the plating layer 74 are wire bonded.

【図11】封止材79が充填された基体1の断面図であ
る。
11 is a cross-sectional view of the base body 1 filled with a sealing material 79. FIG.

【図12】半田60,61によって電気的に接続された
光結合装置35と基板57との断面図である。
FIG. 12 is a cross-sectional view of an optical coupling device 35 and a substrate 57 that are electrically connected by solders 60 and 61.

【図13】本発明の他の実施例である受光装置91を一
方側から見た斜視図である。
FIG. 13 is a perspective view of a light receiving device 91 according to another embodiment of the present invention as seen from one side.

【図14】本発明の他の実施例である受光装置91を他
方側から見た斜視図である。
FIG. 14 is a perspective view of a light receiving device 91 according to another embodiment of the present invention as viewed from the other side.

【図15】本発明のさらに他の実施例である発光装置9
3を一方側から見た斜視図である。
FIG. 15 is a light emitting device 9 which is still another embodiment of the present invention.
It is the perspective view which looked at 3 from one side.

【図16】本発明のさらに他の実施例である発光装置9
3を他方側から見た斜視図である。
FIG. 16 is a light emitting device 9 according to still another embodiment of the present invention.
It is the perspective view which looked at 3 from the other side.

【図17】本発明のさらに他の実施例であるレンズ付き
受光装置95を一方側から見た斜視図である。
FIG. 17 is a perspective view of a light receiving device with a lens 95 which is still another embodiment of the present invention, as seen from one side.

【図18】本発明のさらに他の実施例であるレンズ付き
受光装置95を他方側から見た斜視図である。
FIG. 18 is a perspective view of a light receiving device with lens 95 which is still another embodiment of the present invention, as seen from the other side.

【図19】本発明のさらに他の実施例であるレンズ付き
発光装置97を一方側から見た斜視図である。
FIG. 19 is a perspective view of a light emitting device with lens 97 which is still another embodiment of the present invention, as seen from one side.

【図20】本発明のさらに他の実施例であるレンズ付き
発光装置97を他方側から見た斜視図である。
FIG. 20 is a perspective view of a light emitting device with lens 97 which is still another embodiment of the present invention, as seen from the other side.

【図21】ワイヤボンディング強度を測定する様子を示
した斜視図である。
FIG. 21 is a perspective view showing how the wire bonding strength is measured.

【図22】光結合装置35においてめっき層74と導線
76がワイヤボンディングされた様子を示した平面図で
ある。
22 is a plan view showing a state in which the plating layer 74 and the conductive wire 76 are wire-bonded in the optical coupling device 35. FIG.

【図23】めっき領域部分8aと導線12がワイヤボン
ディングされた様子を示した平面図である。
FIG. 23 is a plan view showing a state in which the plated area portion 8a and the conductive wire 12 are wire-bonded.

【図24】めっき領域部分8aから導線12が剥離した
様子を示した平面図である。
FIG. 24 is a plan view showing a state in which the conductor wire 12 is peeled from the plating region portion 8a.

【図25】けがき傷を入れためっき領域部分8aと導線
12の端部98を示した平面図である。
FIG. 25 is a plan view showing a plating region portion 8a having a scratch and an end portion 98 of the conductive wire 12.

【図26】従来の技術によって製造された半導体装置に
おけるワイヤボンディング強度の測定データである。
FIG. 26 is measurement data of wire bonding strength in a semiconductor device manufactured by a conventional technique.

【図27】本発明に従って製造された半導体装置におけ
るワイヤボンディング強度の測定データである。
FIG. 27 is measurement data of wire bonding strength in a semiconductor device manufactured according to the present invention.

【図28】従来の技術に基づく光結合装置21の製造工
程の順序を示した図である。
FIG. 28 is a view showing the sequence of manufacturing steps for the optical coupling device 21 based on the conventional technique.

【符号の説明】[Explanation of symbols]

35 光結合装置 36 基体 37 仕切り壁 38,39 凹所 42 発光素子 43 受光素子 57 配線基板 58,59 導体 60,61 半田 69,70 ソルダレジスト膜 71,72 下地めっき層 73,74 最も上のめっき層 76 導線 79 封止材 87,88,89 フォトレジスト 35 Optical Coupling Device 36 Base Body 37 Partition Wall 38, 39 Recess 42 Light-Emitting Element 43 Light-Receiving Element 57 Wiring Board 58, 59 Conductor 60, 61 Solder 69, 70 Solder Resist Film 71, 72 Undercoat Plating Layer 73, 74 Topmost Plating Layer 76 Conductor 79 Encapsulant 87, 88, 89 Photoresist

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 合成樹脂製基体上に複数層から成る導体
をめっきによって形成し、 基体または導体の予め定める領域にソルダレジスト膜を
形成し、 半導体素子と前記導体とを導線によってワイヤボンディ
ングする半導体装置の製造方法において、 前記複数層のうち少なくとも最も上の層を、めっきによ
って形成する前に、ソルダレジスト膜を形成することを
特徴とする半導体装置の製造方法。
1. A semiconductor in which a conductor composed of a plurality of layers is formed on a synthetic resin substrate by plating, a solder resist film is formed on a predetermined region of the substrate or the conductor, and a semiconductor element and the conductor are wire-bonded by a conductor wire. A method for manufacturing a semiconductor device, comprising forming a solder resist film before forming at least the uppermost layer of the plurality of layers by plating.
【請求項2】 仕切り壁を隔てて隣接する一対の凹所を
有する合成樹脂製基体を成形し、 基体の各凹所の内周面と、基体の外周面とにわたって複
数層の導体をめっきによって形成し、 前記複数層のうち少なくとも最も上の層を、めっきによ
って形成する前に、前記仕切り壁の端面を含む基体また
は導体の予め定める領域にソルダレジスト膜を形成し、 導体の最も上の層を形成した後に、一方の凹所内で発光
のための半導体素子と導体とを導線によってワイヤボン
ディングするとともに、他方の凹所内で受光のための半
導体素子と導体とを導線によってワイヤボンディング
し、 各凹所内に透光性合成樹脂を充填することを特徴とする
光半導体装置の製造方法。
2. A synthetic resin substrate having a pair of recesses adjacent to each other with a partition wall therebetween is molded, and a plurality of conductor layers are plated on the inner peripheral surface of each recess of the base member and the outer peripheral surface of the base by plating. And forming a solder resist film on a predetermined area of the base or conductor including the end face of the partition wall before forming at least the uppermost layer of the plurality of layers by plating, and forming the uppermost layer of the conductor. After forming, the semiconductor element and the conductor for light emission are wire-bonded with a conductor in one recess, and the semiconductor element and the conductor for light reception are wire-bonded with a conductor in the other recess, and each recess is formed. A method for manufacturing an optical semiconductor device, characterized in that a transparent synthetic resin is filled in the place.
JP20780194A 1994-08-31 1994-08-31 Method for manufacturing optical semiconductor device Expired - Fee Related JP3007800B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20780194A JP3007800B2 (en) 1994-08-31 1994-08-31 Method for manufacturing optical semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20780194A JP3007800B2 (en) 1994-08-31 1994-08-31 Method for manufacturing optical semiconductor device

Publications (2)

Publication Number Publication Date
JPH0878457A true JPH0878457A (en) 1996-03-22
JP3007800B2 JP3007800B2 (en) 2000-02-07

Family

ID=16545727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20780194A Expired - Fee Related JP3007800B2 (en) 1994-08-31 1994-08-31 Method for manufacturing optical semiconductor device

Country Status (1)

Country Link
JP (1) JP3007800B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001291792A (en) * 2000-04-06 2001-10-19 Nec Corp Semiconductor device
JP2013519995A (en) * 2010-02-12 2013-05-30 億光電子工業股▲ふん▼有限公司 Proximity sensor package structure and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001291792A (en) * 2000-04-06 2001-10-19 Nec Corp Semiconductor device
JP2013519995A (en) * 2010-02-12 2013-05-30 億光電子工業股▲ふん▼有限公司 Proximity sensor package structure and manufacturing method thereof

Also Published As

Publication number Publication date
JP3007800B2 (en) 2000-02-07

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