JP2001267569A - Ｍｏｓゲートデバイスの能動電極用の薄いバリア金属 - Google Patents

Ｍｏｓゲートデバイスの能動電極用の薄いバリア金属

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Publication number
JP2001267569A
JP2001267569A JP2001028220A JP2001028220A JP2001267569A JP 2001267569 A JP2001267569 A JP 2001267569A JP 2001028220 A JP2001028220 A JP 2001028220A JP 2001028220 A JP2001028220 A JP 2001028220A JP 2001267569 A JP2001267569 A JP 2001267569A
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JP
Japan
Prior art keywords
layer
aluminum
contact structure
thin
tiw
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001028220A
Other languages
English (en)
Inventor
Thomas Herman
トーマス・ハーマン
Kyle Spring
カイル・スプリング
Mark Maier
マーク・マイアー
Harold Davis
ハロルド・デイビス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Americas Corp
Original Assignee
Infineon Technologies Americas Corp
International Rectifier Corp USA
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Filing date
Publication date
Application filed by Infineon Technologies Americas Corp, International Rectifier Corp USA filed Critical Infineon Technologies Americas Corp
Publication of JP2001267569A publication Critical patent/JP2001267569A/ja
Pending legal-status Critical Current

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Abstract

(57)【要約】 【課題】 温度の昇降が繰返される間にシリコンが析出
してデバイスが不良になる。 【解決手段】 薄いＴiＷバリア層が能動表面の側壁ス
ペーサとアルミニゥムのトップコンタクトとの間に設け
られる。アルミニゥムコンタクトは純アルミニゥムコン
タクトであり、ＴiＷバリア層を覆う。当デバイスは温
度の昇降繰返しに優れ、抵抗率を低減する。アルミニゥ
ムまたは金のボンドワイヤを純アルミニゥムのトップ表
面に結合できる。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、パワーＭＯＳＦＥ
Ｔ、ＩＧＢＴおよびＭＯＳゲートサイリスタのようなＭ
ＯＳゲートデバイスのための接点構造および製造方法に
関し、より詳しくは、アクティブな表面を含むジャンク
ション上のコンタクト層のための改良されたワイヤーボ
ンディングとステップ範囲を可能にする新規なコンタク
ト構造に関する。
【０００２】
【従来の技術】能動なコンタクト表面を有するＭＯＳゲ
ートデバイスで、ワイヤボンドのコンタクトまたは同様
なものが、ソースまたはエミッタコンタクト層下に横た
わる能動な接合部の上に直接に形成されるものが公知で
ある。このようなデバイスは、例えば、米国特許 第 5,
795,793 および1999年１１月８日出願の継続中の出願(I
R-1531) 第09/436,302の“LOW VOLTAGE MOSFET AND PRO
CESS FOR ITS MANUFACYURE AND CIRCUIT APPLICATION
IN THE NAME OF Thomas Herman”に開示されている。
【０００３】このようなデバイスは、通常、適した接合
パターン、例えば単結晶のシリコンチップのトップ表面
内のＤＭＯＳタイプがある。連続したアルミニゥムソー
ス電極(およそ１％のシリコンを含むアルミニゥム)は、
その後、デバイスのトップ表面の上に形成され、接合パ
ターンのソースおよびベース領域にオーミックコンタク
トが作られる。これらの領域は、平面セル状、平面の帯
または溝構造のようないずれか所望の幾何学的形状を持
つ。ＩＧＢＴの場合、ソース領域はエミッタ領域と呼
び、ソース電極はエミッタ電極と呼ばれてもよい。
【０００４】シリコンチップのトップ表面もゲート絶縁
(通常、酸化物)上に配置されたポリシリコンのゲート電
極を持つ。ゲート電極またはパターンの側方エッジおよ
びトップは通常、垂直の側壁またはスペーサを含む低温
の酸化物層によりカバーされる。アルミニゥム電極はそ
の後、シリコン表面でベースおよびソース領域と接触す
るが、ポリシリコンゲート電極から絶縁される。上述の
ように、“アルミニゥム”電極は実際はＡlＳiであり、
アルミニゥムにおよそ１％のシリコンを含む合金であ
る。
【０００５】通常薄い金のワイヤリードであるワイヤリ
ードがソースまたはエミッタ電極(以後、“ソース”電
極)のトップ表面と能動の接合部の上にとにこれらの接
合部に損傷を与えることなく、直接に超音波により結合
されるように、これらのデバイスが整列される。
【０００６】
【発明が解決しようとする課題】特に薄い側壁の酸化物
のスペーサ(例えば０．５マイクロメータ厚)を用いたと
き、超音波結合のワイヤーリードを有するデバイスは、
温度の昇降の繰返しにより、不良に陥ることがわかって
いる。これらの部品を検証した結果、この不良化は、側
壁スペーサとＡlＳiのソースコンタクトとの境界に生じ
た極めて小さいシリコンの塊が予期せずに出現したこと
に起因する。これらの塊は、ＡlＳiコンタクトからの析
出物であり、かつ、これらの塊が温度変化の繰返しの間
に、側壁に対し、機械的な応力および／又は磨耗を与え
たためと認識されている。このような損傷は、ＡlＳiコ
ンタクトへのワイヤーボンディングからも伝わることも
認識されている。
【０００７】
【課題を解決するための手段】本発明によれば、側壁ス
ペーサと覆っているコンタクトとの間で応力バリアとし
て作用させるために、薄い金属バリア層がＡlＳiソース
コンタクトと側壁スペーサとの間に設けられる。その薄
いバリア層は、ワイヤーボンディングの力を吸収もしく
は拡散することが確信されている。また、バリアのため
に通常のＡlＳiソース電極を、通常のＡlＳiソースメタ
ルよりも低い抵抗率(およそ１５％低い)となる純アルミ
ニゥム(純度０．９９９９)の電極に取り変えることが可
能になることもわかった。このことは、温度の昇降繰返
しの間に析出する硬質の研磨性の塊の生成およびその研
磨作用を更に防止する。
【０００８】この発明の別の利点として、薄い(０．２
ミクロン)のバリア層および純アルミニゥム層(８ミクロ
ン)は、トップのシリコン表面に、およびポリシリコン
電極により、存在する様々なエッジ上のソース電極の改
善されたステップの保護を与える。
【０００９】純アルミニゥムコンタクトの使用は、更に
別の予期しない利点を導く。例えば、銅のボンドワイヤ
の使用を可能にする。
【００１０】
【発明の実施の形態】図１を参照すると、パワーＭＯＳ
ＦＥＴの能動部分の極めて小さい部分が断面で示されて
いる。図示のデバイスは、例えば、米国特許、5,008,72
5のような隔てられた多角形のセル、または1999年３月
２３日出願の米国特許出願、第09.038,453の「MOSFETs F
OR VERY LOW VOLTAGE DC TO DC CONVERTERS(IR-1455)」
および1999年１１月８日出願の米国特許出願、第09/43
5,302の「LOW VOLTAGE MOSFET ANDPROCESS FOR ITS MANU
FACTURE AND CIRCUIT(IR-1531)」のような平行に配置さ
れた帯のようないくつかの好ましい幾何学形態を持つ。
【００１１】一般にＭＯＳＦＥＴデバイスは、Ｎ+本体
２０およびそれの上にある、Ｎ-のエピタキシャル堆積
された接合部受け取り層４を有するチップまたはダイ
(ウエハーの一部であり、そこにこのような多数のチッ
プが同時に加工される)に組立られる。層２１の厚さお
よび濃度は、デバイスの所望とする降伏電圧により決定
される。もし図１のデバイスがＩＧＢＴならば、本体２
０はＰタイプでかつ、その上に、うすいＮ+バッファ層
を持つ。
【００１２】つぎにＤＭＯＳタイプの接合パターンが領
域２１のトップ面に形成される。他のタイプも用いられ
るが、記述される本発明ではＤＭＯＳタイプが都合よ
い。典型的なパターンは、隔てられたＰベース領域３
０、３１および３２からなり、これらは、それぞれ自己
整列されたＮ+ソース領域３３、３４および３５をその
中に含む。もしセル状の幾何学的配列が用いられたな
ら、ソース３３、３４および３５は環状であり、そし
て、領域２１のトップ表面で、Ｐ領域３０、３１および
３２それぞれの外側周辺と周辺部との間で環状の反転可
能なチャンネル領域を決定する。もし帯の幾何学形態が
採用されたなら、領域３０、３１および３２は平行な帯
となり、ソース３３、３４および３５は各々のベース領
域の反対側に沿って延在する。
【００１３】どのような形態が用いられても、一般にシ
リコンダイオードであるゲート絶縁がその上に配置さ
れ、各チャンネル領域と共通の空間となる。この結果、
薄いゲート酸化層４０、４１および４２は図示のよう
に、反転可能なチャンネル領域上に延在する。このゲー
ト酸化物は、もし環状の形態が用いられたならば単一の
格子となり、そして、帯の形態が用いられたならば、隔
てられた平行の帯を含む。ゲート酸化物のエレメント４
０、４１および４２のそれぞれの上に導電性ポリシリコ
ン層５０、５１および５２(またはポリシリコングリッ
ド)が位置する。
【００１４】トップのセグメント６０、６１、６２およ
び側壁のセパレータ６３、６５から６５および６６から
６７それぞれをもつＬＴＯ(低温酸化物)の層は、導電性
ポリシリコンセグメント５０、５１および５２を全体的
に覆い絶縁する。その側壁セグメントは、通常、およそ
厚さが０．５ミクロンである。
【００１５】この後、図１に示したように、一般的なＡ
lＳiのソース電極７０が、デバイスのトップ表面の上
と、ＬＴＯ層の表面の上に堆積されるる。浅い開口８
０、８１および８２は、各ベースセルの中央ので、か
つ、接近した側壁部の間でのシリコン表面をエッチング
されている。これらの開口は、アルミニゥムシリコンソ
ース７０を、Ｐ領域３０、３１および３２およびそれら
の個々のソース領域に良好な接触を作ることを可能にす
る。
【００１６】一般に３つの金属の底部のドレイン(また
はコレクタ)接点９がその後、チップの底に形成され
る。
【００１７】図１の結合ワイヤ９２で示したように、通
常、一つまたは複数の金またはアルミニゥムのワイヤが
デバイスのトップ表面および能動接合領域の上にワイヤ
結合される。
【００１８】ワイヤボンディングにより、および温度の
繰返しにより生じた応力が、ソース電極間で短絡まては
接続している側壁６３から６７を不良にしたり、あるい
は、絶縁されたゲートポリシリコン５０、５１および５
２をダメにすることにより、デバイスに故障を生じさせ
る。故障したデバイスを調べてみると、小さくて硬いシ
リコンの塊が側壁６３から６７とＡLＳiコンタクト層７
０との境界に発見された。一般的なＡLＳi電極７０から
生じたことが確認されている。
【００１９】本発明の第１の特徴および図２によれば、
薄い金属性のバリア層１００好ましくはＴｉＷが図２の
パターン化されたＬＴＯ層の上に直接に、かつ、メイン
のソースコンタクトの下に形成される。層１００は薄
く、好ましくはおよそ０．２５のミクロン厚で、０．０
５から０．３５のミクロン厚の範囲であってもよい。好
ましくは、層１００は、ＴiＷ(Ｔi１０％,Ｗ９０％)で
あり、通常、スパッター工程により、堆積される。他の
材料、例えばＴiＮも使用できる。
【００２０】薄いバリア層は、ワイヤボンディングの間
に生じた応力を外に広げ、側壁スペーサの亀裂を防止す
るのに役立つ傾向のあることが見出されている。
【００２１】薄い導電性バリア層がチップのトップ表面
を覆い、かつデバイス表面でソースおよびベース領域で
接触しているため、そのソース電極は、ＡlＳi電極にあ
るシリコン成分を持つ必要がないということも認識され
ている。この結果、バリア層１００の上のメイン電極
は、たとえばおよそ８ミクロン厚(限定ではない)の純
(０．９９９)アルミニゥム層１０１(図２)でなくてはな
らない。更に、ＴiＷのバリアが用いられたとき、ＴiＷ
との改善された両立のために、ＡlＳiよりも純アルミニ
ゥムが好まれる。この純アルミニゥムのコンタクトは、
一般のＡlＳiと比べて抵抗率が１５％低く、より低いＲ
DSONのデバイスを提供する。更に、結合されたバリア層
および純銀層により、ポリシリコンのゲートエッジおよ
び開口８０、８１および８２内により良いステップの保
護が提供されることが見出された。
【００２２】シリコン無しまたは純アルミニゥムの電極
１０１の使用による更に別の利点は、側壁スペーサでの
境界で硬質シリコンの塊はもはや形成されず、そのた
め、これらのスペーサは温度の繰返しの間に疲労しない
ことが見出された。
【００２３】本発明は特定の実施例に関して述べたが、
当業者には他の多くの変形および変化および他の使用が
可能ことは明白である。それ故、本発明は、ここの特定
の開示により限定されるものではなく、付記した特許請
求の範囲にのみによって限定される。
【００２４】
【発明の効果】以上説明したように、本発明は、能動表
面の側壁スペーサとアルミニゥムのトップコンタクトと
の間に薄いＴiＷバリア層を設け、かつ、バリアのため
に通常のＡlＳiソース電極に替えて純アルミニゥムを用
いたので、温度の昇降繰返しの間に析出する硬質の研磨
性の塊の生成およびその研磨作用を更に防止できる。
【図面の簡単な説明】
【図１】 通常のＤＭＯＳ接合パターンおよびAlSiソー
ス接点を採用した従来のパワーＭＯＳＦＥＴの縦断面図
【図２】 図１と同様な縦断面図であるが、本発明に基
づき、純アルミニゥムのソース接点の下にバリアメタル
を用い図
【符号の説明】
２０ Ｎ+本体 ３０,３１,３２ Ｐベース領域 ３３,３４,３５ Ｎ+ソース領域 ４０,４１,４２ ゲート酸化層 ５０,５１,５２ 導電性ポリシリコン層 ６０,６１,６２ トップのセグメント ６３,６４,６５,６６,６７ 側壁 ７０ ＡlＳiコンタクト層 ８０,８１,８２ 開口 １００ バリア層 １０１ 純アルミニゥム電極
───────────────────────────────────────────────────── フロントページの続き (72)発明者 トーマス・ハーマン アメリカ合衆国90266カリフォルニア州マ ンハッタン・ビーチ、パーム・アベニュー 3113番 (72)発明者 カイル・スプリング アメリカ合衆国92592カリフォルニア州テ メキュラ、コルテカルモナ32094番 (72)発明者 マーク・マイアー アメリカ合衆国92591カリフォルニア州テ メキュラ、セナ・コート27406番 (72)発明者 ハロルド・デイビス アメリカ合衆国92103カリフォルニア州サ ンディエゴ、ドーブ・ストリート3911番、 ナンバー305

Claims (10)

    【特許請求の範囲】
  1. 【請求項１】 ＭＯＳゲートデバイスの能動表面に接触
    するためのコンタクト構造であり、前記能動表面はシリ
    コンチップのトップ表面にＤＭＯＳタイプの接合パター
    ンを含み、前記ＤＭＯＳ接合パターンは前記接触構造か
    らポリシリコンのゲートを絶縁するために、薄い絶縁側
    壁のスペーサを有し、 前記コンタクト構造は、前記側壁のスペーサの露出され
    た表面のトップにコーティングされた薄い導電性バリア
    層および、能動表面全体のトップおよび上方にコーティ
    ングされ、かつ、前記薄い導電性バリア層と接触した比
    較的より厚いアルミニゥム層を含むことを特徴とするコ
    ンタクト構造。
  2. 【請求項２】 上記の薄いバリア層は、上記アルミニゥ
    ム層と同じ広がりを持つ請求項１記載のコンタクト構
    造。
  3. 【請求項３】 上記薄いバリア層は、ＴiＷで、上記ア
    ルミニゥム層は純銀である請求項１または２記載のコン
    タクト構造。
  4. 【請求項４】 上記ＴiＷ層は、およそ０．２マイクロ
    メートル厚さで、上記アルミニゥム層は、前記ＴiＷ層
    の少なくともおよそ１０倍以上厚い請求項３記載のコン
    タクト構造。
  5. 【請求項５】 上側表面を持つシリコンチップ、前記シ
    リコン表面の与えられた領域の上のゲート酸化物層、前
    期ゲート酸化物層上の導電性ポリシリコン電極、上側表
    面および前記ポリシリコン電極の前記側壁エッジの周り
    に延在する絶縁層、前記絶縁層を覆い、かつ、前記ゲー
    ト酸化物層のエッジを除去した位置でシリコン表面に接
    触しているＴiＷの層、および前記ＴiＷの層を覆うアル
    ミニゥム層を含むことを特徴とするＭＯＳゲートのデバ
    イス。
  6. 【請求項６】 上記絶縁層は、上記ポリシリコンの層の
    側方エッジでおよそ０．５ミクロンの厚さを有する請求
    項５記載のデバイス。
  7. 【請求項７】 上記絶縁層は、上記ＴiＷ層はおよそ
    ０．２マイクロメータの厚さを有する請求項６記載のデ
    バイス。
  8. 【請求項８】 上記アルミニゥム層は、純アルミニゥム
    である請求項５〜７のいずれかに記載のデバイス。
  9. 【請求項９】 上記アルミニゥム層のトップに超音波的
    に結合される導電性リードワイヤを更に含む請求項５〜
    ７のいずれかに記載のデバイス。
  10. 【請求項１０】 上記導伝性リードワイヤは銅である請
    求項９記載のデバイス。
JP2001028220A 2000-02-04 2001-02-05 Ｍｏｓゲートデバイスの能動電極用の薄いバリア金属 Pending JP2001267569A (ja)

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US09/497735 2000-02-04

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040002065A (ko) * 2002-06-29 2004-01-07 주식회사 하이닉스반도체 파워 소자 형성 방법
US6872653B2 (en) 2002-04-19 2005-03-29 Renesas Technology Corp. Manufacturing method of semiconductor device
KR100851492B1 (ko) * 2002-06-29 2008-08-08 매그나칩 반도체 유한회사 파워 소자 형성 방법
US20100291767A1 (en) * 2009-05-18 2010-11-18 Renesas Technology Corp. Manufacturing method of semiconductor device
JP2020533793A (ja) * 2017-09-11 2020-11-19 ゼネラル・エレクトリック・カンパニイ 半導体素子上に金属層を形成するためのスパッタリングシステムおよび方法

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JPH0834311B2 (ja) * 1987-06-10 1996-03-29 日本電装株式会社 半導体装置の製造方法
FR2616966B1 (fr) * 1987-06-22 1989-10-27 Thomson Semiconducteurs Structure de transistors mos de puissance
US4931408A (en) * 1989-10-13 1990-06-05 Siliconix Incorporated Method of fabricating a short-channel low voltage DMOS transistor
US5019234A (en) * 1990-06-08 1991-05-28 Vlsi Technology, Inc. System and method for depositing tungsten/titanium films
US5171699A (en) * 1990-10-03 1992-12-15 Texas Instruments Incorporated Vertical DMOS transistor structure built in an N-well CMOS-based BiCMOS process and method of fabrication
US5795793A (en) * 1994-09-01 1998-08-18 International Rectifier Corporation Process for manufacture of MOS gated device with reduced mask count
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6872653B2 (en) 2002-04-19 2005-03-29 Renesas Technology Corp. Manufacturing method of semiconductor device
KR20040002065A (ko) * 2002-06-29 2004-01-07 주식회사 하이닉스반도체 파워 소자 형성 방법
KR100851492B1 (ko) * 2002-06-29 2008-08-08 매그나칩 반도체 유한회사 파워 소자 형성 방법
US20100291767A1 (en) * 2009-05-18 2010-11-18 Renesas Technology Corp. Manufacturing method of semiconductor device
US9177813B2 (en) 2009-05-18 2015-11-03 Renesas Electronics Corporation Manufacturing method of semiconductor device
JP2020533793A (ja) * 2017-09-11 2020-11-19 ゼネラル・エレクトリック・カンパニイ 半導体素子上に金属層を形成するためのスパッタリングシステムおよび方法
JP7262448B2 (ja) 2017-09-11 2023-04-21 ゼネラル・エレクトリック・カンパニイ 半導体素子上に金属層を形成するためのスパッタリングシステムおよび方法

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Publication number Publication date
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DE10104274C5 (de) 2008-05-29
DE10104274B4 (de) 2006-05-11

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