JP2001178890A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a power source shutdown operation from being performed by mistake during the startup of a game machine when a power is supplied. SOLUTION: The game machine wherein a game player can perform a predetermined game includes an electric component control means and a power source monitoring means which monitors the voltage of a power source of a predetermined voltage, which is used for the game machine, and outputs a sensing signal when a predetermined condition is established. The electric component control means performs a predetermined power feed suspension process based on a sensing signal from the power source monitoring means and includes a power supply suspension process limit means to prevent a power supply suspension process from being performed when a power is supplied to the electric component control means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko game machine, a coin game machine, a slot machine, etc., in which a game is played in accordance with a player's operation. A gaming machine in which a game is played in accordance with a game machine.

[0002]

2. Description of the Related Art As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of prize balls are obtained. Are paid out to players.
Furthermore, a variable display unit capable of changing the display state is provided,
There is a configuration in which a predetermined game value is provided to a player when a display result of the variable display unit has a predetermined specific display mode.

[0003] The game value means that the state of the variable prize ball device provided in the game area of the gaming machine is in an advantageous state for a player who is likely to win a hit ball, or in an advantageous state for the player. Or a condition in which the conditions for paying out prize game media are easily satisfied.

In a pachinko gaming machine, when a display result of a variable display section for displaying a special symbol is a combination of a predetermined specific display mode, it is generally called a "big hit". When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state in which a hit ball is easy to win. In each open period, a predetermined number (for example, 10
) Will be closed when there is a prize in the special winning opening.
The number of opening of the special winning opening is a predetermined number (for example, 16
Round). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. Further, at the time when the special winning opening is closed, predetermined conditions (for example, winning in the V zone provided in the special winning opening)
Is not established, the big hit gaming state ends.

[0005] In addition, among the combinations of display modes other than the "big hit" combination, at a stage where some of the display results of the plurality of variable display portions have not been derived and displayed yet, the display results have already been derived and displayed. The state in which the display mode of the variable display unit that satisfies the display condition that is a combination of the specific display modes is called “reach”. If the display result of the identification information variably displayed on the variable display unit does not satisfy the condition of “reach”, the result is “out” and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

When a game ball wins a winning opening provided on the game board, a predetermined number of award balls are paid out. Since the progress of the game is controlled by the game control means mounted on the main board, the number of winning balls based on the winning is determined by the game control means,
Sent to the prize ball control board. Hereinafter, the game control means and the other control means may be respectively referred to as electric component control means.

[0007]

As described above, a gaming machine is equipped with various electric component control means including game control means. Generally, each electric component control means is constituted by a microcomputer, and after a power failure occurs, the control returns from an initial state, so that a problem that a player cannot receive a profit that should have been obtained may occur. As one of means for solving such a problem, the game control is interrupted in response to a predetermined signal issued along with a decrease in the voltage value of the gaming machine due to a power failure or the like, and a power-off process is started to set the power-off state. There is a method in which the stored contents are protected by a backup power supply, and the power is restored.

When such a method is used, the microcomputer erroneously starts power-off processing according to the level of a predetermined signal even when the voltage value of the gaming machine is increasing during recovery from a power failure or the like. And the power may be turned off again.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to prevent a power-off process from being erroneously performed during the start-up of a gaming machine when the power is turned on, such as when the power is restored after a power failure.

[0010]

A gaming machine according to the present invention comprises:
A gaming machine in which a player can play a predetermined game, an electrical component control means for performing processing for controlling an electrical component provided in the gaming machine, and a voltage of a predetermined potential power supply used in the gaming machine And a power supply monitoring means for outputting a detection signal when a predetermined condition is satisfied, wherein the electric component control means executes a predetermined power supply stop processing according to the detection signal from the power supply monitoring means, When the power supply of the control means is started, a power supply stop processing restriction means for preventing the power supply stop processing from being executed is provided. Examples of the electric component control means include a game control means for controlling the progress of the game and a payout control means for controlling the payout of the game medium.

The power supply interruption processing restriction means includes a delay means for delaying the timing of canceling the system reset of the electric component control means, and the power supply interruption processing in response to the input of the detection signal of the power supply monitoring means by the delay means. May be configured to delay the timing at which execution of the program can be performed.

[0012] The power supply stop time processing restriction means is longer than the period during which the detection signal from the power supply monitoring means indicates the execution of the power supply stop time processing after the power supply is started. The control means may be configured to hold the system reset state.

The electric component control means performs a predetermined startup process in response to the release of the system reset, and the predetermined condition is satisfied when the voltage of the predetermined potential power supply is less than a predetermined value,
The predetermined value may be set to a value smaller than the value of the voltage of the predetermined potential power supply at the end of the startup process.

[0014] The power supply monitoring means may be configured to output a detection signal to the electric component control means when the power supply is stopped and before the electric component control means becomes inoperable.

The detection signal may be configured to be input to the electric component control means as an NMI interrupt signal.

[0016] The electric component control means, at the start of power supply,
The configuration may be such that the control can be restarted based on the held data held in the storage means capable of holding the contents immediately before the stop of the power supply.

[0017] The electric component control means may be configured to execute a RAM access prohibition process in the power supply stop process.

[0018]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of the pachinko gaming machine 1 as viewed from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the pachinko gaming machine 1 as viewed from the back. In the following embodiments, a description will be given of a pachinko gaming machine as an example, but the gaming machine according to the present invention is not limited to a pachinko gaming machine,
For example, a coin gaming machine or the like may be used. Further, the present invention can be applied to an image-type gaming machine or a slot machine.

As shown in FIG. 1, the pachinko gaming machine 1 comprises:
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing prize balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, a variable display section 9 for variably displaying a plurality of types of symbols and a 7-segment L
A variable display device 8 including a variable display 10 using an ED is provided. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In a passage between the passage gate 11 and the ball outlet 13, there is a gate switch 12 for detecting a hit ball that has passed through the passage gate 11. In addition, the winning ball that entered the starting winning port 14 is
It is guided to the back of the game board 6 and is detected by the starting port switch 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16.

Below the variable winning ball device 15, there is provided an opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state). In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. The winning ball that enters one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V count switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. Variable display device 8
A start winning prize storage display 18 having four display sections for displaying the number of winning balls entering the starting winning prize port 14 is provided below. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The gaming board 6 is provided with a plurality of winning ports 19 and 24, and winning of the gaming balls to the winning ports 19 and 24 is detected by the winning port switches 19a and 24a. At the left and right sides of the game area 7, there are provided decorative lamps 25 which are displayed blinking during the game, and at the lower part there is an out port 26 for absorbing hit balls which have not won. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. A gaming effect LED 2 is provided on the outer periphery of the gaming area 7.
8a and gaming effect lamps 28b and 28c are provided.

In this example, one of the speakers 27
Is provided with a prize ball lamp 51 which is turned on when a prize ball is paid out, and near the other speaker 27, a cutout lamp 52 which is turned on when a supply ball is cut out is provided. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming table 1 and enables lending of balls by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card is in a usable state. If there is a fraction (a number less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter, the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passage gate 11, the display number of the variable display 10 is changed continuously. Further, when a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17, the symbol in the variable display section 9 starts rotating if the symbol can be changed. If it is not possible to start changing the symbol, the start winning memory is increased by one.

The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the specific winning area while the opening and closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols accompanied by a probability change, the probability of the next big hit increases. That is, a high probability state, which is more advantageous for the player, is obtained. Also, when the stop symbol on the variable display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the variable display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. On the back of the variable display device 8, as shown in FIG. 2, a prize ball tank 38 is provided above the mechanism plate 36, and when the pachinko gaming machine 1 is installed on the gaming machine installation island, a prize ball is provided from above. Premium ball tank 3
8 is supplied. The prize ball in the prize ball tank 38 reaches the ball payout device through the guide gutter 39.

On the mechanism board 36, a variable display control unit 29 for controlling the variable display section 9 via the relay board 30, and a game control board (main board) covered with a board case 32 and mounted with a game control microcomputer and the like. ) 31, a relay board 33 for relaying a signal between the variable display control unit 29 and the game control board 31, and a prize ball control board on which a prize ball control microcomputer for controlling the payout of prize balls is mounted. 37 are installed. Further, a ball is hit on the lower part of the mechanism plate 36 by using the rotating force of the motor in the game area 7.
Ball launching device 34 that launches on a game effect lamp / LE
D28a, 28b, 28c, a prize ball lamp 51, and a lamp control board 35 for transmitting signals to the ball-out lamp 52 are provided.

FIG. 3 is a rear view of the mechanical plate of the pachinko gaming machine 1 as viewed from the rear. The ball that passed through the induction gutter 39
As shown in FIG. 3, the broken-out detectors 187a, 187
b, and reaches the ball dispensing device 97 via the ball supply gutters 186a and 186b. The prize ball paid out from the ball payout device 97 is supplied to the hit ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the communication port 45. On the side of the communication port 45, an excess ball passage 46 communicating with the excess ball tray 4 provided on the front of the pachinko gaming machine 1 is formed. A large number of prize balls based on the prize are paid out, and the ball supply tray 3 becomes full. Finally, after the prize balls reach the communication port 45, further prize balls are paid out. It is led to the ball tray 4. When the prize ball is further paid out, the sensing lever 47 is set to the full switch 4.
By pressing 8, the full tank switch 48 is turned on. In this state, the rotation of the stepping motor in the ball discharging device 97 stops, the operation of the ball discharging device 97 stops, and the driving of the hitting ball firing device 34 also stops as necessary. In addition,
In this embodiment, a ball payout device 97 in which game balls are paid out by rotation of a stepping motor is illustrated as a ball payout device that pays out game balls by driving an electric drive source. A ball payout device having a structure of sending out a ball may be used, or a ball payout device having a structure in which a stopper is removed by driving an electric drive source and payout is performed by the weight of the game ball may be used.

Signals from the winning opening switches 19a and 24a, the starting opening switch 17 and the V count switch 22 are sent to the main board 31 in order to perform the prize ball payout control.
When the starting port switch 17 is turned on, the CPU 56 of the main board 31 knows that a winning corresponding to the payout of six winning balls has occurred. Further, when the count switch 23 is turned on, it is known that a winning corresponding to the payout of 15 prize balls has occurred. Then, when the winning opening switch is turned on, it is known that a winning corresponding to the payout of 10 prize balls has occurred. In this embodiment, for example, a game ball that has won the winning opening 24 is detected by the winning opening switch 24 a provided in the winning ball flow path from the winning opening 24, and the game ball that has won the winning opening 19 is detected. Is
It is detected by a winning opening switch 19a provided in a winning ball flow path from the winning opening 19.

FIG. 4 is a block diagram showing an example of the circuit configuration of the main board 31. FIG. 4 also shows the prize ball control board 37, the lamp control board 35, the sound control board 70, the emission control board 91, and the display control board 80.
The pachinko machine 1 is provided on the main board 31 according to the program.
, A switch circuit 58 for giving signals from the gate switch 12, the starting port switch 17, the V count switch 22, the count switch 23, and the winning port switches 19a, 24a to the basic circuit 53, and a variable winning ball device. A solenoid circuit 59 for driving a solenoid 16 for opening and closing the opening 15 and a solenoid 21 for opening and closing the opening and closing plate 20 in accordance with a command from the basic circuit 53; A lamp / LED circuit 60 for driving the lamp 10 and the decorative lamp 25 is mounted.

According to the data supplied from the basic circuit 53, jackpot information indicating occurrence of a jackpot, effective start information indicating the number of start winning balls used to start image display of the variable display section 9, and probability fluctuation have occurred. And an information output circuit 64 that outputs probability change information or the like indicating the fact to a host computer such as a hall management computer.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as an example of a storage means used as a work memory, a CPU 56 for performing a control operation according to a control program, and an I / O port unit 57. including. In this embodiment, the ROM 54,
The RAM 55 is built in the CPU 56. That is,
The CPU 56 is a one-chip microcomputer.
The one-chip microcomputer has at least R
It is sufficient if the AM 55 is built-in.
The / O port section 57 may be externally mounted or built-in. The I / O port unit 57 is a terminal capable of inputting and outputting information in the microcomputer.

Further, the main board 31 has an initial reset circuit 65 for resetting the basic circuit 53 when the power is turned on.
And an address decode circuit 67 that decodes an address signal provided from the basic circuit 53 and outputs a signal for selecting one of the I / O ports in the I / O port unit 57. Although there is switch information input from the ball dispensing device 97 to the main board 31, FIG.
Then they are omitted.

A hit ball launching device that hits and launches a game ball is driven by a drive motor 94 controlled by a circuit on a launch control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

FIG. 5 is a block diagram showing components related to the prize ball, such as the components of the prize ball control board 37 and the ball payout device 97. As shown in FIG. 5, the detection signal from the full tank switch 48 is transmitted to the main board 3 via the relay board 71.
1 is input to the I / O port 57. Full tank switch 4
Reference numeral 8 denotes a switch that detects whether the surplus ball tray 4 is full.

The detection signals from the broken-out detection switch 167 and the broken-out switch 187 (187a, 187b) are transmitted to the main board 3 via the relay board 72 and the relay board 71.
1 is input to the I / O port 57. The cut-out detection switch 167 is a switch for detecting a shortage of supply balls in the prize ball tank 38, and the cut-out switch 187 is a switch for detecting the presence or absence of a prize ball in the prize ball passage.

The CPU 56 of the main board 31 indicates that the detection signal from the burn-out switch 167 or the burn-out switch 187 indicates a burn-out state, or the detection signal from the full-battery switch 48 indicates the full-battery state. If it is, a prize ball control command for instructing ball lending is sent. When receiving the award ball control command instructing the ball lending prohibition, the award ball control CPU 371 of the award ball control board 37 stops the ball lending process.

Further, detection signals from the prize ball count switch 301A and the ball lending count switch 301B are also transmitted to the main board 3 via the relay board 72 and the relay board 71.
1 is input to the I / O port 57. The prize ball count switch 301A and the ball lending count switch 30
1B is provided in the prize ball mechanism portion of the ball payout device 97, and detects the prize balls actually paid out.

When there is a prize, the output ports (ports G, H) 577, 578 of the main board 31 are provided on the prize ball control board 37.
, A prize ball control command indicating the number of prize balls is input. The output port 577 outputs 8-bit data, and the output port 578 outputs a 1-bit strobe signal (INT signal). The award ball control command indicating the number of award balls is input to the I / O port 372a via the input buffer circuit 373. The CPU 371 for controlling the prize ball includes an I / O port 37.
A prize ball control command is input via 2a, and the ball payout device 97 is driven according to the prize ball control command to perform a prize ball payout. In this embodiment, the CPU 37 for controlling the prize ball
Reference numeral 1 denotes a one-chip microcomputer having at least a RAM.

The CPU 371 for controlling the prize ball includes an output port 3
Via 72g, a ball lending number signal indicating the lending ball number is output to the terminal board 160, and a buzzer drive signal is output to the buzzer board 75. A buzzer is mounted on the buzzer board 75. Further, an error signal is output to the error display LED 374 via the output port 372e.

Further, the input port 3 of the prize ball control board 37
A detection signal from the winning ball count switch 301A is input to the relay board 72b via the relay board 72. The drive signal from the prize ball control board 37 to the payout motor 289 is transmitted to the ball payout device 9 via the output port 372c and the relay board 72.
7 to the payout motor 289 in the prize ball mechanism portion 7.

The card unit 50 is provided with a microcomputer for controlling the card unit. Also,
The card unit 50 is provided with a fraction display switch 152, a connection board direction indicator 153, a card insertion indicator lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected to a frequency display LED, a ball lending switch, and a return switch provided near the hit ball supply tray 3.

From the balance display board 74 to the card unit 50
In response to the player's operation, a ball lending switch signal and a return switch signal are provided via the prize ball control board 37. In addition, the balance display board 74 is provided from the card unit 50.
, A card balance display signal indicating the balance of the prepaid card and a ball lending possible display signal are given via the prize ball control board 37. Between the card unit 50 and the prize ball control board 37, a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal)
A pachinko machine operation signal (PRDY signal) is exchanged via the I / O port 372f.

When the power of the pachinko gaming machine 1 is turned on,
The prize ball control CPU 371 of the prize ball control board 37 outputs a PRDY signal to the card unit 50. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the microcomputer for controlling the card unit outputs a BRDY signal to the prize ball control board 37. When a predetermined delay time elapses from this point, the microcomputer for controlling the card unit outputs a BRQ signal to the prize ball control board 37. The CPU 37 for controlling the prize ball on the prize ball control board 37
When the EXS signal to the card unit 50 rises and the falling of the BRQ signal from the card unit 50 is detected, the payout motor 289 is driven to pay out a predetermined number of lending balls to the player. At this time, the drive of the distribution solenoid 310 is stopped. That is, the ball distribution member 3
Turn 11 toward the ball lender. And when the payout is completed,
The award ball control CPU 371 causes the EXS signal to the card unit 50 to fall. Then, the card unit 5
If the BRDY signal from 0 is not on, the winning ball payout control is executed.

As described above, all signals from the card unit 50 are configured to be input to the prize ball control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input from 0 to the main board 31, and there is no room for a signal to be incorrectly input from the card unit 50 side to the basic circuit 53 of the main board 31. The main board 31 and the prize ball control board 37 are provided with a solenoid and a driver circuit for driving a motor or a lamp, but those circuits are omitted in FIG.

In this embodiment, the case where the card unit 50 is provided is described as an example. However, the present invention can be applied to a case where a game ball is lent according to the amount of money when a coin is inserted.

FIG. 6 is a block diagram showing an example of a configuration around the CPU 56 for power supply monitoring and power supply backup. As shown in FIG. 6, a voltage change signal (NM) from a power supply monitoring circuit (power supply monitoring means) mounted on a power supply board is provided.
An I-interrupt signal is output from a non-maskable interrupt terminal (N
MI terminal). The power supply monitoring circuit is a circuit that monitors a voltage of any one of various DC power supplies used by the gaming machine 1 and detects a change (drop or rise) in the power supply voltage. Therefore, the CPU 56 can confirm the occurrence of power interruption or power restoration by the interrupt processing.

On the main board 31, the NMI interrupt signal from the power supply monitoring circuit
It is input to the PU 56 side. Here, 74HC244 is exemplified as the input buffer circuit 900, but any circuit having an input buffer function may be used. The input buffer circuit 900 is an irreversible element that allows a signal to pass only in the direction from the power supply board to the inside of the main board 31.

In this example, the power supply monitoring circuit monitors the +30 V power supply voltage (VSL) and sets the voltage change signal to a low level when the voltage value falls below a predetermined value due to, for example, a power failure. When the voltage change signal goes low, an NMI (Non-Maskable Interrupt) is applied to the CPU 56. The CPU 56
The power-off process is executed according to the MI. Further, the level of the voltage change signal from the power supply monitoring circuit is low for a while after the power is turned on, and becomes high when the voltage value of the VSL power supply voltage becomes a predetermined value or more. Note that the detection voltage of the power supply monitoring circuit (the voltage at which the NMI interrupt signal is output) is +22 V in this embodiment. Therefore,
In this example, the detection condition under which the power supply monitoring circuit outputs the detection signal is that the +30 V power supply voltage decreases to +22 V or increases to +22 V after the power is restored. However, the voltage value used here is an example, and another value may be used.

The main board 31 is provided with a system reset circuit 65. In this example, the system reset circuit 65 monitors the same VSL power supply voltage as the power supply monitoring circuit, and sets the output to a low level when the voltage value of the VSL power supply voltage is equal to or less than a predetermined value. The low level output becomes a system reset signal. Further, the output of the system reset circuit 65 becomes high level when the VSL power supply voltage exceeds a predetermined value. Note that the detection voltage of the system reset circuit 65 is, for example, + 9V. Therefore, the system reset circuit 65
Is to output a low-level system reset signal when the VSL power supply voltage has dropped to + 9V. The detection condition for the system reset circuit 65 to release the system reset is that the VSL power supply voltage has risen to + 9V. However, the voltage value used here is an example, and another value may be used. This +9 V is a voltage at which the CPU can operate normally. By performing a system reset with such a voltage, the processing of the CPU can be normally terminated.

In this embodiment, the system reset circuit 65 includes delay means. The reset IC 651 has
A capacitor is externally connected, and the timing at which the output becomes high level is determined according to the capacitance of the capacitor. Therefore, if the capacitance of the capacitor is selected to generate a predetermined delay time, the output becomes low level for a predetermined time determined by the capacitance of the external capacitor when the power is turned on, and the output becomes high after the predetermined time elapses. Level. Also, the reset IC 651 introduces a power supply voltage of VSL, which is a power supply voltage equal to the power supply voltage monitored by the power supply monitoring circuit, to the voltage change monitoring terminal, monitors the voltage of the terminal, and when the voltage value falls below a predetermined value. Generates a low-level voltage change signal. As shown in FIG. 6, this voltage change signal is the same output signal as the reset signal. The CPU 56 enters a reset state (non-operating state) when the system reset signal from the system reset circuit 65 has a low level, and the system reset signal from the system reset circuit 65 has a high level. The set state (operating state) is set.

It should be noted that +5 which is the driving power source of the CPU 56 and the like is used.
While power is not being supplied from the V power supply, at least a portion of the RAM is backed up by a backup power supply supplied from a power supply board, and its contents are preserved even when the power to the gaming machine is cut off. When the + 5V power supply is restored and the VSL power supply voltage becomes equal to or higher than a predetermined value (in this example, + 9V), a system reset signal is issued from the system reset circuit 65, so that the CPU 56 performs predetermined startup processing such as a security check. After returning to the normal operation state.

As described above, in this embodiment, since the system reset circuit is provided with the delay means, the timing at which the system reset signal rises to a high level is delayed, and the voltage change signal (NMI) from the power supply monitoring circuit is delayed.
Interrupt signal) rises to a high level, and then the system reset signal rises to a high level. Before the system reset rises to a high level, the NMI interrupt signal rises to a high level and the power is turned off. It is possible to prevent the processing from being executed.

FIG. 7 is a block diagram showing a configuration example of a power supply board 910 of a gaming machine. The power supply board 910 is installed independently of the electric component control boards such as the main board 31, the display control board 80, the sound control board 70, the lamp control board 35, and the prize ball control board 37, and controls each electric component control board in the gaming machine. And the voltages used by the mechanical components. In this example,
AC24V, DC + 30V, DC + 21V, DC + 12
V and + 5V DC. Further, the capacitor 916 serving as a backup power supply is charged from DC + 5V, that is, a power supply line for driving an IC or the like on each substrate.

The transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
The C converter 913 has + 21V, + 12V and + 5V.
V is generated and output to the connector 915. Connector 91
5 is connected to, for example, a relay board, from which electric power of a voltage required for each electric component control board and mechanism components is supplied. A power switch for stopping and starting power supply to the gaming machine is provided on the input side of the transformer 911.

+5 V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is provided with an electric power so as to be able to hold a storage state in a backup RAM (power-backed-up RAM, that is, storage means that can be in a storage state) when the power supply to the gaming machine is cut off. Backup power supply. Also,
A diode 917 for preventing backflow is inserted between the + 5V line and the backup + 5V line.

Note that a battery that can be charged from a +5 V power supply may be used as a backup power supply. In the case of using a battery, a rechargeable battery is used which runs out of capacity when power is not supplied from a + 5V power supply for a predetermined time.

The power supply board 910 is mounted with a power supply monitoring IC 902 constituting the power supply monitoring circuit described above. The power supply monitoring IC 902 detects the occurrence of power interruption or power restoration by introducing the VSL power supply voltage and monitoring the VSL power supply voltage. Specifically, when the VSL power supply voltage becomes equal to or lower than a predetermined value (+22 V in this example), a voltage change signal is output assuming that power supply is cut off. As described above, the voltage change signal is an NMI interrupt signal, and when the NMI interrupt signal becomes low level, the NMI is applied to the CPU. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL
Is +30 which is the voltage immediately after conversion from AC to DC.
V is used. The voltage change signal from the power supply monitoring IC 902 is supplied to the main board 31, the prize ball control board 37, and the like.

The predetermined value for the power supply monitoring IC 902 to detect a power-off or power-on recovery is lower than a voltage at which the entire gaming machine operates normally,
Is a voltage that is operable for a while and that allows a switch for detecting a winning ball to perform normal detection. Further, the power supply monitoring IC 902 is configured to monitor a voltage higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and a voltage immediately after conversion from AC to DC. Therefore, the monitoring range can be extended for the voltage required by the CPU. Therefore, more precise monitoring can be performed.

Further, since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric component control board, a voltage change signal can be supplied from the power supply monitoring circuit to the plurality of electric component control boards. No matter how many electrical component control boards need a voltage change signal,
Since it is only necessary to provide one, the cost of the gaming machine does not increase so much even if each electric component control means in each electric component control board performs the power return control described later. Further, since a plurality of models can be used in common, it is possible to reduce the number of component conversion points when changing the model.

In the configuration shown in FIG. 7, the detection output (voltage change signal) of the power supply monitoring IC 902 is transmitted to the respective electric component control boards via the buffer circuits 918 and 919. One detection output may be transmitted to the relay board, and the same signal may be distributed from the relay board to each electric component control board.

FIG. 8 is a timing chart showing an example of the relationship between the system reset signal and the NMI interrupt signal (voltage change signal from the power supply monitoring circuit) at the time of power restoration in this embodiment. When power is applied to the gaming machine and the VSL power supply voltage rises and reaches a predetermined value (+9 V in this example), the system reset circuit 65 outputs a system reset signal in which the timing of rising to a high level is delayed by a predetermined time. . When the system reset signal rises, the CPU
Starts operation. During this predetermined time, the VSL power supply voltage is
The predetermined time is set so that the system reset signal rises after the NMI interrupt signal reaches a voltage value (+22 V in this example) at which it rises to a high level. That is, in this example, the capacitance of the external capacitor is determined so as to be delayed by the predetermined time. When the VSL power supply voltage further rises and reaches a predetermined value (+22 V in this example), the NMI interrupt signal from the power supply monitoring circuit goes high.

As described above, in this embodiment, the delay means is provided in the system reset circuit 65, so that the timing at which the system reset signal generated by the system reset circuit 65 becomes high can be delayed by a predetermined time. Since the system reset signal can be raised after the NMI interrupt signal has risen to a high level (a level at which no NMI is generated), the NMI interrupt signal can be maintained even after the system reset signal has risen and reset has been released. A low level situation does not occur. That is, since the NMI interrupt signal is always at the high level when the CPU starts operating, it is possible to reliably prevent the power-off process from being executed. Note that the delay unit may be, for example, a unit provided with a delay circuit after the system reset circuit.

In this embodiment, the delay means is provided. However, the CPU configured to execute a startup process such as a security check program before the execution of the control program after the reset is released. When used, the NMI interrupt signal may rise before the system reset signal rises and the startup processing such as the security check ends without providing the delay means. In this case, for example, the voltage value of the power supply voltage at which the power supply monitoring circuit raises the NMI interrupt signal is determined in consideration of the time required for the startup process so that the NMI interrupt signal rises during the startup process. Is determined.

FIG. 9 shows the NMI before the start-time process is completed.
FIG. 10 is a timing chart of a system reset signal and an NMI interrupt signal at the time of power restoration when the interrupt signal is set to a high level. When the game machine is powered on, V
When the SL power supply voltage rises and reaches a predetermined value (+9 V in this example), the output (system reset signal) of the system reset circuit 65 goes high. Then, CPU5
6, the startup process is automatically performed, and when the startup process is completed, the control program is executed. The VSL power supply voltage is set to a predetermined value (+22 in this example) during execution of this startup process.
V), the NMI interrupt signal from the power supply monitoring circuit goes high. Then, at the time when the CPU 56 completes the startup processing and shifts to the execution processing of the control program, the NMI does not occur because the NMI interrupt signal is already at the high level. Normally, when the CPU performs the startup process, no NMI occurs even if the NMI interrupt signal goes low.

According to this example, the NMI interrupt signal rises to the high level after the system reset signal rises and the CPU starts operating and before the start-up processing such as security check is completed. Before entering the state, the NMI interrupt signal can be set to a level at which no NMI is generated. As a result, it is possible to reliably prevent the power-off process from being executed after the rise of the system reset signal until the rise of the NMI interrupt signal.

Further, a delay means is provided to delay the timing at which the system reset signal rises by a predetermined time, and after the system reset signal is set to the high level, the NMI interrupt signal becomes high before the start-up processing such as the security check ends. You may rise to the level. In this case, for example, in consideration of the time required for the startup process, the NMI interrupt signal rises during the startup process.
A predetermined time for delaying the system reset signal (in this example, the capacity of the capacitor to be a predetermined time) and a voltage value for outputting each signal are determined.

FIG. 10 shows the system reset signal and the NMI at power-on when the rising timing of the system reset signal is delayed by a predetermined time by the delay means so that the NMI interrupt signal rises before the start-up processing is completed. FIG. 4 is a timing chart showing a relationship with an interrupt signal. When power is applied to the gaming machine and the VSL power supply voltage rises and reaches a predetermined value (+9 V in this example), the system reset circuit 65 outputs a system reset signal whose rising timing is delayed by a predetermined time. The VSL power supply voltage is set to a predetermined value (+5 in this example) during execution of the startup process after the system reset is delayed and released.
22V) for a predetermined period of time. When the system reset is released, the CPU 56
Perform startup processing automatically. During execution of this startup process, the VSL power supply voltage further rises to a predetermined value (+22 in this example).
V), and the NMI interrupt signal from the power supply monitoring circuit rises. The NMI interrupt signal rises to a high level before the CPU 56 finishes the startup process and shifts to the execution of the control program.

According to this example, the rising timing of the system reset signal is delayed by the predetermined time by the delay means, and the NMI interrupt signal rises before the start-up processing such as security check is completed, so that the interrupt is enabled. Before entering the state, the NMI interrupt signal can be set to a high level that does not cause an NMI. When the CPU 56 completes the startup process and shifts to the execution of the control program, the NMI interrupt signal becomes the high level. Therefore, it is possible to reliably prevent the power-off process from being executed when the power is turned on.

Next, the operation of the gaming machine will be described. FIG.
1 is a flowchart illustrating a main process executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main process, the CPU 56
First, it is confirmed whether or not it is time to recover from a power failure (step S1). Whether or not recovery from a power failure has occurred is confirmed by, for example, a power-off flag set in the backup RAM area when the power is turned off.

If recovery from a power failure has occurred, a data check (parity check in this example) of the backup RAM area is performed (step S3). If the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, and the check result becomes normal. If the check result is not normal, since the internal state cannot be returned to the state at the time of power failure, an initialization process executed at the time of power-on without power recovery is executed (steps S4 and S2).

If the check result is normal, the CPU 56
Performs the game state restoring process for returning the internal state to the state at the time of power-off (step S5), and clears the power-off flag (step S6).

If it is not time to recover from a power failure, the CPU
56 executes a normal initialization process (step S1,
S2). Thereafter, in the main process, the process shifts to a loop process in which the monitoring of the timer interrupt flag (step S6) is confirmed. In the loop, a display random number update process (step S7) is also executed.

Here, in step S1, it is confirmed whether or not the power is restored from the power failure. If the power is restored from the power failure, the parity check is performed. First, the parity check is executed, and the check result is normal. Otherwise, it is determined that it is not the recovery from the power failure, and the initialization processing of step S2 is executed, and if the check result is normal, the game state return processing may be performed. That is, it may be determined based on the result of the parity check whether recovery from a power failure has occurred.

When determining whether or not to execute the power failure recovery process, that is, when determining whether or not to recover the game state, the special process flag or the like in the stored RAM data and the number of start winning prizes are stored. According to the data, the gaming machine is in the game waiting state (the symbol is not changing, the jackpot is not playing, the probability is not changing, and there is no start winning memory)
When it is confirmed that the game state is restored, the initialization processing may be executed without performing the game state restoration processing.

In the normal initialization processing, as shown in FIG. 12, the register and RAM are cleared (step S2).
a) and the initial setting (timeout is 2 ms) of the timer register provided in the CPU 56 so that the timer is periodically interrupted every 2 ms after the necessary initial value setting processing (step S2b) is performed. And a setting for operating the repetition timer) is performed (step S2c). That is, in step S2c, a process of activating a timer interrupt and a process of setting a timer interrupt interval are executed.

Therefore, in this embodiment, the CPU 56
Is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is 2 ms
Is set to Then, as shown in FIG. 13, when a timer interrupt occurs, the CPU 56 sets a timer interrupt flag (step S11).

When detecting that the timer interrupt flag is set in step S8, the CPU 56 resets the timer interrupt flag (step S8).
9), a game control process is executed (step S10). According to the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the game control process is executed in the main process.
The game control process may be executed by a timer interrupt process.

FIG. 14 is a flowchart showing the game control processing in step S10. In the game control process,
The CPU 56 first performs processing for setting a display control command sent to the display control board 80 in a predetermined area of the RAM 55 (display control data setting processing: step S
21), a process of outputting a display control command is performed (display control data output process: step S22).

Next, processing for outputting the contents of the storage area for various output data to each output port is performed (data output processing: step S23). Further, an output data setting process for setting output data such as big hit information, start information, and probability variation information output to the hall management computer in the storage area is performed (step S24). Further, various abnormality diagnosis processes are performed by the self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S25).

Next, a process for updating each counter indicating each random number for determination such as a random number for big hit determination used in game control is performed (step S26).

Further, the CPU 56 performs a special symbol process (step S27). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Further, a normal symbol process is performed (step S28). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

Further, the CPU 56 includes a switch circuit 58
, The state of the gate sensor 12, the starting port sensor 17, the count sensor 23, and the winning port switches 19a and 24a are input, and it is determined whether or not each of the winning ports and the winning device has a winning (switch processing: step S29). .
The CPU 56 further performs a process of updating a display random number such as a random number that determines the type of stop symbol (step S3).
0).

Further, the CPU 56 determines that each winning opening 17 and 2
The number of prize balls is set based on the detection of 3, 19a, and 24a (step S31). That is, when a predetermined condition is satisfied, a prize ball control command is output to the prize ball control board 37. Prize ball control CP mounted on the prize ball control board 37
U drives the ball payout device 97 in response to the award ball control command.

As described above, the main processing includes the processing for determining whether or not to shift to the game control processing.
Since a flag is set to determine whether or not to shift to the game control process in the timer interrupt process based on the timer interrupt that is periodically generated by the 56 internal timers, all the game control processes are reliably executed. Is done. In other words, until all of the game control processes have been executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all processes in the game control process will be completed. ing.

In the conventional general game control process, the external game is forcibly returned to the initial state by an external interrupt that occurs periodically. To explain according to the example shown in FIG. 14, for example, even during the processing of step S31, the processing is forcibly returned to the processing of step S21. In other words, there is a possibility that the next game control process will be started before all the processes in the game control process are completed.

Here, the CPU 56 of the main board 31
Is executed in response to a flag set in a timer interrupt process based on a timer interrupt that is periodically generated by an internal timer of the CPU 56, but the signal is periodically (for example, every 2 ms). A hardware circuit which generates the signal may be provided, a signal from the circuit may be introduced to an external interrupt terminal of the CPU 56, and a flag for determining whether or not to shift to the game control process based on the interrupt signal may be set. Good.

Even in such a configuration, the flag is not determined until all the game control processes have been executed, so that it is guaranteed that all processes in the game control process have been completed. You.

FIG. 15 is a flowchart showing an example of the power failure occurrence NMI process executed in response to the NMI based on the voltage change signal from the power supply monitoring circuit of the power supply board 910. In the power failure occurrence NMI process, the CPU 56 first sets interrupt prohibition (step S41). In the power failure occurrence NMI process, a checksum generation process is performed to ensure that the contents of the RAM are preserved. If another interrupt process is performed during that process, the voltage may drop to a level at which the CPU cannot operate before the checksum generation process is completed. The setting is made so that no interrupt occurs. Steps S43 to S49 in the power failure occurrence NMI process are an example of a power supply stop process.

When a CPU having a specification that does not cause another interrupt during the interrupt processing is used, the processing in step S41 is unnecessary.

Next, the CPU 56 checks whether or not the power-off flag has already been set (step S4).
2). If the power-off flag has already been set, no further processing is performed. If the power-off flag is not set, the following power supply stop processing is executed. That is,
The processing from step S43 to step S49 is executed.

First, all output ports are turned off (step S43). If necessary, the contents of each register are stored in the backup RAM area (Step S).
44). Further, an appropriate initial value is set in the backup check data area of the backup RAM area (step S45), and exclusive OR is sequentially performed on the initial value and the data of the backup RAM area (step S4).
6), the final operation value is set in the backup parity data area (step S47). Thereafter, a power-off flag is set (step S48). Further, the RAM access is prohibited (step S49). When the power supply voltage decreases, the levels of various signal lines may become unstable and the contents of the RAM may be corrupted.
If AM access is prohibited, backup RA
The data in M will not be corrupted.

Next, the CPU 56 enters a loop process. That is, no processing is performed. Therefore, before the operation is disabled from the outside by the system reset signal from the reset IC 651 shown in FIG. 6, the operation is internally stopped. Therefore, when the power is turned off, the operation of the CPU 56 is reliably stopped. As a result, the RAM access prohibition control and the operation stop control described above can reliably prevent the contents of the RAM from being destroyed due to an abnormal operation that may occur as the power supply voltage decreases. .

In this embodiment, the power failure occurrence NM
In I processing, the program was looped in the last part,
It may be configured to issue a HALT instruction.

The power-off flag set before the RAM access is prohibited is used to determine whether or not recovery from a power failure has occurred at power-on, as described above. Further, the processing of steps S41 to S49 is performed by the CPU
This is completed before 56 receives the system reset signal from the system reset circuit 65. In other words, the detection voltage of the voltage monitoring circuit is set so as to be completed before receiving the system reset signal from the system reset circuit 65.

In this embodiment, the power-off flag is checked at the start of the power-supply stop processing. If the power-off flag has already been set, the power supply stop processing is not executed. As described above, the power-off flag is a flag indicating that the power-supply-stop processing has been completed. Therefore, for example, even if the NMI occurs again for some reason in the reset waiting loop state, the power supply stop processing will not be repeatedly executed.

However, when a CPU having a specification that does not cause another interrupt during the interrupt processing is used, the determination in step S42 is unnecessary.

FIG. 16 is an explanatory diagram for explaining a backup parity data creating method. However, FIG.
In the example shown in FIG.
The size of the data in the M area is 3 bytes. In the power failure generation process based on the power supply voltage drop, as shown in FIG. 16A, initial data (00H in this example) is set in the backup check data area. Next, "00
The exclusive OR of “H” and “F0H” is calculated, and the result is exclusive ORed with “16H”. Further, an exclusive OR of the result and “DFH” is obtained. Then, the result (“39H” in this example) is set in the backup parity data area.

When the power is turned on again, a parity diagnosis is performed in the power failure recovery processing. FIG. 16B is an explanatory diagram showing an example of the parity diagnosis. If all the data in the backup area is stored as it is, the data as shown in FIG. 16A is set in the backup area when the power is turned on again.

In the process of step S51, the CPU 5
6 is the data set in the backup parity data area of the backup RAM area (in this example, “39”).
H)) as initial data, a process of sequentially taking an exclusive OR for each data in the backup data area is performed.
If all the data in the backup area is stored as it is, the final calculation result is “00H”, that is, the same as the data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final calculation result is “00”.
H ".

Therefore, the CPU 56 compares the final operation result with the data set in the backup check data area, and if they match, determines that the parity diagnosis is normal. If they do not match, it is determined that the parity diagnosis is abnormal.

As described above, in this embodiment, the game control means is provided with the storage means (backup RAM in this example) which is backed up for a predetermined period even if the power of the game machine is turned off. At the time of insertion, the CPU 56 (specifically, a program executed by the CPU 56) is configured to perform a game state restoration process (step S5) for restoring the game state based on the backup data if the storage means is in the backup state. .

In this embodiment, the power supply monitoring circuit is mounted on the power supply board 910 as shown in FIG. 7, and the system reset circuit 65 is mounted on the main board 31 as shown in FIG. When the system reset circuit 65 generates the low-level system reset signal when the power supply voltage decreases, the power supply monitoring circuit (the power supply monitoring IC 902 in this example) outputs the low-level NMI interrupt signal. It is set to be later than when it occurs. Further, a low-level system reset signal from the system reset circuit 65 is input to a reset terminal of the CPU 56.

Then, the CPU 56 enters a loop state after executing a power failure generation process (power supply stop process) based on a voltage change signal from a power supply monitoring means (power supply monitoring IC 902) due to a power supply voltage drop. , In a loop state, a reset state is entered. That is, the operation of the CPU 56 is completely stopped. Below the + 5V power supply voltage value, the normal operation of the CPU 56 cannot be ensured (that is, a state in which the operation cannot be managed occurs), but the CPU 56 is in a reset state while the power supply that can operate normally is supplied. In addition, abnormal operation based on indefinite data is prevented.

As described above, in this embodiment, the CPU
56 is configured to enter a loop state in response to the input of the detection output from the power supply monitoring circuit and to be reset in response to the input of the detection output from the system reset circuit 65. Therefore, when the power is turned off, the data is reliably stored, thereby preventing the player from being disadvantaged.

In this embodiment, the power supply monitoring I
Although the C902 and the system reset circuit 65 monitor the same power supply voltage, they may monitor different power supply voltages. For example, the power supply monitoring circuit of the power supply board 910 has +30 V
Monitors the power supply voltage and sets the system reset circuit 65 to + 5V
The power supply voltage may be monitored. The threshold level of the system reset circuit 65 (system reset) is set so that the timing at which the system reset circuit 65 generates the low-level system reset signal is later than the timing at which the power supply monitoring circuit generates the NMI interrupt signal. The voltage level at which a signal is generated is set. For example, the threshold is 4.25V. 4.25 V is a voltage lower than the normal voltage, but a voltage at which the CPU 56 can operate for a while. The power supply monitoring circuit adjusts the delay time (in this example, the capacitance of the capacitor) of the delay means provided in the system reset circuit 65 to determine when the system reset circuit 65 generates a low-level system reset signal. You may make it delay with respect to the timing which generates an interrupt signal.

In the above embodiment, the CPU 56
Detects an NMI interrupt signal from the power supply board (NMI interrupt signal from the power supply monitoring means) via a non-maskable interrupt terminal (NMI terminal), but detects the NMI interrupt signal as a maskable interrupt terminal. (IRQ terminal). In that case, the power supply stop processing is executed in the interrupt processing (IRQ processing). Further, an NMI interrupt signal from the power supply board via the input port may be detected. In that case, the input port is monitored in the main processing.

When an interrupt signal from the power supply board is detected via the IRQ terminal instead of the NMI interrupt signal,
An IRQ interrupt mask may be set at the start of the game control process in step S10 of the main process, and the IRQ interrupt mask may be released at the end of the game control process.
In such a case, an interruption occurs before and after the start of the game control process, so that the game control process is not interrupted halfway. Therefore, there is no possibility that the command transmission is interrupted when the award ball control command is transmitted to the award ball control board 37 or the like. Therefore, even when a power failure occurs, the transmission of the prize ball control command or the like is surely completed.

Hereinafter, the game state restoring process will be described. First, in this embodiment, the CP of the main substrate 31
A display control command, a sound control command, and a lamp control command that the U56 sends to the display control board 80, the sound control board 70, and the lamp control board 35 will be described.
Each control command is determined to be sent in accordance with the progress of the game in the special symbol process process (step S27) in the game control process shown in FIG. 14, and specific data is displayed in the display control data setting process (step S21). Is set, and is transmitted by being output from the output port in the display control data output process (step S22).

FIG. 17A is an explanatory diagram showing an example of the transmission timing of each control command relating to the symbol variation in the variable display section 9. In this embodiment, the C
When starting the symbol change, the PU 56 sends a change start command to each of the display control board 80, the sound control board 70, and the lamp control board 35. To the display control board 80, a symbol designating command indicating a fixed symbol of the middle left and right symbols is further transmitted.

When the symbol variation is determined, a variation stop command is sent to each of the display control board 80, the sound control board 70, and the lamp control board 35.
Each CPU mounted on the display control board 80, the sound control board 70, and the lamp control board 35 performs display control, sound generation control, and lamp lighting control according to the variation mode specified by the variation start command. The change start command includes information indicating the change time.

FIG. 17B is an explanatory diagram showing an example of the transmission timing of each control command relating to the big hit game executed when the display result of the variable display section 9 is a predetermined big hit symbol. In this embodiment, the CPU of the main board 31
56 sends a big hit start command to each of the display control board 80, the sound control board 70, and the lamp control board 35 at the start of the big hit game. After a lapse of a predetermined time, a one-round (1R) designation command is transmitted. When each CPU mounted on the display control board 80, the sound control board 70, and the lamp control board 35 receives the big hit start command, it performs display control, sound generation control, and lamp lighting control at the start of the big hit. When a one-round designation command is received, display control, sound generation control, and lamp lighting control during a big hit are performed. However, the display control board 80
CPU performs the first round of display.

Thereafter, the CPU 56 of the main board 31 sequentially sends commands indicating each round to the display control board 80. The CPU of the display control board 80 performs corresponding display control according to these commands.

At the end of the big hit game, the CPU 56 of the main board 31 sends a big hit end command to each of the display control board 80, the sound control board 70, and the lamp control board 35. Then, after a predetermined time has elapsed, a normal screen display command is transmitted. Upon receiving the normal screen display command, each electric component control means changes the control state to a game waiting state.

FIG. 18 is a flowchart showing an example of the game state restoring process performed in the power failure restoring process shown in FIG. In this example, if it is necessary to restore the contents of the register, the CPU 56 restores the value stored in the backup RAM to the register (step S61). Then, the game state at the time of the power failure is confirmed based on the data stored in the backup RAM. For example, the gaming state can be confirmed by the value of the special symbol process flag corresponding to the progress of the special symbol process.

If the game state is changing the symbol (step S62), control is performed to send a change start command to the display control board 80, the sound control board 70, and the lamp control board 35 (step S63). If the gaming state is a jackpot game (step S64), the last transmitted control command before the power failure is displayed on the display control board 8.
0, control to send to the sound control board 70 and the lamp control board 35 is performed (step S65). When the game state is other than the above, for example, the normal screen display command is transmitted to the display control board 80 and the sound control board 7.
0 and control to send to the lamp control board 35 is performed (step S66). In addition, for example, the state of the variable prize ball device 15 when the big hit is in progress is automatically performed in a later game control process because the data in the RAM is stored.

Here, the game state restoring processing program is configured to return to the main processing when the game state restoring processing ends, but the stack area pointed to by the stack pointer stored in the power supply stop processing is set. The address stored in the backup RAM area (in the backup RAM area) (the address executed when the NMI interrupt occurs when the power is turned off) may be returned.

FIG. 19 is an explanatory diagram showing an example of the control state when the power is restored after a power failure has occurred. In FIG. 19, the variable display state is realized by the CPU (display control means) of the display control board 80, and the sound state is set by the sound control board 7
0 is realized by the CPU (sound control means), and the state of the lamp is controlled by the CPU (lamp control means) of the lamp control board 35.
It is realized by.

FIG. 19 (A) shows an example in which the power is restored after a power failure occurs during the symbol change. In this case, when the power is restored, a change start command is sent from the main board 31 (step S63 in FIG. 18). Since the change start command is a command sent at the start of the symbol change,
The states of the variable display control, the sound control, and the lamp control return to the states at the start of the change. In this embodiment, the fluctuation start command includes information for specifying the fluctuation time, and the main board 3
After transmitting the fluctuation start command, the first CPU 56 does not transmit anything (except for the symbol designation command) until the finalization command at the end of fluctuation (fluctuation stop command). Therefore, if a power failure occurs during the symbol change, the change cannot be restarted from the state in the middle of the change, but the display control, sound control, and lamp control are synchronized by resending the change start command. Return to

In the main board 31, various parameters used at the start of the fluctuation are stored in the backup RAM. Therefore, the display results (fixed symbols) and the like in the fluctuations after the restoration of the power supply are the same as the display results and the like that would have been made in the fluctuations interrupted by the power failure. Therefore, there is no disadvantage to the player.

FIG. 19 (B) shows an example in which the power is restored after a power failure occurs during the big hit game. In this case, when the power is restored, the command sent from the main board 31 to the display control board 80, the sound control board 70, and the lamp control board 35 last before the power failure is sent again (step S65 in FIG. 18). Therefore, the sound control and the lamp control return to the control state during the big hit game. In addition, the display control also returns to the state performed at the time of the power failure.

In the main board 31, various parameters during the big hit game (number of times of opening the special winning opening, number of winning balls of the special winning opening, etc.) are stored in the backup RAM. Therefore, since the game state for the player also returns to the state before the power failure, there is no disadvantage to the player.

In the above embodiment, the case has been described where the game control means performs the data saving processing and the recovery processing. However, the RAM in the prize ball control means, the voice control means, the lamp control means and the display control means has been described.
May be backed up by a power source, and the prize ball control means, the display control means, the sound control means, and the lamp control means may also perform the processing described above. However, the prize ball control means, the display control means, the sound control means, and the lamp control means do not need to perform the command transmission processing at the time of restoration.

In this embodiment, in the power failure occurrence processing (power supply suspension processing), when the power supply interruption flag indicating that the power supply suspension processing has been already executed is set, the power supply suspension processing is performed. It is configured not to execute processing. In the process of turning off the power, NMI may occur again. Then, if the power-off flag is not checked in the power failure occurrence processing, the N
The power supply stop processing is executed again by the MI.

In the normal power supply stop processing executed first, for example, processing for storing the contents of the register in the backup RAM is performed (step S4 in FIG. 15).
4). Since the power supply voltage gradually decreases in the state of waiting for reset after the normal power supply stoppage processing executed first, the contents of the register may be destroyed.
That is, the register value may have changed from the state at the time when the power-off was detected (when NMI first occurred). If the power supply stop processing is executed again in such a state, a value different from the register value in the state at the time when the power-off is detected is stored in the backup RAM. Then, in the power failure recovery processing executed at the time of power recovery, a value different from the register value in the state at the time when the power failure is detected is restored to the register. As a result, there is a possibility that a game state different from the game state when the power is turned off is reproduced.

Next, the operation of the prize ball control means when a power failure occurs will be described. FIG. 20 is a block diagram showing an example of a configuration around the CPU 371 for controlling the prize ball for power supply monitoring and power supply backup. As shown in FIG. 20, the NMI interrupt signal from the power supply monitoring circuit (power supply monitoring means) mounted on the power supply board 910 is transmitted to the prize ball control CPU 371.
Are input to the non-maskable interrupt terminal (NMI terminal). Accordingly, the CPU 371 for controlling the prize ball can confirm the occurrence of the power-off or the power-on by the NMI processing.

While power is not supplied from the + 5V power supply which is the drive power supply for the prize ball control CPU 371 and the like, at least a part of the built-in RAM of the prize ball control CPU 371 uses the backup power supplied from the power supply board 910 as a backup. Backed up by connecting to the terminal,
The contents are preserved even if the power to the gaming machine is turned off. Then, when the +5 V power supply is restored and the voltage value of the +30 V power supply reaches a predetermined value (+9 V in this example), the output of the system reset circuit 933 goes to a high level and the system reset is released. The CPU 371 returns to a normal operation state. At that time, since the necessary data is backed up, the payout control can be restarted from the state at the time of the power failure at the time of recovery from a power failure or the like.

In the award ball control board 37, the NMI interrupt signal from the power supply monitoring means is input to the award ball control CPU 371 through the input buffer circuit 930. Here, the 74HC244 is illustrated as the input buffer circuit 930, but any circuit having an input buffer function may be used. Also, the input buffer circuit 9
Reference numeral 30 denotes an irreversible element that allows a signal to pass only in the direction from the power supply board to the inside of the prize ball control board 37.

In the configuration shown in FIG. 20, the prize ball control board 37
Is equipped with a system reset circuit 933. The system reset circuit 933 has a voltage of +30 V equal to the power supply voltage monitored by the power supply monitoring circuit of the power supply board 910.
The power supply voltage is monitored, and when the voltage value falls below a predetermined value, a low-level system reset signal is generated. Further, the system reset circuit 933 monitors the voltage of the +30 V power supply, and raises the system reset signal to a high level when the voltage value becomes equal to or higher than a predetermined value at the time of, for example, restoration of the power supply. The detection voltage of the system reset circuit 933 (the voltage at which the system reset signal is output or the voltage at which the system reset signal rises to a high level) is detected by the power supply monitoring circuit mounted on the power supply board 910. Lower than the voltage.

In this embodiment, system reset circuit 933 includes delay means. A capacitor is externally connected to the reset IC 934, and the timing at which the output becomes high level is determined according to the capacitance of the capacitor. Therefore, if the capacity of the capacitor is set to a value that generates a predetermined delay time, when the power is turned on, the output becomes low level for a predetermined time determined by the capacity of the external capacitor,
After a lapse of a predetermined time, the output goes high. Also,
The reset IC 934 introduces a power supply voltage of VSL, which is a power supply voltage equal to the power supply voltage monitored by the power supply monitoring circuit, to a voltage change monitoring terminal, monitors the voltage of the terminal, and sets a low level when the voltage value falls below a predetermined value. Generates a system reset signal. The CPU 371 is connected to the system reset circuit 9
33 is in a reset state (inactive state) when the system reset signal from the system reset circuit 33 is at a low level, and is set after the system reset signal from the system reset circuit 933 is in a high level. )become.

As described above, in this embodiment, since the system reset circuit 933 is provided with the delay means, the timing at which the system reset signal rises to a high level is delayed, and the voltage change signal (NMI Interrupt signal) rises to a high level, the system reset signal rises to a high level, and the NMI interrupt signal rises to a high level before the system reset signal rises to a high level, thereby turning off the power. It is possible to prevent the processing from being executed.

FIG. 21 shows the main board 31 to the prize ball control board 3.
7 is an explanatory diagram showing an example of a bit configuration of a prize ball control command transmitted to No. 7; FIG. As shown in FIG. 21, the upper four bits in one byte are used as a control designator, and the lower four bits are used as an area indicating the number of prize balls.

As shown in FIG. 22, when the bits 7, 6, 5, and 4 are "0, 1, 0, 0" in the control specifying section, it indicates that the command is a payout number specifying command. ,
"0, 1" indicates a payout designation command.
The payout number designation command is sent to the prize ball control board 37 immediately after the CPU 56 of the main board 31 detects a winning.

Bits 7, 6, 5, and 4 are "1, 0, 0,
The out-of-ball designation command of “0” is transmitted from the main board 31 when it is detected that there is no more supply ball. The firing stop designation command in which the bits 7, 6, 5, and 4 are "1, 0, 0, 1" indicates that the surplus ball tray 4 is full and the full switch 48 is turned on (the full tank state). (When the flag is turned on).

The award ball control command is output from the main board 31 to the award ball control board 37 as 1-byte (8 bits: award ball control commands D7 to D0) data. The winning ball control commands D7 to D0 are output in positive logic. When the award ball control commands D7 to D0 are output, a negative logic award ball control INT signal is output.

In this embodiment, as shown in FIG. 23, when the prize ball control commands D7 to D0 are output from the main board 31, the prize ball control INT signal goes low for 5 μs or more. The prize ball control INT signal is transmitted to the prize ball control board 37.
Is connected to the interrupt terminal of the CPU 371 for controlling the prize ball. Therefore, when there is an interrupt, the award ball control CPU 371 transmits the award ball control commands D7 to D0 to the main board 31.
And recognizes that it has been sent from the CPU, and performs a prize ball control command receiving process in the interrupt process.

The command configuration shown in FIG. 21 is an example, and another configuration may be used. For example, the upper and lower parts in one byte may be reversed from the configuration shown in FIG. Further, the award ball control command may have a 2-byte configuration. In this case, the mode of the payout control (designation of the number of payouts and the specification of whether or not the payout is possible) is specified in the first byte, and information on the mode (instruction of the number of payouts and the permission / non-availability of payout) is specified in the second byte.
May be specified. Further, information indicating whether the byte is the first byte or the second byte may be included in the eight bits. For example, if the first byte is “F0H”, the payout number designation is indicated, and the specific number is indicated by the second byte (for example, at least bit 7 of the second byte is “0”).
If the first byte is “FFH”, the payout mode is indicated. If the second byte is “00H”, the payout is permitted. If the first byte is “01H”, the payout is prohibited.

FIG. 24 is a flowchart showing the main processing of the award ball control CPU 371. In the main processing,
The winning ball control CPU 371 first performs an initial value setting process such as clearing the RAM area (step S701).
If data is set in the RAM area (backup RAM area) of the built-in RAM where the power is backed up, those areas are not cleared. After that, in this embodiment, the CPU 371 for controlling the prize ball.
Shifts to a loop process for checking the monitoring of the timer interrupt flag (step S702).

In the initialization processing in step S701, when the value of the total number storage described later is not 0, the non-backup RAM area is cleared. Then, setting for restarting the prize ball is performed. For example, a flag during processing of a prize ball is set. If the backup RAM area is an area irrespective of the number of prize balls, those addresses may be designated and cleared. Furthermore, in addition to these processes, initial settings of a timer register provided in the CPU for controlling a prize ball 371 so that a timer interrupt is periodically performed every 2 ms (setting that the timeout is 2 ms and setting of the repetition timer operating) ) Is performed. That is, a process of activating a timer interrupt and a process of setting a timer interrupt interval are executed.

Therefore, in this embodiment, the internal timer of the CPU 371 for controlling the prize ball is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. Then, as shown in FIG. 25, when a timer interrupt occurs, the CPU 371 for controlling the prize ball.
Sets the timer interrupt flag (step S71)
1).

The CPU 371 for controlling the prize ball controls step S7.
In 02, when it is detected that the timer interrupt flag has been set, the timer interrupt flag is reset (step S703), and a prize ball control process and a ball lending control process are executed (steps S705 and S706). According to the above control, in this embodiment, the prize ball control process and the ball lending control process are started every 2 ms. In this embodiment, only the flag is set in the timer interruption processing, and the prize ball control processing and the like are executed in the main processing. However, the prize ball control processing and the like may be executed in the timer interruption processing.

FIG. 26 is an explanatory diagram showing an example of use of the RAM built in the CPU 371 for controlling a prize ball. In this example,
In the backup RAM area, a total number storage (for example, 2 bytes) and a rental ball number storage are formed. The total number storage stores the total number of payouts instructed from the main board 31 side. The lending ball number storage stores the number of unpaid ball lending.

FIG. 27 is a flowchart showing a prize ball control command receiving process by the interrupt process. The award ball control INT signal from the main board 31 is input to the interrupt terminal of the award ball control CPU 371. Therefore, when the award ball control INT signal from the main board 31 is turned on, the award ball control CP
An interrupt is made to U371, and the reception processing of the award ball control command shown in FIG. 27 is started.

In the process of receiving the award ball control command, the award ball control CPU 371 first reads 1-byte data from the input port assigned to the input of the award ball control command data (step S852). If the read data is a payout number instruction command (step S8)
53), the number specified by the payout number instruction command is added to the total number storage (step S855). Otherwise, a communication end flag is set (step S85).
4). In this example, the communication end flag is a flag indicating that a command other than the payout number instruction command has been received.

As described above, the CPU 371 for controlling the prize ball mounted on the prize ball control board 37 is the CPU 5 of the main board 31.
The number of award balls included in the payout number instruction command sent from 6 is stored in the backup RAM area (total number storage).

FIG. 28 shows a prize ball control process (step S71).
It is a flowchart which shows 1). In the prize ball control processing, the prize ball control CPU 371 checks whether or not the total number storage is not 0 (step S511). If the total number storage is not 0, the award ball control CPU 371 performs an award ball payout process (step S512). In the prize ball payout process, if the payout motor 289 is not turned on, it is turned on, and the detection output of the prize ball count switch 301A is used to confirm whether or not the game balls have been paid out. When it is confirmed that one payout has been made (step S513), the value of the total number storage is decremented by one (step S513).
514). When the value of the total number storage becomes 0 (step S515), the payout motor 289 is turned off (step S516).

The contents of the total number storage are retained by the backup power supply of the power supply board 910 for a predetermined period even if the power supply of the gaming machine is turned off. Therefore, when the power is restored during the predetermined period, the award ball control CPU 371 can continue the award ball payout process based on the contents of the total number storage.

When the power is turned on, the CPU 371 for controlling the prize ball can determine whether to perform the normal initialization processing or restore the state during the prize ball simply by checking the data in the backup RAM area. That is, with a simple judgment,
The prize ball processing can be restarted for the unpaid prize balls.

The award ball control CPU 371 manages the number of award balls instructed from the main board 31 as a total number in the total number memory, but the number of award balls (for example, 15, 10 or 6).
). For example, a number counter corresponding to each prize ball number is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by one. When the payout of each prize ball is completed, the corresponding number counter is decremented by one. Also in this case, each number counter is formed in the backup RAM area. Therefore, even if the power of the gaming machine is turned off, if the power is restored during the predetermined period, the prize ball control CPU 371 can continue the prize ball payout process based on the content of each number counter.

FIG. 29 shows a ball lending control process (step S7).
It is a flowchart which shows 06). In the ball lending control processing, the prize ball control CPU 371 checks whether or not a prize ball is being paid out (step S531). If the prize balls are not being paid out, it is confirmed whether or not the stored number of lending balls is not 0 (step S532). If the lending ball number storage is not 0, the award ball control CPU 371 performs a ball lending process (step S533). In the ball lending process, the payout motor 2
If 89 has not been turned on, it is turned on, and it is checked whether or not a game ball has been paid out based on the detection output of the ball lending count switch 301B. Then, when it is confirmed that one payout has been made (step S534), the value of the stored number of lending balls is decremented by one (step S535). Further, when the value of the number of stored lending balls becomes 0 (step S5).
36), and turns off the payout motor 289 (step S53).
7). In this embodiment, the prize ball and the ball lending are performed by the same payout device.

Next, it is confirmed whether or not there is a ball lending request from the card unit 50 (step S538). If there is a request, the number corresponding to the requested unit number is added to the value of the lending ball number storage (step S539). .

The contents of the lending ball number storage are retained by the backup power supply of the power supply board 910 for a predetermined period even if the power of the gaming machine is turned off. Therefore, when the power is restored during the predetermined period, the prize ball controlling CPU 371 can continue the ball lending process based on the content of the lending ball number storage.

Note that the prize ball controlling CPU 371 manages the number of lent balls requested by the card unit 50 in units (for example, in units of 100 yen) as the total number in the lent ball number storage. Good. For example, a ball lending counter is provided, and when a ball lending request is issued, the ball lending counter is incremented by one. When the payout of the number of units is completed, the ball lending counter is decremented by one. Also in that case, the ball lending counter is formed in the backup RAM area. Therefore, even if the power of the gaming machine is turned off, if the power is restored during the predetermined period, the prize ball controlling CPU 371 can continue the ball lending process based on the content of the ball lending counter.

FIG. 30 is a flowchart showing a power failure occurrence interruption process executed by the award ball control CPU 371 in response to an interruption from the power supply monitoring circuit. When the power supply monitoring IC 902 of the power supply board 910 detects a decrease in the power supply voltage, the voltage change signal indicates a voltage decrease, and the power failure occurrence interrupt processing is started. In the power failure occurrence interrupt processing, the prize ball control CPU 371 sets the interrupt prohibition (step S80).
1) Set the RAM access prohibited state (step S
802), and enters a loop process. That is, no processing is performed.

Therefore, the power supply monitoring IC shown in FIG.
Before being externally disabled (system reset) by the system reset signal from 934, the internal operation is stopped. Thus, the operation of the award ball control CPU 371 is reliably stopped when the power is turned off.

In this embodiment, the power failure occurrence NM
In I processing, the program was looped in the last part,
It may be configured to issue a HALT instruction. If a CPU having a specification that does not cause another interrupt during the interrupt processing is used, the processing in step S801 is unnecessary.

FIG. 31 is a flowchart showing a part of the initialization process (step S701) executed by the CPU 371 for controlling the prize ball when the power is turned on. When the power is turned on or the power is restored, the CPU 371 for controlling the prize ball
First, it is checked whether the value of the total number storage or the lending ball number storage formed in the backup RAM area is not 0 (step S901). If it is 0,
Since there was no unpaid prize ball when the power was last turned off, normal initialization processing is performed. That is, the register and all RAM areas are cleared (step S903),
Initialize the stack pointer (step S90)
4).

If the value of the storage of the total number or the storage of the number of lending balls is not 0, the address is designated to clear the register and the non-backup RAM area (step S90).
5). Then, setting for restarting the prize ball is performed. For example,
The in-prize ball processing flag is set (step S90).
6). If the backup RAM area is an area irrespective of the number of prize balls, those addresses may be designated and cleared.

As described above, the CPU 371 for controlling the prize ball
When the power is turned on, it is possible to determine whether to perform the normal initial setting process or to restore the state during the prize ball only by checking the data in the backup RAM area. In other words, the prize ball processing can be restarted for the unpaid prize balls by a simple judgment.

Note that the CPU 371 for controlling the prize ball may determine whether or not to perform the initialization processing based on the power-off flag, similarly to the CPU 56 of the main board 31. In addition, the main substrate 31
As in the case of the CPU 56, it is possible to ensure the storage of the stored contents by using a parity check code.

In this embodiment, the prize ball control C
PU 371 is a non-maskable external interrupt terminal (NMI terminal)
, The NMI interrupt signal from the power supply board (NMI interrupt signal from the power supply monitoring means) is detected, but the NMI interrupt signal may be introduced to a maskable interrupt interrupt terminal (IRQ terminal). In this case, the power outage interruption processing shown in FIG. 30 is executed by the IRQ processing. Further, an NMI interrupt signal may be detected through an input port. In that case, the input port is monitored in the main processing executed by the award ball control CPU 371.

In the above embodiment, the power supply monitoring circuit is provided on the power supply board 910.
It may be provided on an electric component control board such as 1 or the prize ball control board 37. When an electric component control board on which a power supply circuit is mounted is configured, the power supply monitoring circuit is not mounted on the power supply board.

FIG. 32 is a block diagram showing another configuration example around the CPU 56 for power supply monitoring and power supply backup. As shown in FIG. 32, the voltage change signal from the power supply monitoring circuit (power supply monitoring means) is supplied to the non-maskable interrupt terminal (NMI terminal) of the CPU 56 via the buffer circuit 900.
It is connected to the. The power supply monitoring circuit is a circuit that monitors a voltage of any one of various DC power supplies used by the gaming machine and detects a power supply voltage change. In this embodiment, the power supply voltage of VSL is monitored, and a low-level voltage change signal is generated when the voltage value falls below a predetermined value. Also, VSL
The power supply voltage is monitored and a high-level voltage change signal is generated when the voltage value exceeds a predetermined value. VSL is the highest voltage among DC voltages used in gaming machines, and is +30 V in this example. Therefore, the CPU 56 can confirm occurrence of power interruption or power restoration by the interrupt processing.

Although an initial reset circuit 65 is also shown on the electric component control board, in this embodiment, the initial reset circuit 65 is different from the power supply monitoring circuit provided on the power supply board in this example. Power supply monitoring circuit (other power supply monitoring means). That is, the reset IC 651
When the power is turned on, the output is set to a low level for a predetermined time determined by the capacity of an external capacitor (delay means), and the output is set to a high level after a predetermined time has elapsed. Also, the reset IC 651 introduces a power supply voltage of VSL, which is a power supply voltage equal to the power supply voltage monitored by the power supply monitoring circuit, to the voltage change monitoring terminal, monitors the voltage of the terminal, and when the voltage value falls below a predetermined value. Generates a low-level voltage change signal.
As shown in FIG. 32, this voltage change signal is the same output signal as the reset signal.

As shown in FIG. 32, reset IC 651
Is input to the NAND circuit 947 and also to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. When the input to the clear terminal goes low, the counter IC 941 counts the clock signal from the oscillator 943.
The Q5 output of the counter IC 941 is output to the NOT circuit 9
45, 946 and input to the NAND circuit 947. The Q6 output of the counter IC 941 is input to a clock terminal of a flip-flop (FF) 942.
The D input of the flip-flop 942 is fixed at a high level, and the Q output is input to an OR circuit (OR circuit) 949. The other input of the OR circuit 949 is connected to the NAND circuit 9.
The output of 47 is introduced via NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56.

For example, the detection voltage of the power supply monitoring circuit (the voltage at which the voltage change signal is output) is set to +22 V
And the detection voltage of the other power supply monitoring circuit is set to + 9V. In such a configuration, the power supply monitoring circuit and the other power supply monitoring circuits monitor the voltage of the same power supply VSL, so that the timing at which the voltage monitoring circuit outputs the voltage change signal and the other voltage monitoring circuits The difference in the timing of outputting the voltage change signal can be reliably set to a desired predetermined period. The desired predetermined period is a period from when the power supply stop processing is started in response to the voltage change signal from the power supply monitoring circuit to when the power supply stop processing is completely completed.

In this example, the detection condition that the power supply monitoring means outputs the detection signal is that the power supply voltage is +22 V
That is, the detection condition that the other power supply monitoring means outputs the detection signal is that the + 30V power supply voltage has been reduced to + 9V. However, the voltage value used here is an example, and another value may be used.

However, although the monitoring range is narrowed, it is also possible to use a + 5V power supply voltage as the monitoring voltage of the voltage monitoring circuit and other voltage monitoring circuits. Also in that case, the detection potential of the voltage monitoring circuit is set higher than the detection potentials of the other voltage monitoring circuits.

While power is not supplied from the + 5V power supply which is the driving power supply of the CPU 56 and the like, at least a part of the RAM is backed up by the backup power supply supplied from the power supply board, and the contents are maintained even if the power supply to the gaming machine is cut off. Is saved. When the + 5V power supply is restored, the system reset signal from the system reset circuit 65 is set to the high level, and the system reset is released.
After that, the CPU 56 returns to the normal operation state. At that time, since the necessary data is backed up, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovering from a power failure or the like.

FIG. 33 is a timing chart showing output signals of reset IC 651 of system reset circuit 65 shown in FIG. 32 and peripheral ICs. As shown in FIG. 33, the output of the reset IC 651 has a power supply voltage level exceeding a predetermined value (a level at which the normal operation of the CPU 56 can be ensured, for example, +9 V because the CPU 56 can operate at +5 V). And become high level. When the output of the reset IC 651 becomes high level,
Since the clear state of the counter IC 941 is released, the counter IC 941 starts counting the output clock signal of the oscillator 943. The oscillation frequency of the oscillator 943 is, for example, 11.776 MHz. Note that the output clock signal of the oscillator 943 is also supplied to an external clock terminal of the CPU 56.

When counter IC 941 counts 16 clocks, Q5 output rises. When 32 clocks are counted, the Q6 output rises to a high level.
When the Q6 output of the counter IC 941 rises, FF9
The output at 42 goes high. The IC 947 inverts the logical product of the Q6 output of the counter IC 941 and the output of the reset IC 651, and outputs a signal as shown in FIG. The OR circuit 949 outputs an I signal for inverting the output of the IC 947.
The logical sum of the output of C948 and the output of FF942 is obtained, and a signal as shown in FIG. 33 is output.

Therefore, when the power of the gaming machine is turned on, the CPU
A signal is supplied to the reset terminals 56 so that the reset state (high level) is set once and then the reset state (low level) is set again. That is, when the power is turned on, a low-level signal for resetting the CPU 56 is generated twice. It can also be said that the high level indicating reset release has occurred twice. As a result, even if the CPU 56 is not activated by a change from low level to high level indicating the first reset release, it can be reliably activated by a second change from low level to high level.
Therefore, when the power of the gaming machine is turned on, the game control is reliably started.

The width of the high level pulse (corresponding to the reset release state) and the width of the low level pulse (corresponding to the reset state) output from the IC 949 are determined by the counter IC 941.
Can be set arbitrarily by changing the output terminal of However, the width of the high-level pulse output from the IC 949 is preferably several clocks (for example, four clocks) of the output clock of the oscillator 943 that is also supplied to the CPU 56, but in this example, it is 16 clocks. Has become. The width of the low-level pulse output by the IC 949 is preferably equal to or more than several clocks (for example, 4 clocks) of the output clock of the oscillator 943, but in this example, it is 16 clocks. By adjusting the first high level period of the IC 949, the voltage change signal from the power supply monitoring circuit can be kept at the high level when the output of the IC 949 rises for the second time. Therefore, the embodiment shown in FIG. 32 can also guarantee that the NMI interrupt signal has risen at the time when the CPU 56 starts executing the control program.

In some cases, the CPU 56 is configured to perform a predetermined startup process such as a security check before starting the original control process when the reset state is released and the operation is started. Then, the end point (falling point) of the high-level pulse output by the IC 949
Is desirably before completion of a predetermined startup process (before starting the original control process). Otherwise, the output of the IC 949 rises, a predetermined startup process is performed, and the output of the IC 949 becomes low level after the original control process is started. This is because the situation is reset. I
The end point (falling point) of the high-level pulse output by C949 is, for example, 100 ms from the rising point.
Within the circuit configuration shown in FIG. 32, it is preferably within 100 ms.

When the power is turned off, the reset IC 651
VSL (+ 30V power supply voltage in this example)
Is lower than a predetermined value (+9 V in this example), the output of the reset IC 651 becomes low level. Then F
A low level is input to the clear terminal (CLR) of F942, and the Q output of FF942 becomes low level. Therefore, O
The output of the R circuit 949 becomes low level, and the level indicating the reset state is supplied to the reset terminal of the CPU 56. That is, in the circuit configuration shown in FIG. 32, when the output of the reset IC 651 becomes low level, the CP
The input state of the reset terminal of U56 is fixed at a low level. In other words, when the power is turned off, two reset pulses are not supplied to the CPU 56.

In this embodiment, a circuit configuration as shown in FIG. 32 is used to create a signal state such as the reset signal shown in FIG. 33. Other circuit configurations may be used to create.

FIG. 34 is a timing chart showing the state of the power supply drop and the NMI interrupt signal (here, the power-off signal) when the power of the gaming machine is turned off. When the power supply to the gaming machine is cut off, the voltage value of VSL, which is the highest DC power supply voltage, gradually decreases. In this example, when the voltage drops to +22 V, the power monitoring I
A power-off signal (voltage change signal) is output from C902 (becomes low level).

The power-off signal is sent to the electric component control board (FIG. 34).
In the example shown in FIG. 3, the CPU 56 and the CPU 371 for controlling the prize ball
Input to MI terminal. CPU 56 and prize ball control C
The PU 371 executes predetermined power supply stop processing by the above-described NMI processing.

When the voltage value of VSL further decreases to a predetermined value (+9 V in this example), the output of the reset IC 651 mounted on the main board 31 or the prize ball control board 37 becomes low level, and the CPU 56 And prize ball control C
PU 371 enters a system reset state. Note that CP
The U56 and the award ball control CPU 371 have completed the power supply stop processing before the system is reset.

When the voltage value of VSL further decreases and falls below a voltage capable of generating Vcc (+5 V for driving various circuits), each circuit cannot operate on each substrate. However, at least on the main board 31 and the prize ball control board 37, the power supply stop processing is executed, and the CPU
56 and the award ball control CPU 371 are in a system reset state.

FIG. 35 is a block diagram showing another configuration example around the CPU 371 for controlling the prize ball for monitoring and backing up the power supply. As shown in FIG. 35, a voltage change signal from a power supply monitoring circuit (power supply monitoring means) is connected to a non-maskable interrupt terminal (NMI terminal) of the CPU 371 for award ball control via a buffer circuit 960. The power supply monitoring circuit is a circuit that monitors a voltage of any one of various DC power supplies used by the gaming machine and detects a power supply voltage change. In this embodiment, the power supply voltage of VSL is monitored, and a low-level voltage change signal is generated when the voltage value falls below a predetermined value. Further, the power supply voltage of VSL is monitored, and a high-level voltage change signal is generated when the voltage value exceeds a predetermined value. VSL is the highest voltage among DC voltages used in gaming machines, and is +30 V in this example. Accordingly, the CPU 371 for controlling the prize ball can confirm occurrence of power interruption or restoration of power supply by the interrupt processing.

Although an initial reset circuit 975 is also shown on the electric component control board, in this embodiment, the initial reset circuit 975 is different from the power supply monitoring circuit provided on the power supply board in this example. Power supply monitoring circuit (other power supply monitoring means). That is, the reset IC 97
6 is an external capacitor (delay means) when the power is turned on.
The output is set to the low level only for a predetermined time determined by the capacity, and after the predetermined time elapses, the output is set to the high level. Also, the reset IC 976 introduces a power supply voltage VSL, which is a power supply voltage equal to the power supply voltage monitored by the power supply monitoring circuit, to the voltage change monitoring terminal, monitors the voltage of the terminal, and when the voltage value falls below a predetermined value. Generates a low-level voltage change signal. As shown in FIG. 35, this voltage change signal is the same output signal as the system reset signal.

As shown in FIG. 35, reset IC 976
Is input to the NAND circuit 987 and also to the clear terminal of the counter IC 981 via the inverting circuit (NOT circuit) 984. When the input to the clear terminal goes low, the counter IC 981 counts the clock signal from the oscillator 983.
The Q5 output of the counter IC 981 is output to the NOT circuit 9
85, 986 and input to the NAND circuit 987. The Q6 output of the counter IC 981 is input to a clock terminal of a flip-flop (FF) 982.
The D input of the flip-flop 982 is fixed to a high level, and the Q output is input to an OR circuit (OR circuit) 989. The other input of the OR circuit 989 is connected to the NAND circuit 9
The output of 87 is introduced via NOT circuit 988. The output of the OR circuit 989 is output to the CPU 371 for controlling the prize ball.
Connected to the reset terminal.

Then, for example, the detection voltage of the power supply monitoring circuit (the voltage at which the voltage change signal is output) is set to +22 V
And the detection voltage of the other power supply monitoring circuit is set to + 9V. In such a configuration, the power supply monitoring circuit and the other power supply monitoring circuits monitor the voltage of the same power supply VSL, so that the timing at which the voltage monitoring circuit outputs the voltage change signal and the other voltage monitoring circuits The difference in the timing of outputting the voltage change signal can be reliably set to a desired predetermined period. The desired predetermined period is a period from when the power supply stop processing is started in response to the voltage change signal from the power supply monitoring circuit to when the power supply stop processing is completely completed.

In this example, the detection condition that the power supply monitoring means outputs the detection signal is that the power supply voltage of +30 V is +22.
That is, the detection condition that the other power supply monitoring means outputs the detection signal is that the + 30V power supply voltage has been reduced to + 9V. However, the voltage value used here is an example, and another value may be used.

The predetermined value for the reset IC 976 to detect the power-off is lower than the normal voltage.
This is a voltage at which the PU 371 can operate for a while. Also, since the reset IC 976 is configured to monitor a voltage higher than the voltage (+5 V in this example) required by the prize ball control CPU 371, the prize ball control CPU
The monitoring range can be extended for the voltage required by the 371. Therefore, more precise monitoring can be performed.

While power is not being supplied from the + 5V power supply, which is the drive power supply for the prize ball control CPU 371 and the like, at least a part of the RAM is backed up by the backup power supply supplied from the power supply board, and the power supply to the gaming machine is cut off. Even if the contents are preserved. Then, when the + 5V power supply is restored, the system reset signal from the system reset circuit 975 is raised to a high level to release the system reset.
Return to normal operating state. At that time, since the necessary data is backed up, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovering from a power failure or the like.

As described above, in the present embodiment, since the delay means is provided in the system reset circuit of the electric component control means, the first high-level period of the output of the OR circuit is adjusted so that the second rise time can be adjusted. Can be delayed by delaying the rise of the system reset signal by a predetermined time, so that the system reset signal rises to a high level after the NMI interrupt signal rises to a high level. Is reliably prevented from being executed.

Also in the present embodiment, the processing as shown in FIGS. 9 and 10 can be performed by using the interrupt prohibition period during execution of the startup processing.

Also, in this embodiment, the power supply board 91
The power supply monitoring circuit mounted on the power supply 0 monitors the voltage of the highest power supply VSL among the DC voltages used in the game machine, and when the voltage of the power supply falls below a predetermined value, a voltage change signal (power cutoff detection) Signal). As shown in FIG.
At the timing when the power-off detection signal is output, the IC drive voltage is still at a voltage value that can sufficiently drive various circuit elements. Therefore, the operation time for the award ball control CPU 371 of the award ball control board 37 operating at the IC drive voltage to perform the predetermined power supply stop processing is secured.

In this case, the power supply monitoring circuit also monitors the highest voltage of the power supply VSL among the DC voltages used in the gaming machine. If the timing is such that the operation time for the electric component control means operating at the voltage to perform the predetermined power supply stop processing is secured, the monitored voltage is
It does not have to be the highest voltage of the power supply VSL. That is, if at least the voltage higher than the IC drive voltage is monitored, the power-off detection signal can be generated at a timing such that the operation time for the electric component control means to perform the predetermined power supply stop processing is secured. it can.

In this case, as described above, since the voltage to be monitored is +12 V supplied to various switches of the gaming machine such as the prize ball count switch 301A, it is possible to prevent erroneous switch-on detection when the power is turned off. Is also a voltage that can be expected. That is, it is preferable that the voltage drop can be detected before the + 12V power supply voltage, which is the voltage (switch voltage) supplied to the switch, starts to drop. Therefore, it is preferable to monitor at least a voltage higher than the switch voltage.

However, although the monitoring range is narrowed, it is also possible to use a + 5V power supply voltage as the monitoring voltage of the voltage monitoring circuit and other voltage monitoring circuits. Also in that case, the detection potential of the voltage monitoring circuit is set higher than the detection potentials of the other voltage monitoring circuits.

As described above, according to the present invention, the MNI interrupt signal is raised to the high level before the electric component control means enters the normal operation state. It can be prevented from being done.

As described above, in the present invention, the delay means is provided to delay the rising timing of the system reset signal output from the system reset circuit by a predetermined time, so that the NMI interrupt signal rises to a high level. It is possible to release the system reset later, and it is possible to reliably prevent the power-off process from being executed when the power is turned on.

Further, as described above, in the present invention, the delay means is provided to delay the rising timing of the system reset signal output from the system reset circuit by a predetermined time, so that the predetermined time delayed by the delay means is reduced. Even when the system reset signal rises to a high level before the NMI interrupt signal rises to a high level, the MNI interrupt signal rises to a high level after the system reset signal is raised to a high level. Since the time until the power is turned on can be shortened, it is possible to prevent the power-off process from being executed when the power is turned on.

Further, as described above, the present invention employs a configuration in which the NMI interrupt signal rises to a high level after the system reset is released and before the start-up processing such as the security check is completed. Before entering the valid state, the NMI interrupt signal can be set to a level at which no NMI is generated. As a result, it is possible to reliably prevent the power-off process from being performed when the power is turned on.

Furthermore, as described above, according to the present invention, the rising timing of the system reset signal is delayed by a predetermined time by the delay means, and the NMI interrupt is performed before the start-up processing such as a security check is completed after the system reset is released. With the configuration in which the interrupt signal rises to a high level, the NMI interrupt signal can be set to a level that does not generate an NMI before the interrupt is enabled. As a result, it is possible to reliably prevent the power-off process from being performed when the power is turned on.

In each of the above embodiments, the power supply monitoring means is provided on either the power supply board or the electric component control board. However, the power supply monitoring means may be provided anywhere, for example, in view of the structure of the gaming machine. Can be installed at any position according to the conditions.

In each of the above embodiments, the delay means is provided in the system reset circuit. However, the system reset signal is changed to the high level by using a signal different from the voltage change signal from the power supply monitoring circuit. The NMI interrupt signal may be caused to rise to a high level before the NMI is raised.

FIG. 36 shows a C for power supply monitoring and power supply backup in this embodiment using another signal.
It is a block diagram which shows the example of 1 structure around PU56. FIG.
As shown in FIG. 6, a voltage change signal from a power supply monitoring circuit (power supply monitoring means) mounted on the power supply board and an NMI interrupt forcing signal from a timer 920 mounted on the power supply board are connected to an AND circuit 950. Is connected to the non-maskable interrupt terminal (NMI terminal) of the CPU 56 via the. The power supply monitoring circuit is a circuit that monitors a voltage of any one of various DC power supplies used by the gaming machine 1 and detects a change (drop or rise) in the power supply voltage. The timer 920 outputs a signal for a predetermined time after the power of the gaming machine 1 is turned on. Therefore, the CPU 56 can confirm the occurrence of power interruption or power restoration by the interrupt processing.

In the main board 31, a voltage change signal from the power supply monitoring circuit is sent to the
The signal is input to one input terminal of the D circuit 950. Also, the NMI interrupt compulsory signal from the timer 920 is AND
It is input to the other input terminal of the circuit. Here, 74HC244 is exemplified as the input buffer circuit 900, but any circuit having an input buffer function may be used. Also, the input buffer circuit 90
Reference numeral 0 denotes an irreversible element that allows a signal to pass only in the direction from the power supply board side to the inside of the main board 31.

In this example, the power supply monitoring circuit monitors the +30 V power supply voltage (VSL) and generates a low-level voltage change signal when the voltage value falls below a predetermined value due to, for example, a power failure. When a low-level voltage change signal is issued by the power supply monitoring circuit, the signal from the timer 920 falls after a lapse of a predetermined time after power-on (after the voltage change signal is issued). A low-level NMI interrupt signal is issued, and power-off processing is executed. Further, the timer 920 monitors the + 5V power supply voltage, and raises the NMI interrupt compulsory signal to a high level for a predetermined time when the power is turned on. When the timer 920 causes the NMI interrupt compulsory signal to rise to a high level, the NMI interrupt signal output from the AND circuit 950 rises to a high level. The power supply monitoring circuit monitors the VSL power supply voltage and raises the voltage change signal to a high level when, for example, the power supply is restored after a power failure and the voltage value exceeds a predetermined value.
Note that the detection voltage of the power supply monitoring circuit (the voltage at which an NMI interrupt signal is output) is set to +22 V in this embodiment.
And However, the voltage value used here is an example, and another value may be used.

The main board 31 is provided with a system reset circuit 65. In this example, the system reset circuit 65 monitors the same VSL power supply voltage as the power supply monitoring circuit, and generates a low-level system reset signal when the voltage value falls below a predetermined value. Further, the system reset circuit 65 raises the system reset signal to a high level when the VSL power supply voltage exceeds a predetermined value. Note that the detection voltage of the system reset circuit 65 is, for example, + 9V.
Therefore, the detection condition under which the system reset circuit 65 outputs the low-level system reset signal is V
This means that the SL power supply voltage has dropped to + 9V. Also,
A detection condition for the system reset circuit 65 to raise the system reset signal to the high level and release the system reset is that the VSL power supply voltage has risen to + 9V. However, the voltage value used here is an example, and another value may be used.

It is to be noted that +5 which is the driving power source of the CPU 56 and the like is used.
While power is not being supplied from the V power supply, at least a portion of the RAM is backed up by a backup power supply supplied from a power supply board, and its contents are preserved even when the power to the gaming machine is cut off. Then, when the + 5V power supply is restored and the VSL power supply voltage becomes equal to or higher than a predetermined value (+ 9V in this example), the system reset signal is raised to a high level by the system reset circuit 65.
Returns to a normal operation state after performing a predetermined startup process such as a security check.

FIG. 37 is a block diagram showing an example of a configuration of a power supply board 910 of a gaming machine in this embodiment using another signal. The power supply board 910 is installed independently of the electric component control boards such as the main board 31, the display control board 80, the sound control board 70, the lamp control board 35, and the prize ball control board 37, and controls each electric component control board in the gaming machine. And the voltages used by the mechanical components. In this example, AC24V,
DC + 30V, DC + 21V, DC + 12V and DC
+ 5V is generated. Further, the capacitor 916 serving as a backup power supply is charged from DC + 5V, that is, a power supply line for driving an IC or the like on each substrate.

[0209] The timer 920 described above is mounted on the power supply board 910. The timer 920 has a DC-
The +5 V line from DC converter 913 is branched and input. This timer 920 is turned on when power is turned on.
When the V power supply voltage is input, a voltage of +5 V is passed for a predetermined time (in this example, at least a time until a voltage change signal is output from the power supply monitoring circuit). The signal of the + 5V voltage from the timer 920 is transmitted to the main board 31 or the prize ball control board 37.
And so on. The other configuration shown in FIG. 37 is the same as the configuration shown in FIG. 7 described above. Note that the timer 92
To 0, other power supply voltage or the like may be input, but it is preferable to set the voltage to be lower than the voltage value set as the detection condition of the electric component control means.

FIG. 38 is a block diagram showing an example of a configuration around the CPU 371 for controlling the prize ball for power supply monitoring and power supply backup in this embodiment using another signal. As shown in FIG. 38, a voltage change signal from a power supply monitoring circuit (power supply monitoring means) mounted on a power supply board,
The NMI interrupt compulsory signal from the timer 920 mounted on the power supply board is input to the non-maskable interrupt terminal (NMI terminal) of the award ball control CPU 371 via the AND circuit 965. Accordingly, the CPU 371 for controlling the award ball controls N
The occurrence of power interruption and power on can be confirmed by the MI processing.

In the award ball control board 37, the voltage change signal from the power supply monitoring circuit is input to one input terminal of the AND circuit 965 via the input buffer circuit 930. Here, 74HC is used as the input buffer circuit 930.
Although H.244 is exemplified, any circuit may be used as long as it has an input buffer function. The input buffer circuit 930 is an irreversible element that allows a signal to pass only in the direction from the power supply board to the inside of the prize ball control board 37.

In the configuration shown in FIG. 38, the prize ball control board 37
Is equipped with a system reset circuit 933. The system reset circuit 933 monitors the VSL power supply voltage, which is the same as the power supply voltage monitored by the power supply monitoring circuit of the power supply board 910, and generates a low-level system reset signal when the voltage value falls below a predetermined value. Further, the system reset circuit 933 monitors the VSL power supply voltage, and raises the system reset signal to a high level when the voltage value becomes equal to or higher than a predetermined value when the power is turned on. System reset circuit 93
The detection voltage of No. 3 is lower than the detection voltage of the power supply monitoring circuit mounted on the power supply board 910.

In this embodiment, the output of the system reset circuit 933 is input to the reset terminal of the CPU 371 for controlling a prize ball. Therefore, the CPU 371 for controlling the prize ball,
When a system reset signal is received from the system reset circuit 935, the system enters a reset state (non-operating state), and when the system reset signal rises to a high level, a reset releasing state (set state: operating state).

FIG. 39 is a timing chart showing states of a system reset signal and an NMI interrupt signal at the time of power-on and at the time of power failure in this embodiment. When power is applied to the gaming machine, a +5 V power supply voltage is input to the timer 920, the NMI interrupt compulsory signal from the timer 920 rises for a predetermined time, and the NMI interrupt signal rises to a high level. When the VSL power supply voltage rises and reaches a predetermined value (+9 V in this example), the system reset circuit 6
5, the system reset signal is raised to a high level. When the VSL power supply voltage further increases and reaches a predetermined value (+22 V in this example), a high-level voltage change signal is output from the power supply monitoring circuit.

When a power failure occurs, as shown in FIG. 39, the voltage monitoring circuit detects a decrease in the voltage value of the VSL power supply voltage to a predetermined value (+22 V in this example), and issues a low-level voltage change signal. Since the NMI interrupt compulsory signal has a low level, a low-level NMI interrupt signal is issued. And processing at the time of power supply stop (power cut-off processing)
Is performed.

As described above, in the present embodiment, the NMI is generated by using a signal different from the voltage change signal from the power supply monitoring circuit.
Since the interrupt signal is activated at a timing before the system reset signal, the system reset signal can be activated after the NMI interrupt signal is activated, and the power-off process is executed when the power is turned on. This can be reliably prevented.

Note that, in this embodiment, the timer 920
Is provided on the power supply board, but may be provided on the electric component control means such as the main board 31.

In each of the above embodiments, the case where the RAM is used as the storage means has been described. However, if the storage means is an electrically rewritable storage means, the RAM may be used.
Other than these may be used.

[0219] Here, the prize ball control means has been illustrated as an electric part control means other than the game control means.
The display control unit, the sound control unit, and the lamp control unit may be configured to perform the above-described control.

The pachinko gaming machine 1 of each of the above embodiments
Is a first-class pachinko gaming machine in which a predetermined game value can be given to a player when a stop symbol of a special symbol variably displayed on the variable display portion 9 based on a start winning prize is a predetermined symbol combination. However, if there is a prize in a predetermined area of the electric accessory that is opened based on a winning start, a second-type pachinko gaming machine that can give a predetermined game value to a player, or is variably displayed based on a starting prize. The present invention can be applied to a third-type pachinko gaming machine in which a predetermined right is generated or continued when there is a prize for a predetermined electric accessory which is opened when a symbol combination of a predetermined symbol is released.

Further, not only in pachinko gaming machines, but also in slot machines and the like, when power is cut off due to a power failure or the like, data immediately before the power is cut off is stored in a backup RAM or the like, and control restoration processing based on the stored data is performed when power is restored. The present invention can be applied to such a case.

[0222]

As described above, according to the present invention, a game machine is controlled by an electric component control means for performing processing for controlling electric components provided in the game machine, and a predetermined potential power supply used in the game machine. Power supply monitoring means for monitoring the voltage of the power supply and outputting a detection signal when a predetermined condition is satisfied.The electric component control means executes a predetermined power supply stop processing based on the detection signal from the power supply monitoring means, When the power supply of the electric component control means is started, the power supply stop processing restriction means for preventing the power supply stop processing from being executed is provided. Therefore, the power supply stop processing (power cutoff processing) when the power is turned on. Is prevented from being executed by mistake.

The power supply interruption processing restriction means includes delay means for delaying the timing of releasing the system reset of the electric component control means, and the power supply interruption processing in response to the detection signal input of the power supply monitoring means by the delay means. Is configured to delay the timing at which execution of the power supply monitoring unit is enabled, the detection signal of the power supply monitoring unit is valid during a period in which the processing corresponding to the detection signal of the power supply monitoring unit is not performed after the power is turned on. Since it can be extended until a predetermined period before the power supply is started, it is possible to prevent the power supply stop process from being erroneously executed when the power supply is turned on.
In particular, when the electric component control means is configured to execute the process at the time of power supply stop according to the level of the detection signal of the power supply monitoring means, the detection signal from the power supply monitoring means determines the timing of the system reset release. By delaying until after the level indicating the non-execution of the process at the time of the supply stop is performed, the erroneous execution of the process at the time of the power supply stop is reliably prevented.

The power-supply-stop-time processing restricting means is longer than the period during which the detection signal from the power supply monitoring means indicates the execution of the power-supply-stop processing since the start of power supply. When the control means is configured to hold the system reset state, a period during which processing corresponding to the detection signal of the power monitoring means cannot be performed after the power is turned on, the detection signal of the power monitoring means is used as a power supply stop processing. Can be extended until the execution of the power supply is not indicated any more, so that it is possible to prevent the power supply stop processing from being erroneously executed when the power is turned on.

The electric component control means performs a predetermined startup process in response to the release of the system reset, and the predetermined condition is satisfied when the voltage of the predetermined potential power supply is less than a predetermined value.
If the predetermined value is set to a value smaller than the value of the voltage of the predetermined potential power supply at the end of the startup processing, the startup processing during the period before the interrupt is enabled is performed. Since the detection signal of the power supply monitoring means will be output during
It is possible to prevent the power supply stop processing from being erroneously executed when the power supply rises.

When the power supply monitoring means is configured to output a detection signal to the electric component control means at the stage before the electric component control means becomes inoperable when the power supply is stopped,
Based on the input detection signal, the electric component control unit can perform various processes before the power supply is stopped, so that an appropriate power supply stop process can be executed.

When the detection signal is configured to be input to the electric component control means as an NMI interrupt signal, NM
The power supply stop process can be preferentially performed by the I interrupt process.

At the start of power supply, the electric component control means
If it is possible to restart the control based on the held data held in the storage means capable of holding the contents immediately before the stop of the power supply, if the power supply is stopped due to a power failure or the like, Even in such a case, since the state before the power supply is stopped can be returned after the power is restored, the disadvantage of the player can be eliminated.

When the electric component control means is configured to execute the RAM access prohibition processing in the power supply stop processing, it is possible to protect the information stored in the RAM.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is a front view of the gaming board of the pachinko gaming machine as viewed from the front.

FIG. 3 is a rear view of the mechanical plate of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a block diagram showing a circuit configuration example of a game control board (main board).

FIG. 5 is a block diagram illustrating a circuit configuration example of a winning ball control board.

[Fig. 6] C for power supply monitoring and power supply backup
FIG. 3 is a block diagram illustrating a configuration example around a PU.

FIG. 7 is a block diagram illustrating a configuration example of a power supply board.

FIG. 8 is a timing chart showing an example of an output state of a system reset signal and an NMI interrupt signal.

FIG. 9 is a timing chart showing an example of how a system reset signal and an NMI interrupt signal are output.

FIG. 10 is a timing chart showing an example of how a system reset signal and an NMI interrupt signal are output.

FIG. 11 is a flowchart illustrating an example of a main process executed by a CPU on a main board.

FIG. 12 is a flowchart illustrating an example of an initialization process.

FIG. 13 is a flowchart illustrating an example of a 2 ms timer interrupt process.

FIG. 14 is a flowchart illustrating an example of a game control process.

FIG. 15 is a flowchart illustrating an example of a power failure occurrence NMI process.

FIG. 16 is an explanatory diagram for describing an example of a backup parity data creation method.

FIG. 17 is an explanatory diagram showing an example of transmission timing of each control command from the main board.

FIG. 18 is a flowchart illustrating an example of a game state restoration process.

FIG. 19 is an explanatory diagram illustrating an example of a control state when the power is restored after a power failure occurs.

FIG. 20 is a block diagram illustrating an example of a configuration around a CPU for controlling a prize ball for monitoring and backing up a power supply.

FIG. 21 is an explanatory diagram showing a configuration example of a winning ball control command.

FIG. 22 is an explanatory diagram showing an example of a bit configuration of a winning ball control command.

FIG. 23 is a timing chart showing an example of how the award ball control command data is output.

FIG. 24 is a flowchart illustrating an example of a main process executed by a winning ball control CPU.

FIG. 25 is a flowchart showing an example of a timer interrupt process of the winning ball control CPU.

FIG. 26 is an explanatory diagram showing a configuration example of a RAM in the winning ball control means.

FIG. 27 is a flowchart illustrating an example of a command receiving process of the winning ball control CPU.

FIG. 28 is a flowchart illustrating an example of a winning ball control process.

FIG. 29 is a flowchart showing a ball lending control process.

FIG. 30 is a flowchart showing an example of a power failure generation process executed by the winning ball control CPU.

FIG. 31 is a flowchart illustrating an example of initialization processing of a winning ball control CPU.

FIG. 32 is a block diagram showing another configuration example around a CPU for power supply monitoring and power supply backup.

FIG. 33 is a timing chart showing an example of a state of a reset signal when power is turned on.

FIG. 34 is a timing chart showing an example of a state of a power supply drop or an NMI signal when the power of the gaming machine is turned off.

FIG. 35 is a block diagram showing another configuration example around a CPU for controlling a prize ball for power supply monitoring and power supply backup.

FIG. 36 is a block diagram showing still another configuration example around a CPU for power supply monitoring and power supply backup.

FIG. 37 is a block diagram showing another configuration example of the power supply board.

FIG. 38 is a block diagram showing still another configuration example around a CPU for controlling a prize ball for power supply monitoring and power supply backup.

FIG. 39 is a timing chart showing an example of how the system reset signal and the NMI interrupt signal are output.

[Explanation of symbols]

 1 Pachinko gaming machine 31 Main board 37 Prize ball control board 53 Basic circuit 56 CPU 371 Prize ball control CPU 651, 934, 976 Reset IC 902, 904 Power supply monitoring IC 910 Power supply board

Claims (8)

[Claims] 1. A gaming machine in which a player can play a predetermined game, an electric component control means for performing processing for controlling an electric component provided in the gaming machine, and used in the gaming machine. Power supply monitoring means for monitoring a voltage of a predetermined potential power supply and outputting a detection signal when a predetermined condition is satisfied, wherein the electric component control means detects a predetermined power supply stop by the detection signal from the power supply monitoring means A gaming machine, comprising: a power supply stop processing restriction unit configured to execute processing, and to prevent the power supply stop processing from being performed when the electric component control unit starts power supply. 2. The power supply stop-time processing restriction means includes delay means for delaying the timing of canceling the system reset of the electric component control means, and the power supply according to the detection signal input of the power supply monitoring means by the delay means. 2. The gaming machine according to claim 1, wherein a timing at which a stop-time process can be executed is delayed. 3. The power supply stop-time processing restriction means is longer than a period in which a detection signal from the power supply monitoring means is in a state indicating execution of the power supply stop processing after the power supply is started, The system reset state of the electric component control means is maintained.
The gaming machine described. 4. The electric component control means performs a predetermined start-up process in response to the release of the system reset, and the predetermined condition is satisfied when a voltage of a predetermined potential power supply is less than a predetermined value. 2. The gaming machine according to claim 1, wherein the value is set to a value smaller than the value of the voltage of the predetermined potential power supply at the time of ending the startup process. 5. The game according to claim 1, wherein the power supply monitoring means outputs a detection signal to the electric component control means when the power supply is stopped, before the electric component control means becomes inoperable. Machine. 6. The gaming machine according to claim 1, wherein the detection signal is input to the electric component control means as an NMI interrupt signal. 7. The electric component control means can restart control at the start of power supply based on data held in a storage means capable of holding the contents immediately before the power supply is stopped. The gaming machine according to claim 1. 8. The electric component control means executes a RAM access prohibition process in a power supply stop process.
A gaming machine according to claim 6.