JP2012148004A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine that limits control processing during RAM clear notification and reduces processing loads on control.SOLUTION: When a RAM is zero-cleared (step S13), a main control board transmits a RAM clear command (step S15), and outputs a RAM clear execution signal to an external terminal board (step S16). When a RAM clear execution signal is output, a monitoring timer starts measuring time (steps S17, S18). Upon receiving the RAM clear command, a lamp and a speaker are controlled in a RAM clear notification mode during a first period. After the value of the monitoring timer reaches "0" and a second period having a length longer than the first period elapses from the RAM clear execution signal output (YES in step S18), CTC is initialized (step S25).

Description

  The present invention relates to a gaming machine such as a pachinko machine or a pachislot machine.

  A gaming machine such as a pachinko machine has a built-in main control board on which a microcomputer including a CPU, RAM, and ROM is mounted. 2. Description of the Related Art Conventionally, a gaming machine having a backup function that keeps the stored contents of a RAM when the power is turned off has been proposed. In a gaming machine equipped with such a backup function, the stored contents of the RAM can be initialized (RAM clear) by operating the RAM clear switch.

  In a lottery on the main control board (for example, a big hit lottery on a pachinko machine), a counter variable that is updated every predetermined time is used, and a win ( For example, it is determined whether or not it is a big hit. The above-mentioned winning value and update rules for the counter variable can be found by obtaining a gaming machine (in this case, a pachinko machine) and analyzing the control program. Therefore, if it is the first-round circulation operation immediately after the RAM is cleared, it is relatively easy to intentionally generate a winning state (big hit state) by using an unauthorized device. For this reason, there is a possibility that a number of winning states may be illegally generated by appropriately shutting off the power supply and repeatedly generating the RAM clear.

  In order to suppress such illegal acts, in a conventional gaming machine, when the RAM is cleared, this is notified using a liquid crystal unit, a lamp, or a speaker (for example, Patent Document 1). A predetermined notification period (for example, 30 seconds) is set as the RAM clear notification.

JP 2003-33532 A

  By the way, in the main control unit (main control board), during execution of the RAM clear notification, various control processes by the main control unit are executed as in the case of the RAM clear notification not being executed. Examples of the control process include various processes such as a jackpot determination process and a winning detection process. RAM clearing is often performed when the game store is not in operation, such as before the store is opened, and therefore the possibility that the gaming machine is playing a game by the player during the RAM clear notification is extremely low. Therefore, various control processes executed by the main control unit during the RAM clear notification are useless processes.

  More specific description will be given below. That is, even when the RAM clear notification is being executed, in the same manner as when the RAM clear notification is not executed, various control units (such as a main control unit and an effect control unit that controls voice, light emission, display symbols, etc.) If the process proceeds, verify whether or not it will cause a malfunction or cause a misidentification to a person who can participate in the operation of the gaming machine due to an event that causes the game operation to proceed during the RAM clear notification Is required. Normally, RAM clearing is often performed when the game store is not in operation, such as before the store is opened, so the possibility that the gaming machine is being played by the player during the RAM clear notification is extremely low. Therefore, since the possibility that the game operation proceeds during the RAM clear notification becomes extremely low, performing various control verification operations under such a situation causes an increase in the development man-hours. In addition, when processing related to the progress of the game operation is performed during the RAM clear notification, it is necessary to provide a process to be executed during the RAM clear notification, a limiting process, etc. in some or all of the various control units. Processing is also complicated.

  Accordingly, an object of the present invention is to provide a gaming machine capable of reducing the control processing load by limiting the control processing during RAM clear notification.

  The invention according to claim 1 is a gaming machine (1), comprising: a main control unit (30) for controlling the progress of game processing in the gaming machine; and a control command from the main control unit. An effect control unit (31) for performing the effect operation according to the above, an informing means (15, 25, 27, 28) controlled by the effect control unit, and the main control unit at the time of power-off to the main control unit Including a backup means (61) for continuously holding data in the RAM (72) included in the RAM, and a RAM clear execution means for initializing the stored contents of the RAM. And a RAM clear notification control means (31) for controlling the notification means so as to execute a predetermined RAM clear notification mode during a predetermined first period related to initialization, wherein the main control section 1st period During a predetermined second period including a stop progression of the game processing, the game processing stop / advance means for advancing the game process after a second period including the (30), a game machine.

The numbers in parentheses represent corresponding components in the embodiments described later, but are not intended to limit the scope of the claims to the embodiments. The same applies hereinafter.
According to this configuration, the RAM clear notification (notification regarding the execution of the RAM clear) is executed in association with the initialization of the storage contents of the RAM (that is, the RAM clear). In addition, during the second period including the first period, the progress of the game process by the main control unit is stopped. Accordingly, the progress of the game process is stopped at least during the RAM clear notification. Thereby, the processing load on control can be reduced. And since the possibility that a game is played by the player during the RAM clear notification is extremely low, even if the control process during the RAM clear notification is restricted, it is hardly considered that the player will adversely affect the game execution. . Thereby, the processing load on control during RAM clear notification can be reduced without adversely affecting the game execution by the player.

According to a second aspect of the present invention, the second period may be a period overlapping with the first period. According to this configuration, the gaming process of the gaming machine can be started immediately after the end of the RAM clear notification.
According to a third aspect of the present invention, the game process progress / stop means includes a system reset delay means for delaying the end of the system reset process that is started based on power-on in order to stop the progress of the game process. You may go out.

According to a fourth aspect of the present invention, the game process progress / stop means stops the periodic interrupt progress that stops the progress of the periodic interrupt process that should be started every predetermined time in order to stop the progress of the game process. Means may be included.
In addition, as described in claim 5, the main control unit transmits a RAM clear-related command to the effect control unit in association with the initialization of the stored contents of the RAM, and the RAM And a timer (77) for timing the time since the clear-related command is transmitted to the effect control unit, wherein the RAM clear notification controller is configured to receive the initial value of the RAM in response to the reception of the RAM clear signal. The game process stop / progress means is from the start of timing by the timing means until the second period has elapsed by the timing means. The progress of the game process may be stopped.

  In this case, the RAM clear-related command may be transmitted to the effect control unit after the RAM is cleared by the RAM clear executing unit, or the RAM clear-related command is transmitted to the effect control unit prior to the RAM clear by the RAM clear executing unit. Also good. In the former case, timekeeping by the timekeeping means is executed after execution of the RAM clear. In the former case, timekeeping by the timekeeping means is executed prior to execution of the RAM clear.

1 is a perspective view of a pachinko machine to which a gaming machine according to a first embodiment of the present invention is applied. It is a front view of the game board shown in FIG. It is a block diagram which shows the electrical structure of the pachinko machine shown in FIG. FIG. 4 is a block diagram showing an electrical configuration of a main control board shown in FIG. 3. It is a flowchart which shows the content of the system reset process in a main control board (the 1). It is a flowchart which shows the content of the system reset process in a main control board (the 2). It is a flowchart which shows the content of the system reset process in a main control board (the 3). It is a flowchart which shows the content of the periodic interruption process in a main control board. It is a flowchart which shows the content of the system reset process in the pachinko machine which concerns on 2nd Embodiment of this invention. It is a flowchart which shows the content of the system reset process in the pachinko machine which concerns on 3rd Embodiment of this invention. It is a flowchart which shows the content of the regular interruption process in the pachinko machine which concerns on 3rd Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a perspective view of a pachinko machine 1 to which the gaming machine according to the first embodiment of the present invention is applied. This pachinko machine 1 includes an outer frame 2 having a substantially square frame shape for mounting (installation) on an amusement island arranged in a game store, and an inner frame 3 attached to the outer frame 2 so as to be able to be opened one by one. It has. The inner frame 3 is rotatably held around the rotation axis of the hinge 4 by the left and right hinges 4 of the outer frame 2, for example, the left hinge 4.

  A game board 5 (see FIG. 2) is accommodated and held in the upper part of the inner frame 3. The lower part of the inner frame 3 accommodates and holds firing means (not shown). A front door 6 is provided on the front side of the inner frame 3 so as to be openable and closable. A lower opening / closing plate 7 is provided on the front side of the inner frame 3 below the front door 6 so as to be opened and closed. The front door 6 is formed with a substantially circular opening 8 at a position facing the game board 5. A transparent plate 9 such as a glass plate is fitted in the opening 8, and the game board 5 (see FIG. 2) on the back side of the transparent plate 9 through the transparent plate 9 with the front door 6 closed. ) Can be visually recognized. A pair of left and right speakers (notification means) 28 is disposed on the front door 6. In addition, a pair of left and right lamp units (informing means) 27 for raising the atmosphere of the game is disposed below the front door 6.

  On the lower opening / closing plate 7, an upper plate 10 for storing game balls used for a game and a lower plate 12 for receiving a game ball overflowing from the upper plate 10 through an overflow path (not shown) are arranged vertically. Is provided. On the right side of the lower plate 12, a handle 13 that is operated when a game ball is launched into the game board 5 is disposed. A player can launch a game ball from the launching device toward the game board 5 by gripping and rotating the handle 13, and adjusting the rotation angle of the handle 13 to play the game board 5. It is possible to adjust the momentum of the game ball that is launched toward the.

  FIG. 2 is a front view of the game board 5. On the board surface of the game board 5, a substantially arc-shaped guide rail 14 for guiding the game ball launched from the launching device to the upper side (upper left side) of the game board 5 is disposed. A large number of obstacle nails 16 (only some of the obstacle nails 16 are shown in FIG. 1) are disposed on the surface of the game board 5, and extend along the guide rails 14 from the upper left side of the game board 5. The game ball released obliquely upward to the right flows down between the numerous obstacle nails 16 along the surface of the game board 5.

A liquid crystal display unit (notification means) 15 is disposed at the center of the game board 5. The liquid crystal display unit 15 is for displaying production symbols, predetermined messages, and the like during the game of the pachinko machine 1.
In the lower part of the game board 5, a special figure starting port 18 is arranged. The special drawing start port 18 is provided so that a game ball flowing down along the surface of the game board 5 can enter.

  In the game board 5, an electric tulip accessory (ordinary electric accessory) 19 including a pair of blades is disposed in association with the special drawing start opening 18. The electric tulip accessory 19 is usually constricted so that the tip portions of the blades are close to each other. And in the state where the electric tulip combination 19 is expanded, the frequency of entering the game ball into the special figure starting port 18 is higher than when the electric tulip combination 19 is in an approaching state.

When a game ball enters the special figure starting port 18, a predetermined number (for example, three balls) of prize balls are paid out from a prize ball payout device 50 (see FIG. 3) described later. In addition, a big hit lottery for determining whether or not to execute the special profit state is executed as the game ball enters the special figure starting port 18.
As shown in FIG. 2, for example, a large winning opening 20 having a long rectangular shape on the left and right is disposed below the special drawing start opening 18. The big winning opening 20 is formed in a size that allows a plurality of (for example, 3 to 4) game balls to enter simultaneously in the left-right direction. In connection with the big prize opening 20, a big prize opening opening / closing plate (special electric accessory) 21 capable of opening and closing the big prize opening 20 is provided. The big prize opening / closing plate 21 closes the big prize opening 20 in a state along the board surface of the game board 5 and can prevent the game ball from entering the big prize opening 20. A game ball that flows down onto the big prize opening 20 by opening the big prize opening 20 by tilting to the near side about a rotation shaft (not shown) arranged along the lower edge of the mouth 20. Can be introduced into the grand prize opening 20. When a game ball enters the big prize opening 20, a predetermined number (for example, 10 balls) of prize balls are paid out from the prize ball payout device 50 (see FIG. 3).

On the right part of the game board 5 (on the right side of the liquid crystal display unit 15 on the board surface of the game board 5), a general gate 17 through which a game ball flowing down along the board surface of the game board 5 can pass is disposed. When the game ball passes through the general gate 17, a normal symbol lottery for determining whether or not the electric tulip accessory 19 is in the expanded state (whether or not to execute the normal profit state) is executed.
In the outer area of the guide rail 14 in the upper right part of the game board 5, special figure display means 22 and general figure display means 23 are arranged. The special figure display means 22 is for displaying the result of the big hit lottery executed for entering the game ball into the special figure starting port 18 by variably displaying the special symbol. The normal symbol display means 23 is for displaying the result of the normal symbol lottery executed for the passage of the game ball with respect to the universal symbol gate 17 by variably displaying the normal symbol. The special figure display means 22 and the common figure display means 23 are constituted by, for example, a 7-segment display.

  The result of the big hit lottery is displayed on the special figure display means 22 but is displayed not only on the special figure display means 22 but also on the liquid crystal display unit 15. During the special profit state, the big prize opening 20 is opened by swinging the big prize opening / closing plate 21. In the special profit state, the grand prize opening 20 is opened until a predetermined time (for example, 30 seconds) elapses or until a predetermined number of gaming balls (for example, 10 balls) enter the big prize opening 20 in advance. Such an operation is performed for a number of rounds (for example, 15 rounds) with an interval of a predetermined time (for example, 1.0 second), with the operation of the special prize opening opening / closing plate 21 as one round. The number of prize balls that a player can acquire in one first special profit state is, for example, about 1500 (10 (balls / ball) × 10 (balls / round) × 15 (round)).

In addition, a game lamp (notification means) 25 for raising the atmosphere of the game is arranged on the surface of the game board 5. In FIG. 2, the game lamps 25 (two arranged around the liquid crystal display unit 15) provided in association with the liquid crystal display unit 15 are taken as an example. However, the shape, number and arrangement position of the game lamps 25 are illustrated. Can be set as appropriate.
In addition, for example, a game lamp can be provided in association with the special figure starting port 18 or the big prize opening 20.

In addition, when a normal winning opening is provided on the surface of the game board 5, a game lamp can be provided in association with the normal winning opening.
Of the game balls that flow down along the board surface of the game board 5, game balls (out balls) that have not entered either the special drawing start opening 18 or the special winning opening 20 are formed in the lower part of the game board 5. It is collected in the machine from the out port 24.

  FIG. 3 is a block diagram showing an electrical configuration of the pachinko machine 1. The pachinko machine 1 receives an AC voltage of 24V AC and outputs various DC voltages, a system reset signal SYS, and the like, and a main control board (main control unit) 30 that controls game operation control (game control). , An effect control board 31 for controlling the effect control, a liquid crystal control board 63 for driving the liquid crystal display unit 15, a payout control board 32 for driving the prize ball payout device 50 and paying out game balls, and a player And a launch control board 64 for firing a game ball by driving a launch device (not shown) based on a rotation operation of the handle (not shown). Each control board 30, 31, 32, 63, 64 is mounted with a microcomputer having a configuration including, for example, a CPU, a RAM, and a ROM.

  The main control board 30 is connected to a power supply board (backup means) 61 and a payout control board 32 via a main board relay board 62, respectively. The main control board 30 is connected to the effect control board 31 and the liquid crystal control board 63 via the command relay board 66 and the effect interface board 67, respectively. In addition, the effect control board 31 and the liquid crystal control board 63 are connected via an effect interface board 67. In addition, the power supply board 61 is connected to the effect interface board 67 via the power supply relay board 65.

  The main control board 30 is connected to various game components of the game board 5 via the game board relay board 34. The game board relay board 34 receives a switch signal of a winning detection switch (for example, a big winning opening winning detection switch) for detecting the entrance of a game ball to various winning openings (for example, the big winning opening 20) on the gaming board 5. On the other hand, the driving mechanism (including solenoids, for example) of the electric tulip accessory 19 and the special prize opening / closing plate 21 is driven. Note that the switch signal of the detection switch built in the special figure starting port 18 is directly input to the main control board 30 without going through the game board relay board 34.

  The speaker 28 and the game lamp 25 are connected to the effect interface board 67 via the first frame relay board 69 and the second frame relay board 70, respectively. Further, a lamp board 68 for driving the lamp unit 27 is connected to the effect interface board 67. A system reset signal SYS and a power supply voltage from the power supply board 61 are input to the liquid crystal control board 63 and the lamp board 68 via the effect interface board 67, respectively.

The payout control board 32 is connected to an external terminal board 33 for outputting a signal to the outside of the pachinko machine 1. The external terminal board 33 is communicably connected to, for example, a hall control of an amusement store.
Among the substrates shown in FIG. 3, the payout control substrate 32, the launch control substrate 64, the power supply substrate 61, the second frame relay substrate 70, and the external terminal substrate 33 are frame side members (in FIG. 3) provided on the so-called inner frame 3. (Indicated by a dashed line).

On the other hand, the main control board 30, the production control board 31, the liquid crystal control board 63, the production interface board 67, the lamp board 68, the main board relay board 62, the command relay board 66, the power relay board 65, the first frame relay board 69, and the game The board relay board 34 is a board side member attached to the back surface of the game board 5.
The main control board 30 outputs a control command CMD toward the effect control board 31. A control command CMD from the main control board 30 is given to the effect control board 31 via the command relay board 66 and the effect interface board 67.

  The effect control board 31 turns on / off the game lamp 25 and turns off the speaker 28 via the first frame relay board 69 and the second frame relay board 70 based on the control command CMD from the main control board 30. Control audio output respectively. Further, the effect control board 31 determines the specific effect contents of the liquid crystal display unit 15 based on the control command CMD from the main control board 30, and sends the control command CMD ′ on which the effect contents are described to the liquid crystal control board 63. Send to. The control command CMD ′ output from the effect control board 31 is given to the liquid crystal control board 63 via the effect interface board 67. The liquid crystal control board 63 controls the display of the liquid crystal display unit 15 based on the control command CMD ′ (in this case, a liquid crystal control command) sent from the effect control board 31.

  The payout control board 32 is connected to the main board relay board 62 and is connected to the main control board 30 via the main board relay board 62. A power supply board 61 is directly connected to the payout control board 32, and the power supply board 61 provides the payout control board 32 with a system reset signal SYS, a voltage drop signal DWN, a power supply voltage, and a backup power supply voltage BU. . The main control board 30 outputs a control command CMD ″ toward the payout control board 32. The control command CMD ″ output from the main control board 30 is given to the payout control board 32 via the main board relay board 62. The payout control board 32 controls the payout operation of the prize ball payout device 50 based on the control command CMD ″ from the main control board 30.

  The power supply board 61 supplies a system reset signal SYS, a RAM clear signal DEL, a voltage drop signal DWN, DC12V and DC32V voltages, and a backup power supply voltage BU to the main control board 30 via the main board relay board 62. . The power supply board 61 also applies a system reset signal SYS and AC and DC power supply voltages to the effect interface board 67 via the power supply relay board 65. The effect interface board 67 gives the power supply voltage from the power supply board 61 and the system reset signal SYS to the effect control board 31.

The system reset signal SYS is a signal indicating that the AC power supply 24V has been turned on (supplied) to the power supply board 61.
The RAM clear signal DEL is a signal for determining whether to initialize the contents stored in the RAM of the microcomputer of the main control board 30 and the payout control board 32, respectively.
The microcomputers of the main control board 30 and the payout control board 32 are respectively supplied with a backup power supply BU of DC 5V from the power supply board 61. Therefore, the RAM data in each microcomputer is retained even after the AC power supply 24V is shut off due to the end of business or a power failure. In the present embodiment, the storage contents of the RAM are designed to be retained for at least several days.

The backup power supply voltage BU is stored in the RAM 72 (see FIG. 4) of the main control board 30 and the RAM of the payout control board 32 even after the supply of voltage from the AC power supply 24V to the power supply board 61 is shut off due to business termination or power failure. It is a DC voltage of DC5V for holding data.
The power supply board 61 is configured to output a voltage drop signal DWN to the main control board 30 and the payout control board 32 when the AC power supply 24V is shut off. The voltage drop signal DWN is a signal indicating that the AC power supply 24V has started to drop, and is supplied to the input port of each microcomputer. Based on the input of the voltage drop signal DWN, the main control board 30 and the payout control board 32 respectively save necessary data in the RAM by backup processing.

  In response to receiving the voltage drop signal DWN, the main control board 30 and the payout control board 32 start necessary termination processing prior to a power failure or business termination. As a result, coupled with the effect of power supply by the backup power supply BU described above, the main control board 30 and the payout control board 32 are in the gaming state (or operation) immediately before the power is shut off at the start of business or after recovery from a power failure. You can return to However, the backup power supply BU is not supplied to other control boards such as the effect control board 31 and the liquid crystal control board 63. Therefore, in these control boards, the operation in the initial state is started at the start of business or at the time of recovery from a power failure, regardless of the operation and the state before the power is shut off. These control boards may also be provided with such a backup function.

  The power supply board 61 is provided with a RAM clear switch (not shown) for zero-clearing the RAM data (initializing the stored contents of the RAM). When an operator (for example, an employee of an amusement shop) pushes the RAM clear switch by hand to turn it on, the RAM clear signal DEL becomes L level. When the hand is released from the RAM clear switch, the RAM clear signal DEL returns to the H level. The RAM clear switch may be provided on the main control board 30. In this case, the RAM clear signal DEL may be transmitted to the payout control board 32.

  When the RAM clear signal DEL is at the L level (that is, while the RAM clear switch is being operated), when the power on switch (not shown) provided on the power supply board 61 is turned on and the power is turned on, the main control is performed. The data stored in the RAM 72 (see FIG. 4) of the substrate 30 and the data stored in the RAM of the payout control substrate 32 are cleared to zero. On the other hand, when the RAM clear signal DEL is at the H level (that is, the RAM clear switch is not operated) and the power on switch is turned on to turn on the power, the data is stored in the RAM 72 (see FIG. 4) of the main control board 30. Both the stored data and the data stored in the RAM of the payout control board 32 are not cleared to zero.

  FIG. 4 is a block diagram showing an electrical configuration of the main control board 30. Specifically, the microcomputer is mounted on the main control board 30 as described above. The microcomputer includes a CPU 71, a RAM 72, a ROM 73, a watchdog timer (WDT) circuit 74, a CTC 75, a RAM clear flag 76, and a monitoring timer (time measuring means) 77.

For example, a Z80 CPU (manufactured by Zilog) is adopted as the CPU 71 of the main control board 30.
The watchdog timer circuit 74 forcibly resets the CPU 71 and resumes game control when the CPU 71 runs away.
A random number storage area (not shown) is provided in the work area of the RAM 72. In this random number storage area, various random numbers (for example, a jackpot determination random number, a jackpot symbol determination random number, an outlier symbol determination random number related to the execution of a jackpot lottery executed for a game ball entering the special figure start port 18 are stored. Random numbers and / or random numbers for determining variation patterns) are stored.

  As described above, the RAM 72 is supplied with the backup power supply voltage BU (DC power supply voltage of DC5V) from the power supply board 61. Thus, after the power supply of the power supply board 61 to the main control board 30 is shut off, the RAM 72 holds the backup data. Specifically, when the AC power supply 24V applied to the power supply board 61 starts to drop, a DWN signal is transmitted from the power supply board 61 to the main control board 30. When the voltage drop signal DWN is received, the CPU 71 executes a backup process. After the power is shut off, the backup power supply voltage BU is supplied from the power supply board 61 to the RAM 72, and the data stored in the RAM 72 is retained. Further, the CPU 71 obtains a checksum (a result of a checksum operation that is an addition operation for the work area of the RAM 72, a data error detection code) based on the data stored in the RAM 72, and calculates the obtained checksum as The data is stored in a SUM storage area (not shown) of the RAM 72.

The RAM clear flag 76 indicates whether or not the pachinko machine 1 is in a state where the RAM is cleared. “5A [H]” is stored during execution of the RAM clear, and “00” after the RAM clear is performed. [H] "is stored ([H] means a hexadecimal number).
Further, the CPU 71 outputs a signal to the effect that RAM clear is executed (hereinafter referred to as “RAM clear execution signal”) toward the external terminal board 33. The RAM clear execution signal output from the main control board 30 is output to the hall control of the game store via the external terminal board 33.

The monitoring timer 77 is, for example, a subtraction type timer, and is provided so as to be set to an arbitrary value. The monitoring timer 77 subtracts (counts down) until the set value reaches “0”, and stops when the value reaches “0”.
Next, the program of the main control board 30 will be described. The control program for the main control board 30 is activated every predetermined time (4 msec), and system reset processing (described below, see FIGS. 5 to 7), which is the main processing that is activated based on the restoration and input of the power supply voltage. Maskable periodic interrupt processing (to be described later, see FIG. 8).

5 to 7 are flowcharts showing the contents of the system reset process in the main control board 30.
The execution of the system reset process is started based on the input of the above-described system reset signal SYS to the main control board 30. When the execution of this system reset process is started, the RAM is cleared when the power is turned on without the RAM being cleared, such as when recovering from a power failure, or when the amusement store is opened. In some cases, the power supply is energized. In addition, as a case where the execution of the system reset process is started, there is a case where the CPU 71 is forcibly reset by the watchdog timer circuit 74 due to the runaway of the CPU 71.

  In any of these cases, the CPU 71 first sets itself to the interrupt disabled state (step S1) and sets the interrupt mode 2 (step S2). Thereafter, the value of the stack pointer inside the CPU 71 is set to the final address (for example, 8000H) of the stack area (step S3), and the values of the respective registers built in the CPU 71 are initialized (step S4). Thereafter, when the main control board 30 has received the RAM clear signal DEL from the power supply board 61, the RAM clear signal DEL is read and the level of the RAM clear signal DEL is checked (step S5).

  Next, the CPU 71 waits while clearing the watchdog timer circuit 74 until the initial setting of peripheral boards (for example, boards such as the payout control board 32 and the effect control board 31) is completed (steps S6 and S7). Even after completion of the initial setting in the peripheral substrates, the voltage drop signal DWN is kept waiting while it is at a voltage level (eg, an off state) indicating a power-off state (step S8). This is because the watchdog timer circuit 74 is timed out after the backup processing is completed at the time of power-off and before the CPU 71 shuts down, and the system reset processing is forcibly started. This wait process (S8) is provided because there is a possibility that data in the RAM area may be changed unless the progress of the process is stopped at the timing before the write permission to the RAM 72 is permitted, and normal restoration cannot be performed. ing. Normally, as the power is turned on, the voltage drop signal DWN is input to the main control board 30 at a voltage level (for example, an ON state) indicating a power-on state.

  If the voltage drop signal DWN is at a voltage level indicating a power-on state, the CPU 71 enables the RAM 72 (S9: RAM write permission) and sends a standby screen display command to the effect control board 31 (step S10). ). Thereafter, the CPU 71 monitors whether or not a power-on command is received from the payout control board 32 (step S11). This power-on command is a command indicating that the payout control board 32 has started up, and is a command sent from the payout control board 32 to the main control board 30 when the payout control board 32 is energized and starts up normally. It is.

  When the power-on command is received (YES in step S11), the CPU 71 then determines whether or not an L-level RAM clear signal has been received from the power supply board 61 based on the information read in step S5, that is, the power supply board 61. It is determined whether or not the RAM clear signal received from L is at L level (step S12). When the RAM clear operation is performed when the power is turned on, specifically, when the power is turned on while the RAM clear switch is being pressed (YES in step S12), the main control board 30 moves from the power board 61 to the L level. The RAM clear signal is received. On the other hand, when the power is turned on but the ram clear operation is not performed, specifically, when the power is turned on without pressing the RAM clear switch (NO in step S12), the main control board 30 The RAM clear signal at H level is received from 61.

  When the RAM clear signal received by the main control board 30 is L level (YES in step S12), the entire area of the RAM 72 (including the work area, the RAM clear flag area (RAM clear flag 76), and the SUM storage area is included. All areas) are cleared to zero (the contents stored in the RAM 72 are initialized) (S13: RAM initialization). As the RAM is cleared, “5A [H]” is stored in the RAM clear flag 76 (step S14).

Then, main control board 30 transmits a RAM clear command (RAM clear-related command) for notifying RAM clear to peripheral boards (for example, boards such as payout control board 32 and effect control board 31) (step S15). ).
The RAM clear command output from the main control board 30 is transmitted to the effect control board 31 via the command relay board 66. When the effect control board 31 receives the RAM clear command, the effect control board 31 transmits a control command for RAM clear notification to the liquid crystal control board 63 and the lamp board 68 via the effect interface board 67. The liquid crystal control board 63 that has received this control command gives a message such as a predetermined RAM clear screen (for example, “RAM is being cleared”) to the liquid crystal display unit 15 for a predetermined first period (for example, 30 seconds). Notification mode) is displayed. In addition, the lamp board 68 that has received this control command turns on the lamp unit 27 in a predetermined RAM clear notification mode during the first period. Further, when receiving the RAM clear command, the production control board 31 controls the sound output of the speaker 28 to output a predetermined alarm sound (RAM clear notification mode) from the speaker 28 for the first period, and also the game lamp 25. Is turned on in a predetermined RAM clear notification mode during the first period. In this RAM clear notification mode, all the lamps 25 and 27 of the pachinko machine 1 are lit and an alarm sound is output from the speaker 28 at a high volume. Therefore, it can be said that it is a very flashy production. The effect control board manages the time after receiving the control command for RAM clear notification, that is, the first period, which is the notification period, by a unique timer.

Further, the CPU 71 outputs a RAM clear execution signal toward the external terminal board 33 (step S16). The RAM clear execution signal output from the main control board 30 is input to the hall control of the game store via the external terminal board 33.
Further, the timing by the monitoring timer 77 is started at the timing of the RAM clear execution signal output from the main control board 30 (steps S17 and S18). At the start of timing, a value corresponding to a predetermined second period (for example, 30 seconds) is set in the monitoring timer 77 (step S17). Then, the monitoring timer 77 is subtracted until the value of the monitoring timer 77 becomes “0” (steps S18 and S19). Therefore, if the value of the monitoring timer 77 is larger than “0” (NO in step S18), it means that the second period (for example, 30 seconds) has not elapsed since the output of the RAM clear execution signal.

  When the value of the monitoring timer 77 reaches “0” (YES in step S18), the input / output port (not shown) of the main control board 30 is cleared (step S20) and the RAM clear flag 76 is cleared (“ 5A [H] ”→“ 00 [H] ”) (step S21), the CTC 75 that outputs an interrupt signal for starting the periodic interrupt processing (see FIG. 8) described below is initialized (step S25). ).

  The RAM initialization in S13, the RAM clear flag storage (setting) in step S14, the RAM clear command transmission in step S15, and the RAM clear execution signal output in step S16 are executed in this order. The time interval for executing each step is a sufficiently short time compared to the second period. Therefore, it can also be understood that each step of step S13 to step S16 is executed at substantially the same timing.

Further, steps after steps S14 to S16 are not limited to the order shown in FIG. 6. For example, step S15 may be executed prior to step S14, or step S16 may be executed prior to step S14 or step S15. It may be.
The CTC 75 is initialized after the monitoring timer 77 is decremented until its value becomes “0”. In other words, the end of the system reset process is delayed and the periodic interrupt process is not executed until the second period elapses after the output of the RAM clear execution signal. Further, since the periodic interrupt process includes the switch input process (S33), the switch signal is not executed even if the switch signal is input to the main control board 30 until the second period elapses. It is invalidated.

Then, with the CPU 71 set to the interrupt disabled state (step S26), update processing is executed for various counters (step S27). After the update processing is completed, the CPU 71 is returned to the interrupt enabled state (step S28). Return to S26.
The counter updated in step S27 includes a missed symbol determination counter. This missed symbol determination counter is a big win lottery (a lottery for determining whether or not to execute the special profit state). ) Is a counter for determining what aspect of the off-game is to be produced when the result of () is in the off-state. The counters updated in step S27 include various counters such as a variation pattern determination counter, a symbol determination counter, and an initial value update counter.

On the other hand, if the RAM clear signal received by the main control board 30 is at the H level (NO in step S12), it is determined whether or not the data (backup data) stored in the RAM 72 is valid (step S12). S22).
Specifically, whether the backup data is valid is determined as follows. The CPU 71 collates the checksum (data error detection code) calculated based on the data stored in the RAM 72 at that time with the backup checksum stored in the SUM storage area. The calculated checksum value should essentially match the backup checksum value. However, if the checksum operation cannot be executed when the voltage drops, or if the checksum operation can be executed but data is damaged in the work area, the values of these two checksums do not match. . In this case, assuming that the backup data is invalid (NO in step S22), the process proceeds to the RAM clear process in step S13, and the state of the pachinko machine 1 is returned to the initial state.

  On the other hand, if the calculated checksum value matches the checksum value stored in the SUM storage area (YES in step S12), then a return command process (step S23) and various processes at the time of return (step S24) is executed. In the return command processing in step S23, a return command notifying that power supply is to be returned is transmitted to peripheral boards (for example, boards such as the payout control board 32 and the effect control board 31). In the various processes at the time of return in step S24, state commands for specifying the gaming state (probability state and whether or not the electric tulip accessory 19 (ordinary electric accessory) is activated) at the time of power-off are displayed on the peripheral board (for example, production) When the process for transmitting to the control board 31) and the operation state of the symbol at the time of return are in the demo state, the process for transmitting the demo command and the command according to the error state at the time of return are transmitted. Various processes such as the above process are executed.

When the various processes at the time of return in step S24 are completed, the CTC 75 is initialized (step S25), and then the CPU 71 is set to the interrupt disabled state (step S26), and update processing is performed for various counters (step S27). . After updating the counter, the CPU 71 is returned to the interrupt enabled state (step S28) and the process returns to step S26.
Next, consider a case where the power is turned off while the game processing of the CPU 71 is stopped (NO in step S18), and then the power is restored. Prior to stopping the stop of the game process (steps S18 and S19), the RAM clear is executed (step S13: RAM initialization), and the contents of the SUM storage area are also cleared by this RAM clear. The value of this checksum is “00 [H]” at the time of starting execution of “. Further, since the RAM clear flag is set (step S14) prior to the stop of the progress of the game process (steps S18 and S19), the value of the RAM clear flag is “5A” when the execution of the stop of the progress of the game process is started. It is.

  When a power-off operation is performed while the progress of the game process is stopped, the power supply to the main control board 30 is stopped and the entire operation of the ball game machine 1 is stopped. In this case, as a matter of course, the RAM clear notification using the lamps 25 and 27 and the speaker 28 is also terminated. When the power is cut off, the voltage drop signal DWN is input to the input port. However, since the process for reading the input port is not performed for control, the input of the voltage drop signal DWN to the input port is substantially invalidated. Has been. Therefore, the backup process is not normally executed when the power is turned off. Therefore, the backup checksum value stored in the SUM storage area of the RAM 72 remains “00 [H]”.

  Next, when the power is turned on and the power is restored, the process is executed from the beginning of the system reset process described above. That is, each process shown in FIGS. 5 to 7 is executed in order from the process of step S1 described above. After each process shown in steps S1 to S10 is executed, the CPU 71 monitors whether or not a power-on command from the payout control board 32 is received (step S11). When the power-on command is received (YES in step S11), the CPU 71 then refers to the level of the RAM clear signal to check whether or not the RAM clear switch has been pressed when the power is turned on (step S12). If the RAM clear operation has been performed when the power is turned on (YES in step S12), then, the entire area of the RAM 72 is cleared to zero (S13: RAM initialization).

  On the other hand, when the power is turned on without pressing the RAM clear switch, whether or not the data (backup data) stored in the RAM 72 is valid, that is, based on the data stored in the RAM 72 at that time. It is determined whether or not the calculated checksum matches the backup checksum stored in the SUM storage area (step S22).

  In this case, the newly created checksum data is a value created based on the data (clear data) after the previous RAM clear and the RAM clear flag value “5A [H]”. A mismatch occurs in the comparison with the checksum data of the SUM storage area to be compared (00 [H] ≠ 00 [H] + 5A [H]). Then, assuming that the backup data is invalid (NO in step S22), the process proceeds to the RAM clear process in step S13, and the entire area of the RAM 72 is cleared to zero. As the RAM is cleared, “5A [H]” is stored in the RAM clear flag 76 (step S14). Furthermore, a RAM clear command for RAM clear notification is transmitted to peripheral boards (for example, boards such as the payout control board 32 and the effect control board 31) (step S15). Then, each process of step S16-step S28 shown in FIGS. 5-7 is performed. Since the RAM clear command is transmitted, the RAM clear notification using the liquid crystal display unit 15, the game lamp 25, the lamp unit 27 and the speaker 28 is executed. Specifically, the above-described RAM clear screen is displayed on the liquid crystal display unit 15, and the lamp unit 27 is lit in the above-described RAM clear notification mode. In addition, the above-described alarm sound is output from the speaker 28, and the game lamp 25 is turned on in the above-described RAM clear notification mode. Therefore, even when the RAM clear switch is not depressed when the power is restored, the RAM clear is always executed when the power is restored, and the RAM clear notification is executed according to the execution of the RAM clear. As a result, the expected notification period of RAM clear notification, which is the first period, can be secured.

Next, a description will be given of a periodic interrupt processing program that is interrupted from the main processing and started to be executed every 4 msec. FIG. 8 is a flowchart showing the contents of the periodic interrupt process in the main control board 30.
When the periodic interrupt process is started, the power supply abnormality check process is promptly executed without saving the register of the CPU 71 (step S30). The necessity of executing the power supply abnormality check process is based on the fact that the start timing of the periodic interrupt process is fixed after the interruption is permitted in step S28. In the power supply abnormality check process in step S30, as described above, the level of the voltage drop signal supplied from the power supply board 61 to the main control board 30 is determined.

After the power supply abnormality check process in step S30 is finished, the big win winning random number counter (not shown) used in the normal symbol determination process (step S36) described below and the jackpot used in the big hit determination process (step S37). The value of the winning random number counter (not shown) is updated (S31: random number update process).
After completion of the random number update process in step S31, a timer subtraction process is performed for each timer managing the game operation time (step S32). The timer subtracted here is mainly used for managing the expansion time of the electric tulip accessory 19, the opening time of the special winning opening 20, and other game performance times.

  Next, various switches including a special drawing start opening winning detection switch for detecting a game ball entering the special drawing starting opening 18 and a large winning opening winning detection switch for detecting a game ball entering the special winning opening 20. ON / OFF signal is input, and the level of the ON / OFF signal and its rising state are stored in the work area (S33: switch input processing). The random number update process (S31) described above may be executed after the switch input process (S33).

After the switch input process is completed, an error management process is performed (step S34). In the error management process, whether or not supply of game balls to the ball supply mechanism (not shown) for supplying game balls to the prize ball payout device 50 is stopped, whether or not the game balls are clogged, and abnormal occurrences in the pachinko machine 1 are generated. The presence or absence is also judged.
Next, confirmation of the winning information is performed in order to instruct the number of payouts to the winning ball payout device 50 corresponding to the number of paying out of the game balls won in the winning opening (special drawing start opening 18, large winning opening 20, normal winning opening). And, after executing a prize ball management process for creating command data (step S35), a normal symbol determination process for determining whether or not to operate the electric tulip accessory 19 (whether or not to execute a normal profit state) ( A process equivalent to the above-described normal symbol lottery) is executed (step S36). More specifically, the value of the random number counter for normal winning updated by the random number updating process in step S31 is compared with the winning value. If the value of the random number counter for the regular symbol win matches the winning value, the operation mode is changed to the normal symbol winning mode. In this operation mode, a process for expanding the electric tulip accessory 19 is executed.

Next, a jackpot determination process for determining whether or not to execute the special profit state (operation of the big prize opening 20) is performed (step S37). If the result of the jackpot determination is a jackpot, the operation mode is changed to the special profit state. Further, in the operation mode in the special profit state, processing for the opening operation of the special winning opening 20 (opening / closing operation of the special winning opening / closing plate 21) is executed.
After the jackpot determination process, a lamp lighting process is executed for a predetermined lamp managed by the main control board 30 (step S38), and the expansion operation of the electric tulip accessory 19 and the opening / closing operation of the big prize opening opening / closing plate 21 are performed. After executing the opening / closing accessory driving process to be realized (step S39), the CPU 71 is returned to the interrupt permission state, and the timer interruption is finished (step S40). As a result, the routine returns to the infinite loop process (see FIG. 7) of the main process from the routine interrupt process routine, and the process of step S26 is executed.

  As described above, according to this embodiment, the system reset process does not end until the second period (for example, 30 seconds) elapses from the start of the RAM clear notification, and therefore the periodic interrupt process is not executed. Therefore, the progress of the game process by the main control board 30 is stopped until the second period elapses after the RAM is cleared. Thereby, the control processing of the main control board 30 and the effect control board 31 during the RAM clear notification can be restricted, and the processing burden on control can be reduced.

Further, this is notified for a first period (for example, 30 seconds) after the RAM is cleared. In this embodiment, since the second period is the same length as the first period (a period overlapping each other), the progress of the game process is stopped at least during the RAM clear notification.
Since the possibility of a player playing a game during the RAM clear notification is very low, even if the control processing of the main control board 30 and the effect control board 31 during the RAM clear notification is restricted, the player can execute the game. It is almost impossible to have an adverse effect. Thereby, the processing load on control during RAM clear notification can be reduced without adversely affecting the game execution by the player.

By the way, the RAM clear notification is a very flashy effect as described above. For this reason, it may be uncomfortable for an operator (for example, a store clerk in the game shop) who is working on the pachinko machine 1 to interrupt the RAM clear notification. The RAM clear notification is interrupted by turning off the power after starting the RAM clear notification and then returning the power.
However, the progress of the game process is stopped during the RAM clear notification. As described above, when the power is cut off while the game process is stopped, even if the power is restored without pressing the RAM clear switch, the RAM is always cleared after the power is restored. A RAM clear notification is executed in response to the execution of the clear. Therefore, the expected notification period of the RAM clear notification, which is the first period, can be reliably ensured.

  FIG. 9 is a flowchart showing the contents of the system reset process in the pachinko machine according to the second embodiment of the present invention. In the system reset process in the second embodiment, the processes shown in FIG. 9 are executed in place of the processes in steps S12 to S24 (that is, the processes shown in FIG. 6) in the flowcharts shown in FIGS. The The operation content of the CPU 71 will be described with reference to FIGS.

  The system reset process according to the second embodiment is different from the system reset process according to the first embodiment in that the monitoring timer 77 monitors the progress of the second period prior to the initialization of the RAM 72. Is a point. In relation to this, transmission of a RAM clear command to peripheral boards and output of a RAM clear execution signal to the external terminal board 33 are also executed prior to the initialization of the RAM. This will be specifically described below.

  When the system reset process is started, the CPU 71 first sets itself to the interrupt disabled state and sets the interrupt mode 2 (steps S1 and S2 shown in FIG. 5). Thereafter, the value of the stack pointer in the CPU 71 is set to the final address (for example, 8000H) of the stack area, and the values of the respective registers are initialized (steps S3 and S4 shown in FIG. 5). Thereafter, the level of the RAM clear signal DEL is checked (step S5 shown in FIG. 5). Next, the CPU 71 waits while clearing the watchdog timer circuit 74 until the initial setting of the peripheral board is completed (steps S6 and S7 shown in FIG. 5). While the drop signal DWN is at a voltage level (for example, an off state) indicating a power-off state, it waits (step S8 shown in FIG. 5).

  If the voltage drop signal DWN is at a voltage level indicating a power-on state, the CPU 71 enables the RAM 72 (S9: RAM write permission) and sends a standby screen display command to the effect control board 31 (see FIG. 5). Step S10). Thereafter, the CPU 71 monitors reception of a power-on command from the payout control board 32 (step S11 shown in FIG. 5). When the power-on command is received (YES in step S11), the CPU 71 then proceeds to step S42 in FIG.

  The CPU 71 that has received the power-on command then determines whether or not the L level RAM clear signal has been received from the power supply board 61 based on the information read in step S5 shown in FIG. It is determined whether or not the clear signal is at L level (step S42). When the RAM clear operation is performed when the power is turned on, specifically, when the power is turned on while the RAM clear switch is pressed (YES in step S42), the main control board 30 moves from the power board 61 to the L level. The RAM clear signal is received. On the other hand, when the power is turned on but the ram clear operation has not been performed, specifically, when the power is turned on without pressing the RAM clear switch (NO in step S42), the main control board 30 The RAM clear signal at H level is received from 61.

  If the RAM clear signal received by the main control board 30 is at L level (YES in step S42), “5A [H]” is stored in the RAM clear flag 76 (step S43). Then, the main control board 30 transmits a RAM clear command (RAM clear related command) for RAM clear notification to peripheral boards (for example, boards such as the payout control board 32 and the effect control board 31) (step S44). ). When the effect control board 31 receives the RAM clear command, the effect control board 31 transmits a control command for RAM clear notification to the liquid crystal control board 63 and the lamp board 68. The liquid crystal control board 63 that has received this control command displays a predetermined RAM clear screen (for example, a message such as “RAM clearing”, RAM clear notification mode) on the liquid crystal display unit 15 during the first period.

  In addition, the lamp board 68 that has received this control command turns on the lamp unit 27 in a predetermined RAM clear notification mode during the first period. Further, when receiving the RAM clear command, the production control board 31 controls the sound output of the speaker 28 to output a predetermined alarm sound (RAM clear notification mode) from the speaker 28 for the first period, and also the game lamp 25. Is turned on in a predetermined RAM clear notification mode during the first period. In this RAM clear notification mode, all the lamps 25 and 27 of the pachinko machine 1 are lit and an alarm sound is output from the speaker 28 at a high volume.

Further, the CPU 71 outputs a RAM clear execution signal toward the external terminal board 33 (step S45). The RAM clear execution signal output from the main control board 30 is input to the hall control of the game store via the external terminal board 33.
The RAM clear flag storage (setting) in step S43, the RAM clear command transmission in step S44, and the output of the RAM clear execution signal in step S45 are executed in this order. These steps are executed. The time interval is sufficiently shorter than the second period. Therefore, it can also be understood that the steps S43 to S45 are executed at substantially the same timing.

Further, steps after step S43 to step S45 are not limited to the order shown in FIG. 9. For example, step S44 may be executed prior to step S43, or step S45 may be executed prior to step S43 or step S44. May be.
Further, the timing by the monitoring timer 77 is started at the timing of the RAM clear execution signal output from the main control board 30 (steps S47 and S48). At the start of timing, a value corresponding to a predetermined period (for example, 30 seconds) is preset in the monitoring timer 77 (step S46). Then, the monitoring timer 77 is subtracted until the value of the monitoring timer 77 becomes “0” (steps S47 and S48). Therefore, if the value of the monitoring timer 77 is greater than “0” (NO in step S47), it means that the second period has not elapsed since the output of the RAM clear execution signal.

The CTC 75 is initialized after the monitoring timer 77 is decremented until its value becomes “0”. In other words, the end of the system reset process is delayed and the periodic interrupt process is not executed until the second period elapses after the output of the RAM clear execution signal.
When the value of the monitoring timer 77 reaches “0” (YES in step S48), the entire area of the RAM 72 is cleared to zero (stored contents are initialized) (S46: RAM initialization). Thereafter, the input / output port (not shown) of the main control board 30 is cleared (step S50), and the RAM clear flag 76 is cleared (“5A [H]” → “00 [H]”) (step S51). , CTC75 is initialized (step S25 shown in FIG. 7). Thereafter, the CPU 71 is set to the interrupt prohibited state (step S26 shown in FIG. 7), and update processing is executed for various counters (step S27 shown in FIG. 7). After updating the counter, the CPU 71 is returned to the interrupt permission state (step S28 shown in FIG. 7), and the process returns to step S26 shown in FIG.

The processes in steps S43, S44, S45, S46, S50, and S51 are the same as the processes in steps S14, S15, S16, S17, S20, and S21 shown in FIG. Moreover, the process of step S49 is a process equivalent to the process of step S13 shown in FIG.
On the other hand, if the RAM clear signal received by the main control board 30 is at the H level (NO in step S42), it is determined whether or not the data (backup data) stored in the RAM 72 is valid (step S42). S52). If the backup data is valid (YES in step S52), then a return command process (step S53) and various processes at the time of return (step S54) are executed. Steps S52, S53, and S54 are the same as steps S22, S23, and S24 shown in FIG.

  When various processes at the time of return in step S24 are completed, the CTC 75 is initialized (step S25 shown in FIG. 7), and then the CPU 71 is set to the interrupt disabled state (step S26 shown in FIG. 7), and various counters are updated. Processing is executed (step S27 shown in FIG. 7). After updating the counter, the CPU 71 is returned to the interrupt permission state (step S28 shown in FIG. 7), and the process returns to step S26 shown in FIG. In the second embodiment, a periodic interrupt process similar to that shown in FIG. 8 is executed.

Next, a third embodiment will be described. In the third embodiment, unlike the first and second embodiments, the progress of the second period is monitored by the monitoring timer 77 in the periodic interrupt process.
FIG. 10 is a flowchart showing the contents of the system reset process in the pachinko machine according to the third embodiment of the present invention. In the system reset process in the third embodiment, in the flowcharts shown in FIGS. 5 to 7, the processes shown in FIG. 10 are executed instead of the processes in steps S12 to S24 (that is, the processes shown in FIG. 6). The This will be described with reference to FIGS.

  When the system reset process is started, the CPU 71 first sets itself to the interrupt disabled state and sets the interrupt mode 2 (steps S1 and S2 shown in FIG. 5). Thereafter, the value of the stack pointer in the CPU 71 is set to the final address (for example, 8000H) of the stack area, and the values of the respective registers are initialized (steps S3 and S4 shown in FIG. 5). Thereafter, the level of the RAM clear signal DEL is checked (step S5 shown in FIG. 5). Next, the CPU 71 waits while clearing the watchdog timer circuit 74 until the initialization of peripheral substrates is completed (steps S6 and S7 shown in FIG. 5), and then waits until the power supply abnormality signal is turned off. (Step S8 shown in FIG. 5).

  When the power supply abnormality signal is turned off, the CPU 71 enables the RAM 72 to write (S9: RAM write permission) and sends a standby screen display command to the effect control board 31 (step S10 shown in FIG. 5). Thereafter, the CPU 71 monitors reception of a power-on command from the payout control board 32 (step S11 shown in FIG. 5). When the power-on command is received (YES in step S11), the CPU 71 then proceeds to step 62 in FIG.

  The CPU 71 that has received the power-on command then determines whether or not an L level RAM clear signal has been received from the power board 61, that is, whether or not the RAM clear signal received from the power board 61 is at the L level. (Step S62). When the RAM clear operation is performed when the power is turned on, specifically, when the power is turned on while the RAM clear switch is pressed (YES in step S11 and YES in step S62), the main control board 30 An L level RAM clear signal is received from the substrate 61. On the other hand, when the power is turned on but the ram clear operation is not performed, specifically, when the power is turned on without pressing the RAM clear switch (YES in step S11 and NO in step S62), the main control board 30 Receives an H level RAM clear signal from the power supply board 61.

  If the RAM clear signal received by the main control board 30 is L level (YES in step S62), the entire area of the RAM 72 is cleared to zero (stored contents are initialized) (S63: RAM initialization). The main control board 30 transmits a RAM clear command for RAM clear notification to a peripheral board (for example, the effect control board 31) (step S65). When the effect control board 31 receives the RAM clear command, the effect control board 31 transmits a control command for RAM clear notification to the liquid crystal control board 63 and the lamp board 68. The liquid crystal control board 63 that has received this control command gives a message such as a predetermined RAM clear screen (for example, “RAM is being cleared”) to the liquid crystal display unit 15 for a first period (for example, 30 seconds). ) Is displayed.

  In addition, the lamp board 68 that has received this control command turns on the lamp unit 27 in a predetermined RAM clear notification mode during the first period. Further, when receiving the RAM clear command, the production control board 31 controls the sound output of the speaker 28 to output a predetermined alarm sound (RAM clear notification mode) from the speaker 28 for the first period, and also the game lamp 25. Is turned on in a predetermined RAM clear notification mode during the first period. In this RAM clear notification mode, all the lamps 25 and 27 of the pachinko machine 1 are lit and an alarm sound is output from the speaker 28 at a high volume. At this time, the alarm sound output from the speaker 28 is, for example, a high volume. .

Further, the CPU 71 outputs a RAM clear execution signal toward the external terminal board 33 (step S66). The RAM clear execution signal output from the main control board 30 is input to the hall control of the game store via the external terminal board 33.
After outputting the RAM clear execution signal, the input / output port (not shown) of the main control board 30 is cleared (step S70), and then the CTC 75 is initialized (step S25 shown in FIG. 7). Thereafter, the CPU 71 is set to the interrupt prohibited state (step S26 shown in FIG. 7), and update processing is executed for various counters (step S27 shown in FIG. 7). After updating the counter, the CPU 71 is returned to the interrupt enabled state, and the process returns to step S26.

The processes in steps S63, S65, S66, and S70 are the same as the processes in steps S13, S15, S16, and S20 shown in FIG.
On the other hand, if the RAM clear signal received by the main control board 30 is at the H level (NO in step S62), it is determined whether or not the data (backup data) stored in the RAM 72 is valid (step S62). S72). If the backup data is valid (YES in step S72), then a return command process (step S53) and various processes at the time of return (step S54) are executed. Steps S72, S73, and S74 are the same as steps S22, S23, and S24 shown in FIG.

  When various processes at the time of return in step S24 are completed, the CTC 75 is initialized (step S25 shown in FIG. 7), and then the CPU 71 is set to the interrupt disabled state (step S26 shown in FIG. 7), and various counters are updated. Processing is executed (step S27 shown in FIG. 7). After updating the counter, the CPU 71 is returned to the interrupt permission state (step S28 shown in FIG. 7), and the process returns to step S26 shown in FIG.

Next, a periodic interrupt process (periodic interrupt process) program that is executed every 4 msec with the main process suspended will be described. FIG. 11 is a flowchart showing the contents of periodic interrupt processing in the pachinko machine according to the third embodiment of the present invention.
When the periodic interrupt process is started, the time measurement by the monitoring timer 77 is started immediately at the start timing without saving the register of the CPU 71 (step S81). The monitoring timer 77 (for example, data corresponding to 30 seconds) is set at a predetermined timing (for example, immediately after S66) after RAM initialization on the system reset processing side. After the start of timing, the monitoring timer 77 is decremented until the value of the monitoring timer 77 becomes “0” (steps S81 and S84). Therefore, if the value of the monitoring timer 77 is greater than “0” (NO in step S81), it means that the second period has not elapsed since the start of the periodic interrupt processing.

When the value of the monitoring timer 77 reaches “0” (YES in step S81), a power supply abnormality check process is executed (step S82). This power supply abnormality check process is equivalent to the power supply abnormality check process in step S30.
After completion of the power supply abnormality check process in step S82, various processes in the regular process are executed (step S83). The various processes in the regular process mean various processes in the regular interrupt, and include, for example, the processes in steps S31 to S40 shown in FIG. That is, the various processes in the regular process include, for example, a regular-winning random number update process (S31 shown in FIG. 8), a timer subtraction process (S32 shown in FIG. 8), a switch input process (S33 shown in FIG. 8), and an error management process. (S34 shown in FIG. 8), prize ball management processing (S35 shown in FIG. 8), normal symbol determination processing (S36 shown in FIG. 8), jackpot determination processing (S37 shown in FIG. 8), lamp lighting processing (FIG. 8). S38), and an opening / closing accessory driving process (S39 shown in FIG. 8), and these processes are executed in a predetermined order. After all these processes are completed, the CPU 71 is returned to the interrupt enabled state, and the timer interrupt is completed.

As described above, according to this embodiment (third embodiment), the periodic interruption process does not proceed and is interrupted until the second period (for example, 30 seconds) elapses from the start of the RAM clear notification. Therefore, the progress of the game process by the main control board 30 is stopped until the second period elapses after the RAM is cleared.
Further, this is notified for a first period (for example, 30 seconds) after the RAM is cleared. In this embodiment, since the second period is the same length as the first period, the progress of the game process is stopped at least during the RAM clear notification. Thereby, the control processing of the main control board 30 and the effect control board 31 during the RAM clear notification can be restricted, and the processing burden on control can be reduced.

  Since the possibility of a player playing a game during the RAM clear notification is very low, even if the control processing of the main control board 30 and the effect control board 31 during the RAM clear notification is restricted, the player can execute the game. It is almost impossible to have an adverse effect. Thereby, the processing load on control during RAM clear notification can be reduced without adversely affecting the game execution by the player.

  Although three embodiments of the present invention have been described above, the present invention can be implemented in other forms. For example, as shown by a two-dot chain line in FIG. 11 in the third embodiment, the random number update process is executed even during subtraction of the monitoring timer 77, that is, before the timer value becomes “0”. It is also possible (step S91). The random number update process in step S91 is equivalent to the random number update process (S31) included in the various processes within the periodic interrupt in step S83.

If the random number is not updated until the second period (for example, 30 seconds) elapses, the random number is updated based on the expiration timing of the second period (the timing when the value of the monitoring timer 77 becomes “0”). Will be started. In this case, if the player knows the expiration timing of the second period, there is a possibility that a goto action using a sensory device or the like may be performed.
On the other hand, by executing the random number update process even during the subtraction of the monitoring timer 77, the random number is updated even before the second period elapses, thereby making it difficult for the player to know the update timing of the random number. be able to.

  Further, in each of the above-described embodiments, by monitoring the voltage level of the voltage drop signal DWN input to the input port while the game processing of the CPU 71 is stopped, the power is cut off while the game processing of the CPU 71 is stopped. The CPU 71 can grasp this fact. When there is a power interruption while the game processing of the CPU 71 is stopped, the checksum calculation target when the power is restored includes not only the work area in the RAM 72 but also the RAM clear flag area (RAM clear flag 76). Field (sum value target area at power recovery). On the other hand, the checksum calculation target at the time of backup processing is only the work area in the RAM 72 (the sum value target area at the time of backup processing) as described above. Therefore, the checksum data newly created at the time of power recovery and the SUM storage There is a discrepancy between the checksum data in the area. Therefore, when a power-off operation is performed while the game process of the CPU 71 is stopped, the RAM can be reliably cleared after the power is restored. And since RAM clear alerting | reporting is performed with RAM clear, the notification alerting period of the RAM clear alerting | reporting called 1st period can be ensured reliably.

  In each of the embodiments described above, the voltage drop signal DWN may be input to an NMI (Non Maskable Interrupt) terminal instead of the voltage drop signal DWN. In this case, a case is considered in which the power-off operation is performed while the game processing of the CPU 71 is stopped, and then the power is restored without performing the RAM clear operation. When there is a power interruption while the game processing of the CPU 71 is stopped, the checksum calculation target when the power is restored includes not only the work area in the RAM 72 but also the RAM clear flag area (RAM clear flag 76). Field (sum value target area at power recovery). On the other hand, since the target of the checksum operation at the time of the backup process is only the work area in the RAM 72 as described above, the checksum data newly created when the power is restored and the checksum data in the SUM storage area. A discrepancy occurs. Therefore, when a power-off operation is performed while the game process of the CPU 71 is stopped, the RAM can be reliably cleared after the power is restored. And since RAM clear alerting | reporting is performed with RAM clear, the notification alerting period of the RAM clear alerting | reporting called 1st period can be ensured reliably.

  Further, when the power is turned off while the game process of the CPU 71 is stopped, the CPU 71 refers to the RAM clear flag (information indicating that the RAM is cleared) when the power is restored, and if the RAM clear flag is set, the CPU 71 again By executing time setting and command transmission for RAM clear, execution of RAM clear and RAM clear notification may be secured after power is restored.

  Further, when the power is turned off while the game processing of the CPU 71 is stopped, the CPU 71 refers to the RAM clear notification timer (information indicating that the RAM is cleared) when the power is restored, and at least the notification timer is not zero. The RAM clear command may be transmitted to guarantee execution of the RAM clear notification after the power is restored. In this case, the RAM clear notification may be executed only for the remaining notification period, or the intended notification period RAM clear notification may be executed.

In each of the above-described embodiments, the first period for performing the RAM clear notification is described as 30 seconds. However, a period other than this can be provided as the first period. Further, in each of the above-described embodiments, the case where the second period is the same length as the first period has been described as an example. However, the second period can be set to a period longer than the first period.
In addition, the RAM clear notification mode of the liquid crystal display unit 15, the lamps 25 and 27, and the speaker 28 in each of the above-described embodiments is not limited to that described above, and the RAM clear notification can be executed using other modes. .

Further, although an example in which both the game lamp 25 and the lamp unit 27 are driven (lighted) in the RAM clear notification has been described, only one of the game lamp 25 and the lamp unit 27 may be driven (lighted). .
Further, the present invention is not limited to using all of the liquid crystal display unit 15, the speaker 28, and the lamps 25 and 27, and can be performed using at least one of the liquid crystal display unit 15, the lamps 25 and 27, and the speaker 28.

Further, the main control board 30 may be configured without the watch dog timer circuit 74.
Further, a backup RAM is provided on the main control board 30 in addition to the RAM 72. When the main control board 30 is backed up, the storage contents (data and checksum) of the RAM 72 of the main control board 30 are transferred to the backup RAM, and when the power is turned off. It may be kept in the backup RAM. In this case, the backup power supply voltage BU from the power supply board 61 is supplied only to the backup RAM.

Further, for example, a checksum is given as an example of the data error detection code, but a hash function can also be used as the data error detection code.
In each of the above-described embodiments, the backup function is provided in the main control board 30 and the payout control board 32 as an example. However, the backup function may be provided only in the main control board 30.

Further, the notification end timing of the RAM clear notification may be managed by the main control board 30 instead of the effect control board 31. And it is good also as a structure which transmits a predetermined | prescribed end command from the main control board 30 to the production | presentation control board 31 at the time of an expiration of an alerting | reporting period.
In the above-described embodiment, a pachinko machine has been described as an example of a gaming machine. However, the present invention is not limited to a pachinko machine and can be applied to other gaming machines such as a pachislot machine.

  In addition, various design changes can be made within the scope of matters described in the claims.

1 Pachinko machine (game machine)
15 Liquid crystal display unit (notification means)
25 Game lamp (notification means)
27 Lamp unit (notification means)
28 Speaker (notification means)
30 Main control board (Main control unit)
31 Production control board (RAM clear notification control means)
61 Power supply board (backup means)
77 Monitoring timer (time measuring means)

Claims (5)

A gaming machine,
A main control unit for controlling and controlling the progress of game processing in the gaming machine;
An effect control unit that executes an effect operation according to a control command from the main control unit,
Informing means controlled by the effect control unit;
Backup means for continuing to hold data in the RAM included in the main control unit when the power to the main control unit is shut off;
RAM clear execution means for initializing the storage contents of the RAM,
The production control unit includes a RAM clear notification control means for controlling the notification means so as to execute a predetermined RAM clear notification mode during a predetermined first period related to initialization of the RAM,
The main control unit includes a game process stop / progress unit that stops the progress of the game process during a predetermined second period including the first period and advances the game process after the second period has elapsed. Gaming machine.   The gaming machine according to claim 1, wherein the second period is a period overlapping with the first period.   The game according to claim 1, wherein the game process progress / stop means includes system reset delay means for delaying completion of a system reset process that is activated based on power-on in order to stop the progress of the game process. Machine.   The said game process progress / stop means includes the periodical interruption progress stop means for stopping the progress of the periodical interrupt process that should be started every predetermined time in order to stop the progress of the game process. The gaming machine according to any one of the above. The main control unit
Means for transmitting a predetermined RAM clear-related command to the effect control unit in relation to initialization of the stored contents of the RAM;
And further includes time measuring means for measuring the time since the RAM clear related command was transmitted to the effect control unit,
The RAM clear notification control means executes a notification operation for notifying initialization of the RAM in response to reception of a RAM clear related command,
The game process stop / progress means stops the progress of the game process from the start of timing by the timing means until it is counted by the timing means that the second period has elapsed. The gaming machine according to any one of the above.

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