JP2009018119A - Game machine - Google Patents

Abstract

A gaming machine that effectively eliminates illegal games.
A configuration is adopted in which even when a CPU of a main control unit 1 that is centrally responsible for game control operations including a lottery process goes into a runaway state, the CPU is left without being forcibly reset. The main control unit 1 and the payout control unit 5 are each configured to be supplied with a clear signal CLR indicating a switch operation when a switch operation is performed to erase the stored contents of each memory. The payout control unit 5 transmits a confirmation signal ACK to the main control unit 1 only when the payout control unit 5 receives the clear signal CLR before starting a typical game control operation. Unless the main control unit 1 receives the confirmation signal ACK, the next operation of the main control unit 1 is not started.
[Selection] Figure 4

Description

  The present invention relates to a gaming machine that includes a computer circuit, and more particularly to a gaming machine that can effectively eliminate fraudulent games.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a profit state advantageous to the player. However, in actuality, whether or not the big hit state is determined in advance by the big hit lottery process based on the winning of the game ball, and the symbol display section performs the symbol changing operation exclusively to increase the player.

  In the big win lottery process, the counter variable CT updated every predetermined time is used, and the value of the counter variable CT (random value RND) acquired at the time of winning the game ball is compared with the winning value Hit to determine whether or not the big win state. Is decided. If the RWM clear signal is ON after the power is turned on, the counter variable CT is initialized to zero by zero clearing (RWM clear processing) of all areas of the RWM (Read Write Memory), and thereafter every predetermined time. The predetermined numerical value range (0 to MAX-1) is circulated by an increment operation or the like executed at the same time.

  By the way, the above-described update rules for the winning value Hit and the counter variable CT can be found by obtaining a gaming machine and analyzing the control program. Therefore, it is relatively easy to intentionally generate a winning state by using an improper instrument if it is the first cycle of the cyclic operation within a predetermined numerical range immediately after the power is turned on and after the RWM clear process is performed. is there. Therefore, there is a concern about an illegal act of resetting the RWM clear signal to execute the RWM clear process while resetting the CPU without shutting off the power.

In addition, Patent Document 1 and Patent Document 2 propose that a liquid crystal display notifies that RWM has been cleared to zero, but in the first place, such countermeasures are effective even if RWM is cleared to zero. Measures that can be eliminated are more effective.
JP 2003-033532 A Japanese Patent Laid-Open No. 2003-205161

  The present invention has been made based on the above idea, and an object thereof is to provide a gaming machine that can effectively eliminate fraudulent games when the RWM is cleared to zero.

  In order to achieve the above object, the invention according to claim 1 executes a lottery process based on a player's operation or a winning state of a game medium, and provides a profit state advantageous to the player based on the lottery result. A main control unit that is centrally responsible for game control operations including the lottery process, and a sub-control that executes individual game control operations based on control commands received from the main control unit Even if the CPU of the main control unit is in a runaway state, the CPU is left without being forcibly reset, and the main control unit and the sub control unit Is configured such that when a switch operation is performed to erase the stored contents of each memory, a clear signal indicating the switch operation is supplied, and only after the power is turned on, at the start of a steady game control operation, The sub There is provided a first means for transmitting a confirmation signal from the control section to the main control section, and a second means for not starting the next operation of the main control section unless the main control section receives the confirmation signal. It is characterized by that.

  In the invention according to claim 1, even if the unauthorized player resets only the CPU of the main control unit and supplies a clear signal to the main control unit without shutting off the power supply, the sub control unit to the main control unit On the other hand, since the confirmation signal is not transmitted, the game control operation is surely stopped and the illegal game is not successful.

  In the present invention, preferably, a flag setting means for setting a determination flag to an ON value after the CPU of the sub control unit is reset and before a steady game control operation is started, and the sub control unit After the steady game control operation is started, the value of the determination flag is determined. If the determination flag value is ON value, it is changed to OFF value and the confirmation signal is output to the main control unit. The sub-control unit should include a transmission unit and a monitoring unit that continuously monitors whether the determination flag is an OFF value while executing a steady game control operation of the sub-control unit.

  Alternatively, preferably, after the CPU of the sub-control unit is reset, a flag setting means for setting a specific bit of output data to an ON value until a steady game control operation is started, and the sub-control When the regular game control operation is started in the unit, the sub-control unit is provided with transmission means for setting the specific bit to an OFF value after outputting the specific bit to the main control unit as a confirmation signal Should.

  The invention according to claim 4 is a gaming machine that executes a lottery process due to a player's operation or a winning state of a game medium, and generates a profit state advantageous to the player based on the lottery result. And a main control unit that is centrally responsible for game control operations including the lottery process, and a sub-control unit that executes individual operations based on control commands received from the main control unit. The clear signal indicating the switch operation is supplied to the main control unit when the switch operation is performed to erase the stored contents of the memory, and the clear signal received by the main control unit is Whether or not the stored contents of the memory are erased before the regular game control operation is started after the CPU of the sub control unit is reset. Depending on the judgment flag Flag setting means for setting an ON value or an OFF value at the same time, and after the steady control operation of the sub-control unit is started, the value of the determination flag is determined and the stored contents of the memory are erased In the case of an ON value indicating a flag change means for changing this to an OFF value, and while the determination flag is in an OFF value state, the sub-control unit performs a steady game control operation, Time consumption means for consuming a predetermined time; then, signal monitoring means for monitoring a clear signal transferred from the main control section while executing a steady game control operation of the sub-control section; and the signal monitoring means When the clear signal is detected by the above, the sub control unit is provided with stop means for stopping the subsequent operation in the sub control unit.

  In the invention according to claim 4, the sub-control unit monitors a clear signal transferred from the main control unit while executing a steady game control operation. Therefore, when only the CPU of the main control unit is reset without shutting off the power supply and an illegal clear signal is supplied to the main control unit, this clear signal is immediately detected by the sub-control unit. And since subsequent operation | movement of a sub-control part is stopped, an illegal game is not made successful.

  Incidentally, an initialization switch is generally used to erase the stored contents of the memory of the main control unit and / or sub-control unit when the power is turned on. This initialization switch is usually composed of an output terminal pulled up by the main control unit and / or the sub control unit, and a switch for opening and closing the ground line of the power supply board. Then, the initialization switch is turned on before the power is turned on and turned off after the power is turned on to generate a clear signal, which is supplied to the main control unit and / or the sub control unit.

  However, in such a configuration, the clear signal may not function if the staff releases the initialization switch too early. In particular, if the hand is released from the initialization switch before the power is turned on, no clear signal is generated in the first place. In addition, since the timing at which the staff releases the initialization switch is also random, the clear signal cannot be used effectively.

  However, according to the inventions of claims 5 and 6, the above problem can be solved. These inventions are particularly effective when combined with the inventions of claims 1 and 4.

  The invention according to claim 5 is a gaming machine that executes a lottery process due to a player's operation or a winning state of a game medium, and generates a profit state advantageous to the player based on the lottery result, The main control unit is responsible for the game control operation including the lottery process, and the sub control unit executes an individual game control operation based on a control command received from the main control unit. , An initialization switch that can be turned on prior to turning on the power, a capacitor that is charged regardless of whether the power is turned on when the initialization switch is turned on, and cleared after the power is turned on until the capacitor is discharged A pulse output unit that outputs a signal, and when the main control unit and / or the sub-control unit receives the clear signal before starting a steady game control operation after turning on the power, Memory It is configured to erase the contents.

  The invention according to claim 6 is a gaming machine that executes a lottery process due to a player's operation or a winning state of a game medium, and generates a profit state advantageous to the player based on the lottery result, The main control unit is responsible for the game control operation including the lottery process, and the sub control unit executes an individual game control operation based on a control command received from the main control unit. An initialization switch that can be turned on prior to turning on the power, an operation detection unit that outputs a trigger signal when the initialization switch is turned on when the power is turned on, and a predetermined pulse width that receives the trigger signal. Each of the main control unit and / or the sub control unit receives the clear signal before starting a steady game control operation after the power is turned on. Memory憶 is configured to erase the contents.

  According to a sixth aspect of the present invention, there is provided an initialization switch that can be turned on prior to turning on the power, an operation detection unit that outputs a trigger signal when the initialization switch is turned on when the power is turned on, and the trigger signal. It is preferable to provide a clear circuit having a pulse output unit that receives and outputs the clear signal having a predetermined pulse width.

  In this case, the operation detection unit receives a switch signal indicating the ON / OFF state of the initialization switch, and a system reset signal for resetting the power of the CPUs of the main control unit and the sub control unit, respectively. It is preferable to have an element. More preferably, a delay unit for receiving and delaying the system reset signal should be further provided, and another gate element for receiving the output of the gate element and the delay unit and outputting the trigger signal should be provided.

  In any of the above-described inventions, the operations of the main control unit and the sub control unit are configured to include a main process that starts after power-on and ends with an infinite loop process, and a timer interrupt process that starts at regular intervals. In this case, it is preferable that the regular game control operation is executed by the timer interrupt process in both the main control unit and the sub control unit.

  As described above, according to the present invention, it is possible to realize a gaming machine that can effectively eliminate fraudulent games when the RWM is cleared to zero.

  Hereinafter, embodiments of the present invention will be described in detail. FIG. 1 is a block diagram illustrating an overall circuit configuration of a pachinko machine according to an embodiment. Broken lines in the figure mainly indicate DC voltage lines.

  As shown in the figure, this pachinko machine has a power supply board 7 that receives 24V AC and outputs various DC voltages, a system reset signal SYS, an RWM clear signal CLR, and the like, and a main control board 1 that is centrally responsible for game control operations. An effect control board 2 that executes a lamp effect and an audio effect based on a control command CMD ′ received from the main control board 1, an effect interface board 3 that transmits a signal received from the effect control board 2 to each part, and an effect The liquid crystal control board 4 that drives the liquid crystal display DISP based on the control command CMD "received from the interface board 3 and the payout motor M based on the control command CMD received from the main control board 1 are used to pay the game ball. The payout control board 5 to be taken out and the launch control board 6 for launching a game ball in response to the player's operation are mainly configured.

  Here, the main control board 1, the production control board 2, the liquid crystal control board 4, and the payout control board 5 are each equipped with a computer circuit including a one-chip microcomputer. Therefore, in this specification, the main control board 1, the production control board 2, the liquid crystal control board 4, and the circuits mounted on the payout control board 5 and the operations realized by the circuits are generically named. It may be called the control part 1, the production control part 2, the liquid crystal control part 4, and the payout control part 5. Note that all or part of the effect control unit 2, the liquid crystal control unit 4, and the payout control unit 5 are sub-control units.

  The main control unit 1 transmits a control command CMD to the payout control unit 5 in one direction. The payout control unit 5 pays out a designated number of prize balls based on the control command CMD received from the main control unit 1. Specifically, the required prize ball motion is realized by rotating the payout motor M.

  On the other hand, the payout control unit 5 transmits a confirmation signal ACK indicating that the RWM clear signal CLR has been received from the power supply board 7 to the main control unit 1. In addition, the payout control unit 5 transmits to the main control unit 1 a prize ball count signal indicating the payout operation of the game ball and a status signal CON related to an abnormality in the payout operation. Note that the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal.

  Further, the payout control unit 5 outputs an AC voltage AC24V and a launch control signal CTL to the launch control board 6. The launch control signal CTL is a condition for operating the launch solenoid. When the launch control signal CTL is at the L level, the launch operation of the game ball is prohibited.

  By the way, the DC 5 V backup power supply BU is supplied from the power supply board 7 to the main control unit 1 and the payout control unit 5. Therefore, even after the AC power supply 24V is shut off due to the end of business or a power failure, the RWM data inside the one-chip microcomputer is retained. In this embodiment, it is designed so that the stored contents of the RWM are retained for at least several days.

  Further, the power supply board 7 is configured to output a voltage drop signal ABN to the main control unit 1 and the payout control unit 5 when the AC power supply 24V is shut off. In this embodiment, the voltage drop signal ABN is supplied to the input port instead of the interrupt terminal of each one-chip microcomputer. The main control unit 1 and the payout control unit 5 grasp the level drop of the voltage drop signal ABN by the flag sense method, and then save necessary data in the RWM. Therefore, coupled with the operation of the backup power supply BU described above, the main control unit 1 and the payout control unit 5 can resume the operation before the power shutoff at the start of business or at the time of recovery from a power failure.

  Furthermore, the power supply board 7 has the RWM clear signal CLR (hereinafter abbreviated as the clear signal CLR) indicating that the initialization switch SW (FIG. 2) has been turned ON with respect to the main control unit 1 and the payout control unit 5. May be output). Therefore, each control board 1 and 5 can grasp the ON / OFF state of the initialization switch SW by determining the level of the clear signal CLR. The initialization switch SW is a rebound switch, and is turned on by an attendant prior to the power switch when the stored contents of the RWM held by the backup power supply BU are to be erased.

<First Embodiment>
FIG. 2 shows the connection relationship between the power supply board 7 and the main control board 1 and the payout control board 5 for the first embodiment. As shown in the figure, the main control board 1 and the payout control unit 5 receive not only the DC power supply voltage including the backup power supply BU but also the clear signal CLR for clearing the RWM and the voltage drop of the AC power supply from the power supply board 7. The voltage drop signal ABN shown and the system reset signal SYS are received. The clear signal CLR is supplied in synchronization with the input port IN1 of the main control unit 1 and the input port IN3 of the payout control unit 5.

  The payout control unit 5 receives a control command CMD from the output port OUT1 of the main control unit 1 via the input port IN4, while receiving a status signal from its own output port OUT2 to the input port IN2 of the main control unit 1. CON and confirmation signal ACK are transmitted. The drive pulse for the payout motor M is output from the output port OUT3. The payout control unit 5 outputs the firing control signal CTL described above to the firing control board 6.

  FIG. 4 is a flowchart for explaining the operation contents of the main control unit 1 when the power is turned on in the first embodiment. This main process ends with the infinite loop process of steps ST13 to ST15, but the original process for controlling the game operation is started at predetermined time intervals (4 mS) during the infinite loop process (ST13 to ST15). This is executed in the timer interrupt processing. In the first embodiment, the watchdog timer circuit is not provided, and the CPU (equivalent to Z80 CPU) is not forcibly reset. However, the payout control unit 5 may or may not be provided with a watchdog timer circuit.

  Hereinafter, the main process of the main control unit 1 will be described with reference to FIG. The main process is started when the power is turned on without the initialization switch SW (FIG. 2) being operated as in the case of recovery from the power failure state, and when the initialization switch SW is turned on. Sometimes the power is turned on.

  In any case, the Z80 CPU first sets itself to the interrupt disabled state (ST1) and sets to the interrupt mode 2 (ST2). Further, the value of the stack pointer SP in the CPU is initialized to the final address of the stack area (ST3). Next, after initializing the values of internal registers including each part of the one-chip microcomputer (ST4), the value of the RWM clear signal CLR is determined (ST5). As described above, the RWM clear signal CLR is a signal for determining whether or not to initialize all areas of the built-in RWM of the one-chip microcomputer, and the ON / OFF state of the initialization switch SW operated by the staff It has a value corresponding to.

  Here, assuming that the RWM clear signal CLR is in the ON state, following the determination in step ST5, the entire area of the built-in RWM is cleared to zero (ST9). Therefore, the value of the backup flag BFL set when the power is turned off becomes zero together with other checksum values.

  Next, after the RWM clear command for notifying that the RWM area has been cleared to zero is output (ST10), it waits for the confirmation signal ACK to be transmitted from the payout control unit 5 (ST11). As will be described later with reference to step ST52 in FIG. 6, the confirmation signal ACK is transmitted at the final timing in the first timer interrupt process in the payout control unit 5. Therefore, the main control unit 1 can confirm from the confirmation signal ACK that the initial operation of the payout control unit 1 is completely completed.

  If the confirmation signal ACK can be received, the CTC (Z80 counter timer circuit) that outputs an interrupt signal for starting the timer interrupt operation is initialized (ST12), and the CPU is set to the interrupt disabled state (ST13). Update processing is executed for various counters (ST14), and then the CPU is returned to the interrupt enabled state (ST15) and the process returns to step ST13.

  By the way, returning to the determination process of step ST5, the description will be continued. At the time of recovery from the power failure state, the initialization switch SW (RWM clear signal CLR) is in the OFF state. In such a case, the content of the backup flag BFL is determined following the determination in step ST5 (ST6). The backup flag BFL is set to 5AH when the power is shut off, and is reset to zero in the first timer interrupt processing after the power is restored.

  Therefore, when the power is turned on or when recovering from the power failure state, the content of the backup flag BFL is 5AH. However, the backup flag BFL = 00H if the predetermined processing is not completed before the power is shut off for some reason. Therefore, if BFL ≠ 5AH (normally BFL = 00H), the process proceeds from step ST6 to step ST9 to return the operation of the gaming machine to the initial state.

  On the other hand, if the backup flag BFL = 5AH, a checksum calculation for calculating a checksum value is executed (ST7). Here, the checksum operation is an 8-bit addition operation for the work area of the built-in RWM. When the checksum value is calculated, the calculation result is compared with the stored value at the SUM address of the RWM (ST8).

  The SUM address stores a checksum value obtained by the same checksum calculation when the power is shut off. The stored calculation result is maintained by the backup power source together with other data of the built-in RWM. Therefore, the two should be matched by the determination in step ST8.

  However, if the checksum calculation cannot be executed when the power is turned off, or if the data in the work area is damaged after the execution of the checksum calculation (ST7) of the main process even if it can be executed In such a case, the determination result in step ST8 is inconsistent. If data corruption is detected due to a discrepancy between the determination results, the process proceeds to step ST9 to execute the RWM clear process, and the operation of the gaming machine is returned to the initial state. On the other hand, if it is determined in step ST8 that the checksum value obtained by the checksum calculation (ST7) matches the stored value at the SUM address, the process proceeds to step ST11.

  Subsequently, the operation content of the payout control unit 5 in the first embodiment will be described with reference to FIGS. 5 and 6. The operation of the payout control unit 5 can be outlined as follows: a main process (FIG. 5A) that starts after power-on and ends with an infinite loop process, and a reception interrupt process that is activated by a strobe signal STB from the main control unit 1 ( 5 (b)) and timer interrupt processing (FIG. 6) started every fixed time (2mS).

  As shown in FIG. 5B, in the reception interrupt process, the control command CMD is acquired from the input port IN4 (FIG. 2), stored in the command buffer area of the RWM (ST101), and then the CPU is permitted to interrupt. The state (EI) is set and the process ends (ST103).

  Next, the operation content of the main process (FIG. 5A) will be described. This process is almost the same as the main process of the main control unit 1 described with reference to FIG. That is, the process of step ST22 of the payout control unit 5 corresponds to steps ST2 to ST4 of FIG. 4, and the processes of steps ST23 to ST2 correspond to steps ST5 to ST8 of FIG. Steps ST21 and ST28 are the same processes as steps ST1 and ST9 in FIG. The clear signal determined in step ST23 is the RWM clear signal CLR transmitted from the power supply board 7.

  The payout control unit 5 expresses the backup flag BAK to distinguish it from the backup flag BFL. Then, the payout control unit 5 immediately resets the backup flag BAK to zero if the result of the sum calculation in step ST25 matches (ST27).

  In any case, when the process of step ST27 or the process of step ST28 is completed, the value of the determination flag FLG is set to 5AH (ST29). In the first embodiment, the determination flag FLG is used for determining whether or not the power is on, and enables the operation of returning the confirmation signal ACK to the main controller 1 only once when the power is turned on ( (See FIG. 6).

  Next, a CTC (Z80 counter timer circuit) that outputs a timer interrupt signal is initialized (ST30), the CPU is set in an interrupt enabled state (ST31), and the infinite loop process is repeated.

  During execution of this infinite loop process, the timer interrupt process shown in FIG. 6 is executed at regular time intervals (2 mS). Here, in the command analysis process (ST44), the control command CMD acquired in the reception interrupt process is analyzed, and a prize ball operation is executed based on the analysis result.

  Specifically, the winning ball operation is realized by motor processing (ST49) for preparing drive data to be output to the payout motor M and data output processing (ST50) for outputting the prepared drive data. Then, whether or not the payout motor M rotationally driven by the data output process (ST50) actually paid out the prize ball is confirmed by the data input process (ST42) and the prize ball process (ST47).

  Further, in this data output process (ST50), not only the light emitting diode lighting process such as error notification, but also the transmission process (ST51 to ST53) of the confirmation signal ACK to the main control unit 1 is executed. That is, at the end of the data output process (ST50), the value of the determination flag FLG is checked (ST51). If the value is 5AH, the confirmation signal ACK is sent from the output port OUT2 to the main control unit 1. After the output (ST52), the determination flag FLG is reset to zero (ST53). As the determination flag FLG is reset to zero (ST53), the confirmation signal ACK is not output in subsequent timer interruptions.

  Thus, in the first embodiment, the confirmation signal ACK is output by the process of step ST53 only once when the power is turned on. Then, in the main control unit 1 that has received the confirmation signal ACK, the operation is shifted from step ST11 in the standby state to step ST12, and gaming control of the gaming machine is started in earnest.

  Since the data output process (ST50) is arranged at the end of the timer interrupt process, the operation in the payout control unit 5 is reliably started at the timing when the main control unit 1 receives the confirmation signal ACK. Therefore, the payout control unit 5 does not miss the control command CMD transmitted by the main control unit 1.

  In addition, since the confirmation signal ACK is output only once when the power is turned on, for example, even if an unauthorized player intentionally uses the RWM clear signal CLR to intentionally generate a big hit state, the prospect is successful. There is nothing. That is, the main control unit 1 continues to wait for the confirmation signal ACK even if the CPU of the main control unit 1 is forcibly reset without shutting down the power and the RWM clear signal CLR is intentionally lowered to the L level. Therefore, the control operation is not started (ST11).

  Note that the standby process in step ST11 is not canceled unless the confirmation signal ACK is received. Therefore, a similar standby state also occurs in the case of a CPU reset operation by the watchdog timer. Therefore, in this embodiment, the watchdog timer circuit is not provided. However, experience shows that it is extremely rare for the CPU to be in a runaway state regardless of the illegal gaming behavior, and thus no adverse effects occur.

  Rather, there is an advantage that an illegal player can use an electromagnetic noise or the like to make the CPU runaway and misuse the forced reset operation of the CPU by the watchdog timer circuit to eliminate the illegal act of clearing the RWM to zero.

  Although the first embodiment has been described above, instead of the process of step ST29, the specific bit corresponding to the confirmation signal in the output 8-bit data prepared in the memory may be set to the ON state (FIG. 5). (See dashed line). However, in this case, in the data output process (ST50), after the specific bit is transmitted to the main control unit 1 every time, it is set to the OFF state (see the broken line portion in FIG. 6). Therefore, even in such a configuration, the confirmation signal of the ON state is transmitted to the main control unit 1 only once after the power is turned on.

Second Embodiment
As described above, the first embodiment in which the watchdog timer circuit is not provided has been described, but the present invention is not necessarily limited to this configuration. 3 and 7 to 9 are drawings for explaining the second embodiment.

  As shown in FIG. 3, in the second embodiment, the clear signal CLR received from the power supply board 7 by the main control unit 1 is transferred to the payout control unit 5 as it is and supplied to the input port IN3 of the payout control unit 5. Yes. In order to distinguish from the clear signal CLR received from the power supply board 7 by the payout control unit 5, the clear signal CLR transferred from the main control unit 1 may be particularly referred to as a transfer clear signal CLR. In addition, the clear signal CLR that the payout control unit 5 receives from the power supply board 7 may be referred to as a direct clear signal CLR. However, in the second embodiment, the direct clear signal CLR is not essential and can be omitted.

  In the second embodiment, the confirmation signal ACK is not transmitted from the payout control unit 5 to the main control unit 1, but transmission of the confirmation signal ACK is not prohibited. In the second embodiment, the main control unit 1 is provided with a watchdog timer circuit so that when the CPU is out of control, the CPU is forcibly reset to resume game control. However, in the second embodiment, as in the first embodiment, a configuration in which a watchdog timer circuit is not provided may be employed.

  FIG. 7 is a flowchart for explaining main processing of the main control unit 1 in the second embodiment. As is clear from the comparison between FIG. 7 and FIG. 4, the second embodiment is the same as the first embodiment except that the waiting process (ST11) for the confirmation signal ACK is not provided. However, as described above, of course, the process of step ST11 may be provided.

  FIG. 8 is a flowchart for explaining the main process of the payout control unit 5 in the second embodiment. As apparent from the comparison between FIG. 8 and FIG. 5A, in the second embodiment, when the RWM clear process (ST28) is executed, the determination flag FLG is set to 5AH (ST29), and the RWM clear is performed. If the process (ST28) is not executed, the determination flag FLG is set to 00H (ST27). If the RWM clear process (ST28) is not executed, the timer variable TIME is initialized to 1000.

  In this embodiment, the determination flag FLG is used to store the operation content when the power is turned on. In addition, the timer variable TIME is used to secure a time until the clear signal CLR that is artificially generated and artificially disappears by the pressing operation of the initialization switch SW is surely disappeared. That is, in the payout control unit 5, since the timer interrupt is activated every 2 mS, 2 seconds is secured as the time until the clear signal CLR disappears reliably by initializing the timer variable TIME to 1000. .

  As shown by the broken line in FIG. 8, when the watchdog timer circuit is provided in the payout control unit 5, 5AH is set in the determination flag FLG immediately after the process of step ST23. Accordingly, in response to this, in the RWM clear process (ST28), the RWM area is cleared to zero except for the determination flag FLG.

  FIG. 9 illustrates a part of the timer subtraction process (ST43) and the data output process (ST50) in the second embodiment, and shows a characteristic operation of the present embodiment. First, timer interrupt processing will be described for the case where the initialization switch SW is turned on after power is turned on.

  In such an operating state, as a result of the RWM clear process (ST28), the timer variable TIME is zero, so the process of step ST71 shown in FIG. 9A is skipped (ST70). On the other hand, in the final process of the data output process (ST50) shown in FIG. 9B, since the timer variable TIME is zero, the value of the determination flag FLG set in the process of step ST27 or step ST29 of FIG. Is checked (ST60 to ST61).

  Here, since it is assumed that the staff member has turned on the initialization switch SW when the power is turned on, the determination flag FLG = 5AH should be obtained after the RWM clear process (ST28) is executed. Therefore, the determination flag FLG is reset to zero, and the timer variable TIME is initialized, and the process ends (ST62). As in step ST27, the timer variable TIME is initially set to 1000 because the timer interrupt cycle is 2 ms.

  Thereafter, the timer variable TIME initialized to 1000 is decremented in the timer subtraction process (ST71), and the process from step ST61 onward is prohibited until it becomes zero (= 2 seconds). On the other hand, when 2 seconds have passed, the transfer clear signal CLR and the direct clear signal are acquired from the input port IN3 through the processing of step ST60 → step ST61 (ST63).

  At this timing, since at least 2 seconds have passed since the power was turned on, the attendant must have released his hand from the initialization switch SW. As a result, the direct clear signal and the transfer clear signal CLR are also reliably turned off. It must be in a state. Therefore, after the determination in step ST64, the data output process is finished without doing anything.

  The operation content has been described above on the assumption that the clerk has turned on the initialization switch SW when the power is turned on. On the other hand, if the initialization switch SW is not turned ON, the determination flag FLG is reset to zero in the main process (ST27), and the timer variable TIME is initialized to 1000 (ST27).

  Therefore, after 1000 timer interruptions, the process of steps ST60 → ST61 → ST63 is executed, and the value of the clear signal CLR is determined (ST63). As in the previous case, at least 2 seconds have passed since the power was turned on, the clerk must be released from the initialization switch SW, and as a result, the clear signal CLR is also surely turned off. It should be a habit. Therefore, if it is confirmed in step ST64 that the clear signal CLR is in the OFF state, the data output process is finished without doing anything.

  As described above, in the second embodiment, the value of the clear signal CLR is checked in a steady state in which the gaming machine is executing a gaming operation. Therefore, even if an unauthorized player tries to intentionally generate a big hit state by exploiting the RWM clear signal CLR, the prospect will not succeed. That is, if the CPU of the main control unit 1 is forcibly reset without shutting down the power supply and the RWM clear signal CLR is intentionally lowered to the L level, the fact is determined by the payout control unit 5 in step ST64. Immediately reveal at.

  In this case, the payout control unit 5 executes the abnormality process based on the transfer clear signal CLR in the ON state (ST65). The content of the abnormal process is not particularly limited, but for example, a buzzer sound is sounded and the launch control signal CTL supplied to the launch control board 5 is changed to L level to prohibit the launch operation of the game ball. Also, the winning ball operation and other processes are stopped in an infinite loop. Therefore, even if the big hit state can be generated, no prize ball can be obtained.

  For the purpose of eliminating erroneous determination, the abnormality process should be executed only when the clear signal CTL is continuously ON for a predetermined number of times (MAX) (ST600).

<Third Embodiment>
By the way, in the above description, the structure which detects a fraudulent game in the payout control part 5 was taken. However, it is not necessary to be limited to this configuration, and the main control unit 1 may be configured to detect unauthorized games. FIG. 10 is a flowchart showing a main process of the main control unit 1 in the third embodiment. This process is substantially the same as the main process of the payout control unit 5 shown in FIG. 8, and the broken line part is a characteristic part.

  Further, the timer interrupt process of the main control unit 1 is substantially the same as the timer interrupt process of the payout control unit 5 shown in FIG. In the third embodiment, needless to say, transfer of the clear signal CLR from the main control unit 1 to the payout control unit 5 is not necessary.

<Fourth embodiment>
By the way, in each above-mentioned embodiment, 2 seconds were ensured as a time until a staff member cancels the ON operation of the initialization switch SW. However, if the initialization switch SW is kept on even after 2 seconds, the abnormal process (ST65) will be executed. In addition, there is a possibility that the initialization switch SW is turned on after the power switch is turned on. In such a case, the abnormality process (ST65) is executed.

  Therefore, in order to solve such a problem, it is preferable to provide a clear circuit shown in FIG. 11A in relation to the initialization switch SW. The clear circuit includes a NOT gate G1 that inverts the clear signal CLR, an AND gate G2 that receives the inverted clear signal PSH and the system reset signal SYS, a delay circuit 10 that delays and inverts the system reset signal SYS, and a delay circuit 10 and an NAND gate G4 that receives the output of the AND gate G2, and a one-shot multivibrator 11 that starts when the output OT of the NAN gate G4 falls.

  The system reset signal SYS is a signal for resetting the power of the CPU of each control board, and maintains the L level for a predetermined time from the rising timing of the power supply voltage (indicated as power ON in FIG. 11). .

  As shown in the figure, one of the initialization switches SW is connected to the ground, and the other is pulled up and supplied to the NOT gate G1. The delay circuit 10 is constituted by a series circuit of an integrating circuit composed of a resistor R1 and a capacitor C1 and a NOT gate G3. The one-shot multivibrator 11 is composed of two NAND gates G5 and G6 and a differentiation circuit including a resistor R2 and a capacitor C2. Therefore, the output signal CLR ′ of the one-shot multivibrator 11 is at the L level for a predetermined time τ defined by the time constant R2 × C2.

  The output signal CLR ′ of the clear circuit shown in FIG. 11A (the output signal of the one-shot multivibrator 11) has a constant pulse width τ regardless of the duration of the ON operation time of the initialization switch SW by the attendant. . Even if the initialization switch SW is operated after the power switch is turned on, the output signal CLR 'of the clear circuit does not change as long as the timing is after T1. Therefore, if the output signal CLR ′ of the clear circuit is supplied to the main control unit 1 and the payout control unit 5 as the RWM clear signal, the above-described troubles can be surely solved.

  Note that the power supply voltage is also supplied to the input terminal of the NAND gate G4, thereby preventing the clear circuit from malfunctioning when the voltage is unstable immediately after the power is turned on. Further, if an OR gate G7 for receiving the output DLY of the delay circuit 10 and the clear signal CLR is provided and the light emitting diode LP is turned on based on the output of the OR gate G7, the clerk releases the initialization switch SW. A good timing is demonstrated. That is, the light-emitting diode LP is turned on when the one-shot multivibrator 11 starts to operate reliably, and then turned off when the clerk releases the initialization switch SW. Thus, the possibility of erroneous operation of the clerk is greatly reduced. The

  By the way, even when the circuit configuration of FIG. 11A is adopted, if the hand is released from the initialization switch SW before the power is turned on, the clear signal is not generated and the RWM clear process cannot be executed. Therefore, in order to solve such a problem, it is preferable to adopt the circuit configuration shown in FIG.

  The initialization switch circuit includes an initialization switch SW, a transformer TR, a rectifier circuit, and a NOT gate G8. In this circuit, the AC 24V is short-circuited between the initialization switch SW and the primary coil of the transformer TR on the upstream side of the power switch PW. The AC voltage of the secondary coil of the transformer TR is rectified by the diode D and the smoothing capacitor C4.

  Therefore, in this initialization switch circuit, it is sufficient for the staff to turn on the rebound type initialization switch SW for a moment prior to turning on the power switch PW. That is, the smoothing capacitor C4 is charged by the ON operation of the initialization switch SW, and then, after the power switch PW is turned on, only a predetermined time (for example, set to 1 second) until the charged charge of the smoothing capacitor C4 is naturally discharged. The clear signal CLR is maintained at the L level.

  Note that if the initialization switch SW is kept pressed even after the power is turned on, the clear signal CLR does not return to the H level. However, if the clear signal CLR output from the initialization switch circuit is supplied to, for example, the clear circuit shown in FIG. 11A, the clear signal CLR ′ having a predetermined pulse width can be generated.

  Finally, a bullet ball game machine to which the present invention is preferably applied will be described for confirmation. FIG. 12 is a perspective view showing the pachinko machine 21 of the present embodiment, and FIG. 13 is a side view of the pachinko machine 21. A plurality of pachinko machines 21 are arranged in the length direction of the island structure of the pachinko hall while being electrically connected to the card-type ball lending machine 22.

  The illustrated pachinko machine 21 includes a rectangular frame-shaped wooden outer frame 23 that is detachably mounted on an island structure, and a front frame 24 that is pivotably mounted via a hinge H fixed to the outer frame 23. It consists of A game board 25 is detachably attached to the front frame 24 from the back side, and a glass door 26 and a front plate 27 are pivotally attached to the front side so as to be freely opened and closed.

  The front plate 27 is provided with an upper plate 28 for storing game balls for launch. A lower plate 29 for storing game balls overflowing from or extracted from the upper plate 28 and a launch handle 30 are disposed below the front frame 24. And are provided. The launch handle 30 is interlocked with the launch motor, and a game ball is launched by a striking rod 31 (see FIG. 15) that operates according to the rotation angle of the launch handle.

  On the right side of the upper plate 28, an operation panel 32 for lending the ball to the card-type ball lending machine 22 is provided, and on this operation panel 32, a card remaining amount display unit 32a for displaying the remaining amount of the card with a three-digit number. A ball lending switch 32b for instructing lending of game balls for a predetermined amount, and a return switch 32c for instructing to return the card at the end of the game. On the upper part of the glass door 26, a big hit LED lamp P1 indicating a big hit state is arranged. In addition, in the vicinity of the big hit LED lamp P1, abnormality notification LED lamps P2 and P3 are provided to indicate a replenishment state or a full state of the lower plate.

  As shown in FIG. 14, the game board 25 is provided with a guide rail 33 formed of a metal outer rail and an inner rail in an annular shape, and the display device 8 (specifically, at the approximate center of the game area 25a on the inner side thereof. In particular, a liquid crystal color display) is arranged. In addition, at a suitable place in the game area 25a, there are arranged a symbol start opening 35, a big winning opening 36, a plurality of normal winning openings 37 (four on the left and right sides of the big winning opening 36), and a gate portion 38 which is two passing openings. It is installed. Each of these winning openings 35 to 38 has a detection switch inside, and can detect the passage of a game ball.

  The display device 8 is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. The display device 8 has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 39 in the upper right portion. The normal symbol display unit 39 displays a normal symbol. When a game ball that has passed through the gate unit 38 is detected, the displayed normal symbol fluctuates for a predetermined time, and when the game ball passes through the gate unit 38. The stop symbol determined by the random number for lottery extracted in is displayed and stopped.

  For example, the symbol start opening 35 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 35a. When the stop symbol after fluctuation of the normal symbol display unit 39 displays a winning symbol, the symbol start port 35 is opened and closed. The claw 35a is opened only for a predetermined time. When a game ball wins the symbol start opening 35, the display symbols of the special symbol display portions Da to Dc change for a predetermined time, and are determined based on the lottery result corresponding to the winning timing of the game ball to the symbol start opening 35. Stop at the stop symbol.

  The big winning opening 36 is controlled to open and close by, for example, an opening / closing plate 36a that can be opened forward, but when the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, “big hit” Is started, and the open / close plate 36a is opened. Inside the big winning opening 36, there is a winning area 36b for detecting a winning ball.

  After the opening / closing plate 36a of the big winning opening 36 is opened, the opening / closing plate 36a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. At this time, the special game is continued up to, for example, 15 times at maximum, and is controlled in a state advantageous to the player. Furthermore, when the stop symbol after the change is a special state occurrence symbol among the special symbols, a special state is generated.

  As shown in FIG. 15, a back mechanism plate 40 that presses the game board 25 from the back side is detachably attached to the back side of the front frame 24. An opening 40a is formed in the back mechanism plate 40, and a prize ball tank 41 and a tank rail 42 extending therefrom are provided on the upper side thereof. A payout device 43 connected to the tank rail 42 is provided on the side of the back mechanism plate 40, and a passage unit 44 connected to the payout device 43 is provided below the back mechanism plate 40. The game balls paid out from the payout device 43 are paid out to the upper plate 28 from the upper plate discharge port 28a (FIG. 12) via the passage unit 44.

  The opening 40a of the back mechanism plate 40 is fitted with a back cover 45 mounted on the back side of the game board 25 and a winning ball discharge basket (not shown) for discharging the game balls won in the winning holes 35 to 37. Has been. The main control board 1 is disposed inside the case CA1 attached to the back cover 45 (see FIG. 15).

  A power supply board 7 and a payout control board 5 are provided inside the case mounted on the back mechanism plate 40. A power switch 53 (denoted as PW in FIG. 11) and an RWM clear switch 54 (denoted as SW in FIG. 2) are disposed on the power supply board 7. The parts corresponding to both the switches 53 and 54 are notched, and both switches can be operated simultaneously with a finger. Inside the case CA5 attached to the rear side of the firing handle 30, a firing control board 6 is provided.

  As mentioned above, although the Example of this invention was described concretely, the description content does not specifically limit this invention. For example, in the embodiment, a ball game machine has been described, but it is applicable not only to a pachinko machine, an arrange ball machine, and a sparrow ball machine, but also to a spinning machine using medals and a spinning machine using game balls. Of course you can.

It is a block diagram which shows the whole structure of the pachinko machine which concerns on embodiment. The connection relationship among a power supply board, a main control board, and a payout control board is illustrated in the first embodiment. In the second embodiment, the connection relationship among the power supply board, the main control board, and the payout control board is illustrated. It is a flowchart which shows the main process of the main control part regarding 1st Embodiment. It is a flowchart which shows the main process of the payout control part regarding 1st Embodiment. It is a flowchart which shows the timer interruption process of a payout control part regarding 1st Embodiment. It is a flowchart which shows the main process of the main control part regarding 2nd Embodiment. It is a flowchart which shows the main process of the payout control part regarding 2nd Embodiment. It is a flowchart which shows a part of timer interruption process of a payout control part regarding 2nd Embodiment. It is a flowchart which shows the main process of the main control part regarding 3rd Embodiment. It is drawing explaining a clear circuit and an initialization switch circuit. It is a perspective view which shows the pachinko machine of embodiment. It is a side view of the pachinko machine of FIG. It is a front view of the game board of the pachinko machine of FIG. It is a rear view of the pachinko machine of FIG.

Explanation of symbols

GM gaming machine 1 main control unit 5 sub control unit CLR clear signal ACK confirmation signal

Claims (10)

A gaming machine that executes a lottery process due to a player's operation or a winning state of a game medium and generates a profit state advantageous to the player based on the lottery result, and includes a game control operation including the lottery process And a sub-control unit that executes an individual game control operation based on a control command received from the main control unit,
Even if the CPU of the main control unit goes into a runaway state, the CPU is left without being forcibly reset, and the stored contents of each memory are erased in the main control unit and the sub control unit. When a switch operation is performed, a clear signal indicating the switch operation is supplied to each,
First means for transmitting a confirmation signal from the sub-control unit to the main control unit only at the start of a steady game control operation after power-on;
A gaming machine comprising: a second means that does not start the next operation of the main control unit unless the main control unit receives the confirmation signal. Flag setting means for setting a determination flag to an ON value after the CPU of the sub-control unit is reset and before a steady game control operation is started;
After a steady game control operation is started by the sub-control unit, the value of the determination flag is determined. If the determination flag value is an ON value, it is changed to an OFF value and the confirmation signal is sent to the main control signal. A transmission means for outputting to the control unit;
Thereafter, monitoring means for continuously monitoring that the determination flag is an OFF value while executing a steady game control operation of the sub-control unit,
The gaming machine according to claim 1, wherein the sub-control unit is provided. Flag setting means for setting a specific bit of output data to an ON value until a steady game control operation is started after the CPU of the sub-control unit is reset;
When a steady game control operation is started in the sub-control unit, after the specific bit is output to the main control unit as a confirmation signal, a transmission unit that sets the specific bit to an OFF value;
The gaming machine according to claim 1, wherein the sub-control unit is provided. A gaming machine that executes a lottery process due to a player's operation or a winning state of a game medium and generates a profit state advantageous to the player based on the lottery result, and includes a game control operation including the lottery process A main control unit that centrally takes charge of and a sub-control unit that executes individual operations based on control commands received from the main control unit,
When a switch operation is performed to erase the stored contents of the memory, a clear signal indicating the switch operation is configured to be supplied to the main control unit, and the clear signal received by the main control unit is Configured to be transferred to the sub-control unit,
After the CPU of the sub-control unit is reset, an ON value or an OFF value is set to the determination flag depending on whether or not the stored contents of the memory are erased before a steady game control operation is started. Flag setting means to perform,
After the routine control operation is started in the sub-control unit, the value of the determination flag is determined, and in the case of an ON value indicating that the stored contents of the memory are erased, this is set to an OFF value. A flag changing means to be changed;
Time consumption means for consuming a predetermined time from power-on while executing a steady game control operation of the sub-control unit when the determination flag is in an OFF value;
Thereafter, a signal monitoring means for monitoring a clear signal transferred from the main control unit while performing a steady game control operation of the sub control unit,
A gaming machine comprising: a sub-control unit provided with a stop unit that stops subsequent operation of the sub-control unit when a clear signal is detected by the signal monitoring unit. A gaming machine that executes a lottery process due to a player's operation or a winning state of a game medium and generates a profit state advantageous to the player based on the lottery result, and includes a game control operation including the lottery process And a sub-control unit that executes an individual game control operation based on a control command received from the main control unit,
An initialization switch that can be turned on prior to turning on the power, a capacitor that is charged regardless of whether the power is turned on when the initialization switch is turned on, and a clear signal after the power is turned on until the capacitor is discharged And a pulse output unit for outputting
In the main control unit and / or the sub control unit,
A gaming machine configured to erase the stored contents of each memory when receiving the clear signal after the power is turned on and before starting a regular game control operation. A gaming machine that executes a lottery process due to a player's operation or a winning state of a game medium and generates a profit state advantageous to the player based on the lottery result, and includes a game control operation including the lottery process And a sub-control unit that executes an individual game control operation based on a control command received from the main control unit,
An initialization switch that can be turned on prior to turning on the power, an operation detection unit that outputs a trigger signal when the initialization switch is turned on when the power is turned on, and the predetermined pulse width received by the trigger signal A pulse output unit for outputting a clear signal,
In the main control unit and / or the sub control unit,
A gaming machine configured to erase the stored contents of each memory when receiving the clear signal after the power is turned on and before starting a regular game control operation.   The operation detection unit includes a gate element that receives a switch signal indicating an ON / OFF state of the initialization switch and a system reset signal for resetting the power of the CPUs of the main control unit and the sub control unit. The gaming machine according to claim 6, wherein the gaming machine is configured as described above.   8. The system according to claim 7, further comprising a delay unit that receives and delays the system reset signal, and another gate element that receives the output of the gate element and the delay unit and outputs the trigger signal. Game machines.   2. The operation of the main control unit and the sub control unit includes a main process that is started after power is turned on and ends with an infinite loop process, and a timer interrupt process that is started at regular intervals. A gaming machine according to claim 8. The gaming machine according to claim 9, wherein the steady game control operation is executed by the timer interrupt process in both the main control unit and the sub-control unit.

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