JP4764442B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine that includes a computer circuit, and more particularly to a gaming machine that can effectively eliminate fraudulent games.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a profit state advantageous to the player. However, in actuality, whether or not the big hit state is determined in advance by the big hit lottery process based on the winning of the game ball, and the symbol display section performs the symbol changing operation exclusively to increase the player.

  In the big hit lottery process, a counter variable CT (big hit counter) that is updated every predetermined time is used, and the value of the big hit counter CT (random number value RND) acquired when winning the symbol at the game start of the game ball is the winning value. It is compared with Hit to determine whether or not it is a big hit state. When the game ball wins, a winning switch signal SG supplied from the symbol starting port to the main control board is turned on.

  The jackpot counter CT is cleared to zero together with other areas of the volatile memory RAM by a RAM clear process if the initialization switch SW is turned on by a staff member when the power is turned on, and then incremented by a predetermined time. Cycle through a predetermined numerical range.

  By the way, the above-mentioned rules for updating the winning value Hit and the big hit counter CT can be found by obtaining a gaming machine and analyzing the control program. Therefore, if it is the first round of the circulation operation of the big hit counter CT immediately after the power is turned on and after the RAM clear process, it is impossible to intentionally generate a winning state by using an illegal board. Absent.

  For example, if the gaming machine (see FIG. 10) is supplied with the system reset signal SYS and the RAM clear signal CLR from the power supply board to the main control board, an unauthorized board (hanging board) is connected to the connector of the main control board. Attach and intentionally supply the system reset signal SYS and the RAM clear signal CLR to the main control board, and then, at the timing when the big hit counter CT coincides with the winning value Hit, the ON level winning switch signal SG May be supplied to the main control board.

Note that Patent Documents 1 and 2 propose that a liquid crystal display notifies that the RAM has been cleared to zero, but that alone is not a sufficient measure.
JP 2003-033532 A Japanese Patent Laid-Open No. 2003-205161

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a gaming machine that can effectively eliminate unauthorized games when the RAM is illegally cleared to zero.

In order to achieve the above object, the present invention determines a lottery result of a lottery process for determining whether or not a game state advantageous to a player is generated in relation to a predetermined game operation, and centralizes the game operation. A main control unit having a computer circuit responsible for it, and a power supply unit that receives an external power supply and supplies necessary voltages to each part of the apparatus, and stores the volatile memory of the computer circuit even after the external power supply is interrupted A gaming machine provided with a backup function for maintaining the contents, wherein the main control unit corresponds to an ON operation of a single initialization switch arranged so that the operation unit is exposed from a case sealing the control circuit board and, not based on an external signal, is configured to generate a clear signal of its own oN level, wherein the main control unit, upon power-up of the computer circuit, whether the initialization switch is turned oN And determining operation determining means clear signal based on whether the ON level, the initialization switch is determined to have been turned ON by the operation determination means, to force the contents stored in the volatile memory of the computer circuit An erasing unit for erasing, and a notification instruction unit for displaying a notification screen by transmitting a control command to a display control unit that controls the display device when the erasing unit functions;
Confirmation means for confirming whether or not the initialization switch has returned to the OFF state based on whether or not the clear signal is at the OFF level, and after confirming the OFF level clear signal by the confirmation means, the initialization switch is turned on. Re-determination means for re-determining whether or not it is in the state based on whether or not the clear signal is ON level, and if the initialization switch determines that the initialization switch is in the ON operation state, the subsequent control operation It is configured to have a transition section to migrate and to.

  Further, the main control unit is further provided with an abnormality detection means for detecting that the computer circuit has been restarted without shutting off the power after the power is turned on, and when the restart of the computer circuit is detected In addition, it is preferable that the content stored in the volatile memory is forcibly erased. Here, “detecting that the computer circuit has been restarted” includes not only a case where the restart is correctly detected, but also a case where there is a possibility that the computer circuit has been restarted. In any case, since an abnormal situation that does not occur originally has occurred, it is possible to prevent the abnormal situation thereafter by deleting the contents of the volatile memory.

  The configuration of the abnormality detection means is not particularly limited. For example, the backup is reset in a volatile memory of a computer circuit to a prescribed value after a predetermined process executed when a power supply that receives a voltage drop signal is interrupted, and reset in a steady operation. When the flag is provided, the abnormality detection unit restarts the computer circuit when the operation determination unit does not detect the ON operation of the initialization switch and the backup flag is not a specified value. It is preferable to determine that it has been done.

  Further, when the volatile memory of the computer circuit is provided with a storage area for storing a calculation result of a predetermined process executed when the power supply receiving the voltage drop signal is shut down, the abnormality detection unit is configured so that the operation determination unit It is preferable to determine that the computer circuit has been restarted when the ON operation of the initialization switch is not detected and the execution result of the same operation as the predetermined processing does not match the value in the storage area. is there. In any of the embodiments, as described above, the determination that there is a possibility of being restarted is also included.

The display control unit should provide a screen that prompts the user to turn on the initialization switch in response to receiving the control command.

  After the transmission process of the control command, it is preferable to execute the time consumption process for a preset random consumption time. In this case, it is possible to disable an illegal game in which the transmission timing of the control command is stolen.

  Further, if the counter value used for the lottery result is set to a random initial value after the erasing means functions, it is practically impossible to play illegal games. The consumption time or the initial value is preferably determined by a numerical value stored in an internal register of the CPU prior to the operation of the erasing means.

  As described above, according to the present invention, it is possible to realize a gaming machine that can effectively eliminate fraudulent games when the RAM is cleared to zero.

  Hereinafter, embodiments of the present invention will be described in detail. FIG. 1 is a front view showing a pachinko machine GM according to the present embodiment. The illustrated pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It consists of A game board 5 is detachably attached to the front frame 3 from the front side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be opened and closed.

  An upper plate 8 for storing game balls for launch is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowing from or extracted from the upper plate 8 and a launch handle 10 are mounted at the bottom of the front frame 3. And are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  An elliptical push button 11 with a built-in lamp is provided at the approximate center of the upper plate 8. The push button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the push button 11 without releasing the right hand from the firing handle 10. This push button 11 does not function normally, but when the game state becomes, for example, a “button chance state”, the built-in lamp is turned on and can be operated.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation for the card-type ball lending machine is provided, a remaining amount display unit 12a for displaying the remaining amount of the card with a three-digit number, and a predetermined amount of game balls A ball lending switch 12b for instructing ball lending and a return switch 12c for instructing the return of the card at the end of the game are provided.

  As shown in FIG. 2, the game board 5 is provided with a guide rail 13 formed of a metal outer rail and an inner rail in an annular shape, and a liquid crystal color display DISP is provided at the approximate center of the game area 5a inside. The lottery result display section 14 by 7 segment LED and the two LED lamps 19 are arranged at the upper part.

  The liquid crystal display DISP is a part that functions as an effect symbol display unit that variably displays an effect symbol (for example, a three-digit effect symbol “7, 7, 7”) directly related to the special symbol related to the big hit state, and a background image And various characters are also displayed in animation. On the other hand, the lottery result display unit 14 functions as a special symbol display unit. After the blinking operation is performed in synchronization with the variation display operation of the liquid crystal display DISP, the lottery processing is performed in accordance with the stop operation of the liquid crystal display DISP. The result of success / failure is displayed deterministically.

  In this embodiment, the big hit state is divided into a probable big hit and a normal big hit, but the liquid crystal display DISP informs whether the probable big hit, normal big hit or lost by the arrangement of the production symbols in the stopped state. On the other hand, the lottery result display unit 14 notifies this by a predetermined stop pattern. Specifically, the liquid crystal display DISP has “7, 7, 7”, “6, 6, 6”, “2, 5, 2”, etc., depending on whether it is probable big hit, normal big hit or lost. In accordance with the stop display of the effect symbol, the lottery result display unit 14 displays stop symbols of “77”, “66”, and “-” when two 7-segment LEDs are provided, for example. The probability variation jackpot means a jackpot state in which a game in which the winning probability of the jackpot is increased (a game in the probability variation state) is started after the special gaming state similar to the case of the normal jackpot is completed.

  On the other hand, the two LED lamps 19 are portions that normally function as symbol display units. When a game ball that has passed through the gate 18 is detected, the display content fluctuates for a predetermined time. The success / failure state determined on the basis of the random number for lottery drawn at the time of passing is displayed. In this embodiment, when both of the two LED lamps are turned on and stopped, a hit state is obtained, and when one or two of the LED lamps are stopped in an unlit state, a lost state is obtained.

  As shown in FIG. 2, a design starting port 15, a big winning port 16, four normal winning ports 17, and a gate 18 that is a left and right passing port are arranged at appropriate positions in the game area 5 a of the game board 5. .

  Each of the winning holes 15 to 17 and the gate 18 has a detection switch inside, so that the passage of the game ball can be detected.

  In the present embodiment, the symbol start opening 15 is enlarged and reduced by an electric tulip having a pair of opening and closing claws, and is opened and closed when a hit display is made in a stopped state after the LED lamp 19 which is a normal symbol display portion changes. The nail is enlarged for a predetermined time. When a game ball wins the symbol start opening 15, the display symbols on the liquid crystal display DISP as the effect symbol display portion and the lottery result display portion 14 as the special symbol display portion change for a predetermined time, and It stops at the stop symbol determined based on the lottery result corresponding to the winning timing of the game ball.

  The big prize opening 16 is opened and closed by an opening / closing plate 16a that can be opened forward, but the symbols after the change stop of the production symbol display portion DISP are arranged such as “6, 6, 6”, “7, 7, 7”, etc. When it is an effect symbol ("66" or "77" is displayed on the lottery result display unit 14), a special game state called "big hit" is started, and the opening / closing plate 16a is opened.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. Such opening and closing operations are controlled to a state advantageous to the player, for example, the special game is continued up to 16 times.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. As shown in the figure, this pachinko machine GM receives AC24V and outputs various DC voltages, a system reset signal SYS, a voltage drop signal ABN, and the like, and a main control board 21 that is centrally responsible for game control operations. And an effect control board 22 that executes a lamp effect and a sound effect based on the control command CMD received from the main control board 21, and a liquid crystal that drives the liquid crystal display DISP based on the control command CMD ′ received from the effect control board 22. The control board 23, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21 and paying out the game ball, and the game ball is fired in response to the player's operation. The launch control board 25 is mainly configured.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26. The control command CMD ′ output from the effect control board 22 is transmitted to the liquid crystal control board 23 via the effect interface board 27.

  The main control board 21, the effect control board 22, the liquid crystal control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer.

  Accordingly, the circuits mounted on the control boards 21 to 24 and the operations realized by the circuits are collectively referred to as a function. In this specification, the main control unit 21, the effect control unit 22, and the liquid crystal control unit 23 are used. , And the payout control unit 24. All or part of the effect control unit 22, the liquid crystal control unit 23, and the payout control unit 24 is a sub-control unit.

  As shown in FIG. 3, the power supply board 20 outputs the system reset signal SYS and the voltage drop signal ABN to the main control unit 21 and the payout control unit 24 together with the backup power supply BU and other DC voltages. Here, the system reset signal SYS is a signal indicating that the AC power supply 24V has been turned on to the power supply board 20, and the one-chip microcomputer and the IC element mounted in each of the control units 21 and 24 by this signal SYS. The power is reset. The system reset signal SYS is similarly supplied to the one-chip microcomputers and IC elements of the other control units 22 and 23.

  The voltage drop signal ABN is a signal indicating that the AC power supply 24V has started to drop. By receiving this voltage drop signal ABN, the main control unit 21 and the payout control unit 24 prior to a power failure or business termination, Necessary termination processing is started. The backup power source BU is a DC 5V DC power source that retains data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power source 24V is cut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 25 can resume the game operation before power-off after power-on (power backup function).

  This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  By the way, in this embodiment, the RAM clear signal CLR is generated in the main control board 21 and is supplied from the main control board 21 to the payout control board 24. Here, the RAM clear signal CLR is a signal for determining whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each of the control units 21 and 24. It has a value corresponding to the OFF state.

  The initialization switch SW is a rebound-type push switch, and is arranged so that only its head is exposed on the main control board 21 arranged strictly sealed on the back of the gaming machine GM (FIG. 4). (See (b)). Thus, in this embodiment, the RAM clear signal CLR is not generated unless the gaming machine is unlocked and the initialization switch SW on the back side is pressed, in other words, the main control board 21 Since the RAM clear signal CLR is not received from the circuit board, it is effective in preventing illegal acts (the reason will be described later).

  The RAM clear signal CLR generated by the main control board 21 is supplied to the payout control board 24 via the output buffer BUF (see FIG. 4A). Therefore, the payout controller 24 can be reset to the initial state as the main controller 21 is reset to the initial state. Therefore, for example, even if the prize ball payout operation is not completed at the end of the previous day's business, the meaningless prize ball payout operation of the next day can be avoided by turning on the initialization switch SW.

  As described above, in this embodiment, although the RAM clear signal CLR is output from the main control board 21, it passes through the output buffer BUF, so that an illegal board is provided to drop the RAM clear signal line to the ground potential. However, the influence cannot be exerted on the main control board 21. On the contrary, if the output buffer BUF is not provided, the L-level RAM clear signal CLR is supplied to the input port IN of the one-chip microcomputer of the main control board 21 only by dropping the RAM clear signal line to the ground potential. .

  Returning to FIG. 3 and supplementing the explanation related to the main control unit 21, the main control unit 21 is connected to each game component of the game board 5 via the game board relay board 29. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven.

  The main control unit 21 is also connected to the symbol display board 33 via the game board relay board 29 and directly drives the LED group to light. This LED group includes a 7-segment LED constituting the lottery result display unit 14 and two LED lamps constituting the normal symbol display unit 19. In addition, the main control unit 21 also directly displays an LED for displaying the number of lottery holds, the number of jackpot rounds, and the like that are in a standby state when a game ball passes through the gate 18 or the symbol start port 15 continuously. The lighting is controlled.

  The main control unit 21 transmits a control command CMD ″ to the payout control unit 25, while the payout control unit 25 receives a prize ball count signal indicating a payout operation of game balls and a status signal related to an abnormality in the payout operation. The status signal CON includes, for example, an out-of-supply signal, an insufficient payout error signal, and a lower plate full signal.

  FIG. 4 shows the relationship among the power supply board 20, the main control board 21, and the payout control board 24 in an organized manner.

  The voltage monitoring unit provided on the power supply board 20 generates a system reset signal SYS when the AC power supply (24 V) is turned on, and generates a voltage drop signal ABN when the AC power supply drops. The system reset signal SYS is supplied to the reset terminals RSET of the one-chip microcomputers of the main control unit 21 and the payout control unit 24, and the power of each CPU core is reset. The CPU core is composed of an equivalent product of Z80CPU (Zilog).

  The voltage drop signal ABN is supplied to an input port IN built in each one-chip microcomputer. Then, each CPU periodically checks the data of the input port IN, so that the control unit 21 and 24 can grasp the power-down state.

  On the other hand, the initialization switch SW is arranged on the main control board 21 in a pull-up state, and the RAM clear signal CLR generated by the ON operation of the initialization switch SW is directly transmitted to the one-chip microcomputer of the main control unit 21. Supplied to the input port IN. The RAM clear signal CLR is output from the main control board 21 to the payout control board 24 via the output buffer BUF, and is also supplied to the input port IN of the one-chip microcomputer of the payout control unit 24. Accordingly, the control units 21 and 24 grasp the RAM clear signal CLR by checking the data of the corresponding input port IN.

  The winning switch signal SG obtained from the symbol start port 15 is supplied to the input port IN of the one-chip microcomputer of the main control unit 21, while the control command output from the output port of the main control unit 21 is an output destination. Is transmitted to the corresponding control unit via the output buffer BUF corresponding to. Note that the shaded portions in FIG. 4 indicate places where illegal boards may be mounted. For example, the system reset signal SYS is disguised, the winning switch signal SG is disguised, and the transmission timing of the control command CMD is stolen. There is concern.

  Subsequently, the operation content of the one-chip microcomputer of the main control unit 2 will be described. The operation of the main control unit 21 is realized by a main process (FIG. 6) that is started when the CPU is reset and a timer interrupt process (FIG. 7) that is started every predetermined time (4 mS) and advances the game operation. Has been.

  First, the main process of the main control unit 21 will be described with reference to FIG. The main process starts when the power is turned on without the initialization switch SW being operated, such as when recovering from a power failure, and when the initialization switch SW is turned on and the power is turned on. There is a case.

  In any case, the Z80 CPU first sets itself to the interrupt disabled state (ST1) and sets to the interrupt mode 2 (ST2). Further, the value of the stack pointer SP in the CPU is initialized to the final address of the stack area (ST3). Next, the internal register values including each part of the one-chip microcomputer are initialized (ST4).

  In this embodiment, in the process of step ST4, among the internal registers of the Z80 CPU, the HL register and the DE register are initialized to random values. Specifically, the contents of a predetermined address (for example, SUM address) in the work area of the built-in RAM are stored in the HL register, and the contents of another address are stored in the DE register.

  Note that the internal register to be used and the random value stored in the internal register are not limited to the above example, and can be changed as appropriate.

  For example, the random value set in the HL register is used as the initial value of the jackpot counter CT (ST13), and the random value set in the DE register, for example, determines the consumption time in step ST14.

  When step ST4 is completed in this manner, the input port is accessed to determine the level of the RAM clear signal CLR generated by the main control board (ST5). Here, when the initialization switch SW is turned on when the power is turned on, since the RAM clear signal CLR is at the ON level, the RAM clear process is executed (ST9). As a result, the entire area of the built-in RAM is cleared to zero, and the value of the big hit counter CT and the value of the backup flag BFL set when the power is turned off become zero together with other checksum values.

  On the other hand, when the initialization switch SW is not operated, including when recovering from the power failure state, the RAM clear signal CLR is at the OFF level. In such a case, the content of the backup flag BFL is determined following the determination in step ST5 (ST6).

  The backup flag BFL is set to 5AH when the power is shut off, and is reset to zero in the first timer interrupt processing after the power is restored.

  Therefore, when the power is turned on or when recovering from the power failure state, the content of the backup flag BFL is 5AH. However, the backup flag BFL = 00H if the predetermined processing is not completed before the power is shut off for some reason.

  Further, even when an illegal system reset signal SYS is supplied by an illegal board during a game operation (see FIG. 4A), after the CPU is reset, an OFF level RAM clear signal CLR is determined. At the timing (ST6), the backup flag BFL = 00H.

  In the case of BFL ≠ 5AH (normally BFL = 00H) including the case of such illegal acts, the process proceeds from step ST6 to step ST9, and the value of the big hit counter CT becomes zero. As the illegal player thinks.

  On the other hand, if the backup flag BFL = 5AH, a checksum operation for calculating a checksum value is executed (ST7). Here, the checksum operation is an 8-bit addition operation for the work area of the built-in RAM. When the checksum value is calculated, the calculation result is compared with the stored value at the SUM address in the RAM (ST8).

  The SUM address stores a checksum value obtained by the same checksum calculation when the power is shut off. The stored calculation results are maintained by a backup power source together with other data in the built-in RAM. Therefore, the two should be matched by the determination in step ST8.

  However, if the checksum calculation cannot be executed when the power is turned off, or if the data in the work area is damaged after the execution of the checksum calculation (ST7) of the main process even if it can be executed In such a case, the determination result in step ST8 is inconsistent. If data corruption is detected due to a discrepancy between the determination results, the process proceeds to step ST9 to execute a RAM clear process, and the operation of the gaming machine is returned to the initial state. On the other hand, if it is determined in step ST8 that the checksum value obtained by the checksum calculation (ST7) matches the stored value at the SUM address, the process proceeds to step ST15.

  By the way, when the RAM clear process (ST9) is executed including the case of illegal action, next, a control command for notifying that the RAM area is cleared to zero is output (ST10). This control command (RAM clear command) is transmitted to the liquid crystal control unit 23 via the effect control unit 22, but in the present embodiment, the liquid crystal control unit 23 that has received the RAM clear command is sent to the liquid crystal display DISP. The “screen for prompting the operator to turn on the initialization switch SW” is displayed.

  In response to this display operation, the main control unit 21 waits for the RAM clear signal CLR to become ON level (ST11). Therefore, unless the clerk turns ON the initialization switch SW, the game is not started, which is effective in preventing illegal games.

  Note that the staff member who has turned on the initialization switch SW when the power is turned on is waiting at the place until the gaming machine is normally started. Therefore, upon receiving the notification in step ST10, it is sufficient to turn on the initialization switch SW again, or to maintain the initialization switch SW that has been turned on first until the timing of step ST11. It seems not to give.

  In any case, if the RAM clear signal CLR becomes ON level, a control command indicating that the RAM clear process (ST9) is normally completed is transmitted to the sub-control units 22 and 23 (ST12). As a result, on the liquid crystal display DISP, a normal initial screen such as a demo screen is displayed instead of the previous display screen.

  Next, the initial value of the big hit counter CT is set to a random value based on the value of the HL register (ST13). As described above, in this embodiment, the data of the SUM address is stored in the HL register by the process of step ST4. When the HL register is used in the processes of steps ST10 to ST12, the value of the HL register may be stored in the RAM work area after the RAM clear process.

  Thus, in the present embodiment, the value of the big hit counter CT is initially set to a random value at the timing of step ST13. Therefore, in the unlikely event that the illegal player unlocks the gaming machine during the game operation, the system reset signal SYS is generated by the illegal board while the initialization switch SW is turned on, or the power switch is turned on. Even if an OFF → ON operation is performed, illegal games cannot be made successful.

  Subsequently, in this embodiment, the time wasting process is executed only for the time determined by the value of the DE register (ST14). Since a random value is stored in the DE register by the process of step ST4, the processing time of step ST14 becomes a random value. When the DE register is used in the processes of steps ST10 to ST12, the value of the DE register is stored in the RAM work area after the RAM clear process.

  In the present embodiment, since the process of step ST14 is provided, an illegal player should be able to specify the initial value of the jackpot counter CT, and the command transmission timing of step ST12 is set to an illegal board (see FIG. Even if it is grasped in 4), it is impossible to aim at the subsequent big hit timing. In this embodiment, since the timer interruption period is 4 mS, it is preferable that the consumption time in the process of step ST14 is a random time of about 1 second that is sufficiently longer than the timer interruption period.

  When the above processing is completed, a CTC (Z80 counter timer circuit) built in the one-chip microcomputer, which outputs a timer interrupt signal, is initialized (ST15). Also, with the CPU set to the interrupt disabled state (ST16), update processing is executed for various counters (ST17), and then the CPU is returned to the interrupt enabled state (ST19) and the process returns to step ST16.

  In the main process described above, one of the process in step ST6 and the processes in steps ST7 and ST8 may be omitted. In addition, the execution order of these processes ST5 to ST8 including the process of step ST5 may be changed as appropriate. Next, a timer interrupt processing program (FIG. 7) started every 4 mS by interrupting the infinite loop processing (ST16 to ST19) will be described. When a timer interrupt occurs, first, a power supply monitoring process is executed (ST31). Since the timer interrupt is started only after execution of step ST19, the value of the internal register of the CPU is not saved in the stack area at the beginning of the timer interrupt process.

  FIG. 8A is a flowchart specifically showing the contents of the power supply monitoring process. First, the voltage drop signal ABN is acquired from the input port of the one-chip microcomputer (ST51), and its level is determined (ST52). If the voltage drop signal ABN is at a normal level, the subroutine processing is finished as it is. On the other hand, if voltage drop signal ABN is at an abnormal level, it is determined that AC power supply AC24V is in a cut-off state. Then, the same checksum calculation as in step ST7 of the main process is executed (ST53). Specifically, 8-bit addition is continuously performed on the work area of the built-in RAM, and the addition result is stored as a checksum value at the SUM address.

  Thereafter, after storing the flag value 5AH at the address BFL (ST54), access to the RAM is prohibited, and the CPU waits for the power supply voltage to drop and the CPU to become inoperative (ST55).

  After that, the CPU becomes inoperative, but the backed up data is maintained as it is because the backup power BU is supplied to the RAM.

  As shown in FIG. 8B, the return address (HHLL) at the end of the timer interrupt and the next address (XXYY) of the subroutine of the power monitoring process are stored in the stack area when the power is shut off. In the initial setting process (ST3) of the stack pointer SP after the insertion, virtually all disappears.

  However, the timer interrupt processing does not save the CPU internal register (it is not necessary to save), so no problem occurs. Also, in this embodiment, after power is turned on, it is always executed first from the power monitoring process. For example, even if the power supply is not stable at the time of power recovery from a power failure, the trouble caused by that Can be prevented. Note that a watchdog timer (not shown) mounted on the main control unit functions even if the power supply voltage is unstable and the power supply is turned on and falls into an infinite loop in step ST55. This resets the CPU.

  The power supply monitoring process (ST31) executed at the head of the timer interrupt process has been described above. Normally, however, since the voltage drop signal ABN is at the H level, the process immediately proceeds to the process of ST31 step ST4 and the random number is changed. Creation processing is executed (ST32). The random number generation processing includes update processing of the winning counter RG and the big hit counter CT used in the lottery operation in the normal symbol processing ST40 and the special symbol processing ST45. Since the initial value of the jackpot counter CT is set to a random value (ST13), the illegal action cannot be made successful.

  When the random number generation process (ST32) ends, a timer subtraction process is performed for the timer that manages the time of each game operation (ST33). The timer to be subtracted here is mainly used for managing the opening time of the electric tulip and the special winning opening and other game effect times. At this time, a clear signal is supplied to the watchdog timer to prevent the CPU from being forcibly reset.

  Subsequently, ON / OFF signals of various switches including a winning detection switch of the symbol start opening 15 and the big winning opening 16 are inputted, and the ON / OFF signals are stored in the work area (ST34). If an unreasonable ON signal is detected, an illegal winning command is transmitted (ST35). The illegal winning command is transmitted, for example, when an ON signal is obtained from the detection switch of the special winning opening 16 even though the special game is not being performed.

  Next, error management processing is performed (ST36). The error management process is a determination as to whether or not an abnormality has occurred inside the device, such as whether or not the supply of game balls has stopped or the game balls are clogged. Next, after creating a control command for the payout control board (ST37), the control command generated in each of the above processes is transmitted to the corresponding sub-control board (ST38).

  Next, normal symbol processing is performed on the condition that the current operation mode is not the hit mode (ST40). The normal symbol processing means determination as to whether or not to operate an ordinary electric accessory such as an electric tulip. Specifically, when it is determined that the game ball has passed the gate based on the switch input result in step ST34, the winning counter RG updated in the random number generation process (ST32) is compared with the winning winning value. Done. If the comparison result is a winning state, the operation mode is changed to the winning operation mode. Further, if it is hit, a process for operating an ordinary electric accessory such as an electric tulip is performed (ST42).

  Subsequently, necessary control commands are transmitted to the corresponding sub control board (ST43), and special symbol processing is performed on the condition that the current operation mode is not a big hit (ST45). The special symbol process is a determination as to whether or not to operate a special electric accessory such as the special prize opening 16.

  Specifically, when it is determined from the switch input result in step ST34 that the game ball has passed the symbol start port, the big hit counter CT updated in the random number generation process (ST32) is used as the big win winning value Hit. In contrast to. Then, if the comparison result is a winning state, the operation mode is changed to the big hit mode. If it is a big hit, a process for operating a special electric accessory such as a big prize opening is performed (ST47).

  Thereafter, the control command generated in each of the above processes is transmitted to the corresponding sub control board, and the interrupt process is completed (ST48). As a result, the process returns from the interrupt process routine to the infinite loop process (ST16 in FIG. 6) of the main process.

  As described above, in the above embodiment, the ball game machine has been described. However, the present invention is not limited to pachinko machines, arrange ball machines, and sparrow ball game machines, but also to revolving game machines using medals and revolving game machines using game balls. Of course, it is also applicable. Further, the circuit configuration and processing contents are not particularly limited to specific description contents.

  For example, the configuration (see FIG. 5) in which the initialization switch SW is arranged on the power supply board 20 and the RAM clear signal CLR generated there is supplied to the main control unit 21 and the payout control unit 24 is not prohibited. However, in this case, it is preferable to transfer the RAM clear signal CLR from the payout control unit 24 to the main control unit 21 separately from the path from the power supply board to the main control unit 21. Hereinafter, for the sake of convenience, the RAM clear signal received from the payout control unit 24 is referred to as a transfer clear signal CLR2 in distinction from the RAM clear signal CLR1 received from the power supply board 20.

  FIG. 9 is a flowchart showing a main process of the main control unit 21 when such a configuration is adopted. In this embodiment, prior to the RAM clear process (ST9), it is determined whether or not the transfer clear signal CLR2 is at the ON level (ST99).

  Next, the same processing (ST9 to ST10) as in FIG. 6 is performed, and it waits for the RAM clear signal to become the OFF level (ST100). If the RAM clear signal becomes the OFF level, the RAM clear signal is again transmitted. Wait until it becomes ON level (ST11). The RAM clear signal determined here may be the original RAM clear signal CLR1 or the transfer clear signal CLR2.

  In any case, after the CPU reset, unless the RAM clear signal changes from ON → OFF → ON → OFF, the process does not proceed to step ST12, which is effective in eliminating illegal games. That is, the clerk only has to release the initialization switch SW that was initially turned on and then turn it on again, but it is troublesome to generate the same signal on the illegal board. Even if the process can pass through step ST11, the processes in steps ST13 and ST14 function effectively, so that illegal gaming is virtually impossible.

  In the circuit configuration of FIG. 5, the crime prevention effect is extremely enhanced by using the transfer clear signal CLR2, and as a result, there is a concern that the gaming machine will not start up regardless of illegal games due to the influence of disconnection or noise. Is done. Therefore, for example, as shown in FIG. 9B, if the ON level transfer clear signal CLR2 cannot be detected in the determination in step ST99, it is also preferable to notify the hall computer and proceed with the process (ST200). ).

  For example, only when the checksum value is abnormal, the abnormal process may be executed to stop the gaming operation (ST204).

  When the checksum value is normal, the flag indicating the big hit state and the state flag indicating the probability change that is advantageous to the player are cleared, and then the normal game operation is performed (ST203). In the third embodiment shown in FIG. 9C, this corresponds to the fact that the RAM clear process is not executed unless the ON level transfer clear signal CLR2 can be detected. This is to eliminate the state and the probability variation state.

It is a front view of the pachinko machine concerning an embodiment. It is a front view of the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. The connection relationship among a power supply board, a main control board, and a payout control board is illustrated. 6 shows another connection relationship among a power supply board, a main control board, and a payout control board. It is a flowchart which shows the main process of a main control part. It is a flowchart which shows the timer interruption process of a main control part. It is a flowchart which shows the power supply monitoring process which is a part of FIG. It is a flowchart which shows another embodiment of the main process of a main control part. It is drawing explaining the problem of a prior art.

Explanation of symbols

GM gaming machine 20 power supply unit 21 main control unit 24 sub control unit CLR clear signal SYS system reset signal ABN voltage drop signal SW initialization switch

Claims (8)

A main control unit having a computer circuit that determines a lottery result of a lottery process as to whether or not to generate a gaming state advantageous to the player in relation to a predetermined game operation, and plays a central role in the game operation; A gaming machine having a backup function for maintaining the stored contents of the volatile memory of the computer circuit even after the external power supply is interrupted. There,
The main control unit clears the ON level itself without being based on an external signal in response to the ON operation of a single initialization switch arranged so that the operation unit is exposed from the case sealing the control circuit board. Configured to generate a signal,
In the main control unit,
An operation determining means for determining whether or not the initialization switch is turned on at the time of power-on of the computer circuit, based on whether or not the clear signal is at the ON level ;
If it is determined by the operation determining means that the initialization switch has been turned ON, the erasing means for forcibly erasing the stored contents of the volatile memory of the computer circuit ;
A notification instructing means for displaying a notification screen by transmitting a control command to a display control unit for controlling the display device when the erasing means functions;
Confirmation means for confirming whether or not the initialization switch has returned to the OFF state based on whether or not the clear signal is at the OFF level;
Re-determination means for re- determining whether or not the initialization switch is in the ON operation state based on whether or not the clear signal is ON level after the confirmation means confirms the OFF level clear signal ;
When it is determined by the re-determination means that the initialization switch is in the ON operation state, transition means for shifting to the subsequent control operation;
A gaming machine characterized by having a structure. The computer circuit of the main control unit is output from the first input unit that receives the primitive clear signal generated in response to the ON operation of the single initialization switch and the other control unit that has received the primitive clear signal. And a second input unit for receiving a transfer clear signal ,
2. The gaming machine according to claim 1, wherein the operation determination unit is configured to determine that the initialization switch has been turned ON when both the primitive clear signal and the transfer clear signal are at the ON level . The gaming machine according to claim 2 , wherein the confirmation unit determines whether or not the clear signal is at an OFF level based on one or both of the primitive clear signal and the transfer clear signal . The gaming machine according to claim 2 or 3 , wherein the re-determination means determines whether or not the clear signal is at an ON level based on one or both of the primitive clear signal and the transfer clear signal . A payout control unit having a sub computer circuit for controlling a payout operation based on a control command received from the main control unit;
A backup function for maintaining the storage contents of the volatile memory of the sub computer circuit even after the external power supply is interrupted,
The gaming machine according to claim 2, wherein a transfer clear signal is configured to be transmitted to the sub computer circuit via a buffer circuit of the main control unit. The gaming machine according to any one of claims 1 to 5, wherein the transition unit is configured to display a notification screen different from the notification screen by transmitting a control command to a display control unit that controls the display device. . A first means for setting a first set value in a first register of the CPU of the computer circuit until the erasing means functions;
The counter value used for the lottery process after the control command is transmitted by the shift means is configured to be set to a random initial value based on the first set value. The gaming machine described. A second means for setting a second set value in a second register of the CPU of the computer circuit until the erasing means functions;
The gaming machine according to any one of claims 1 to 7, wherein after the control command is transmitted by the shift means, the time consumption process is executed for a random consumption time based on the second set value .