JP2001076492A5 - - Google Patents

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Publication number
JP2001076492A5
JP2001076492A5 JP1999248810A JP24881099A JP2001076492A5 JP 2001076492 A5 JP2001076492 A5 JP 2001076492A5 JP 1999248810 A JP1999248810 A JP 1999248810A JP 24881099 A JP24881099 A JP 24881099A JP 2001076492 A5 JP2001076492 A5 JP 2001076492A5
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JP
Japan
Prior art keywords
bit line
capacitance
sub
capacitor
potential
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JP1999248810A
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English (en)
Japanese (ja)
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JP2001076492A (ja
JP4253734B2 (ja
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Priority to JP24881099A priority Critical patent/JP4253734B2/ja
Priority claimed from JP24881099A external-priority patent/JP4253734B2/ja
Priority to US09/597,728 priority patent/US6198654B1/en
Publication of JP2001076492A publication Critical patent/JP2001076492A/ja
Publication of JP2001076492A5 publication Critical patent/JP2001076492A5/ja
Application granted granted Critical
Publication of JP4253734B2 publication Critical patent/JP4253734B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP24881099A 1999-09-02 1999-09-02 強誘電体メモリ装置およびその装置からのデータ読み出し方法 Expired - Fee Related JP4253734B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP24881099A JP4253734B2 (ja) 1999-09-02 1999-09-02 強誘電体メモリ装置およびその装置からのデータ読み出し方法
US09/597,728 US6198654B1 (en) 1999-09-02 2000-06-19 Ferroelectric memory device and method of reading data therefrom

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24881099A JP4253734B2 (ja) 1999-09-02 1999-09-02 強誘電体メモリ装置およびその装置からのデータ読み出し方法

Publications (3)

Publication Number Publication Date
JP2001076492A JP2001076492A (ja) 2001-03-23
JP2001076492A5 true JP2001076492A5 (https=) 2006-04-06
JP4253734B2 JP4253734B2 (ja) 2009-04-15

Family

ID=17183753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24881099A Expired - Fee Related JP4253734B2 (ja) 1999-09-02 1999-09-02 強誘電体メモリ装置およびその装置からのデータ読み出し方法

Country Status (2)

Country Link
US (1) US6198654B1 (https=)
JP (1) JP4253734B2 (https=)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4350222B2 (ja) * 1999-08-26 2009-10-21 Ｏｋｉセミコンダクタ株式会社 強誘電体メモリ装置の動作方法
DE19950581A1 (de) * 1999-10-20 2001-04-26 Infineon Technologies Ag Anordnung zur Selbstreferenzierung von ferroelektrischen Speicherzellen
JP2001297581A (ja) * 2000-04-11 2001-10-26 Fujitsu Ltd データ読み出し方法及び半導体記憶装置
JP4064599B2 (ja) * 2000-04-24 2008-03-19 沖電気工業株式会社 不揮発性半導体スイッチ回路
US6611448B2 (en) * 2001-07-30 2003-08-26 Intel Corporation Ferroelectric memory and method for reading the same
JP3740577B2 (ja) * 2001-12-20 2006-02-01 松下電器産業株式会社 負電位発生回路、負電位発生装置及びこれを用いた半導体装置
US6646904B2 (en) * 2001-12-21 2003-11-11 Intel Corporation Ferroelectric memory and method of reading the same
JP3806084B2 (ja) * 2002-12-25 2006-08-09 株式会社東芝 強誘電体メモリ及びそのデータ読み出し方法
JP2006024263A (ja) * 2004-07-07 2006-01-26 Seiko Epson Corp 強誘電体記憶装置、電子機器
DE102005003461A1 (de) * 2005-01-25 2006-08-03 Infineon Technologies Ag Integrierter Halbleiterspeicher und Verfahren zum Betreiben eines Halbleiterspeichers
CN109643571A (zh) 2016-08-31 2019-04-16 美光科技公司 包含铁电存储器及用于存取铁电存储器的设备及方法
EP3507805B1 (en) 2016-08-31 2025-10-01 Micron Technology, Inc. Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory
KR102314663B1 (ko) 2016-08-31 2021-10-21 마이크론 테크놀로지, 인크. 2 트랜지스터-1 커패시터 메모리를 포함하고 이를 액세스하기 위한 장치 및 방법
SG11201901210UA (en) 2016-08-31 2019-03-28 Micron Technology Inc Ferroelectric memory cells
US10304514B2 (en) * 2017-07-05 2019-05-28 Micron Technology, Inc. Self-reference sensing for memory cells
US10867675B2 (en) 2017-07-13 2020-12-15 Micron Technology, Inc. Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells
WO2025257671A1 (ja) * 2024-06-11 2025-12-18 株式会社半導体エネルギー研究所 半導体装置および半導体装置の駆動方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6097624A (en) * 1997-09-17 2000-08-01 Samsung Electronics Co., Ltd. Methods of operating ferroelectric memory devices having reconfigurable bit lines

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