JP2001068669A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JP2001068669A
JP2001068669A JP24275499A JP24275499A JP2001068669A JP 2001068669 A JP2001068669 A JP 2001068669A JP 24275499 A JP24275499 A JP 24275499A JP 24275499 A JP24275499 A JP 24275499A JP 2001068669 A JP2001068669 A JP 2001068669A
Authority
JP
Japan
Prior art keywords
region
source
forming
semiconductor device
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24275499A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001068669A5 (enExample
Inventor
Yuji Komatsu
裕司 小松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP24275499A priority Critical patent/JP2001068669A/ja
Priority to US09/652,508 priority patent/US6380053B1/en
Publication of JP2001068669A publication Critical patent/JP2001068669A/ja
Publication of JP2001068669A5 publication Critical patent/JP2001068669A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
JP24275499A 1999-08-30 1999-08-30 半導体装置の製造方法 Pending JP2001068669A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP24275499A JP2001068669A (ja) 1999-08-30 1999-08-30 半導体装置の製造方法
US09/652,508 US6380053B1 (en) 1999-08-30 2000-08-31 Method for producing a semiconductor device with an accurately controlled impurity concentration profile in the extension regions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24275499A JP2001068669A (ja) 1999-08-30 1999-08-30 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2001068669A true JP2001068669A (ja) 2001-03-16
JP2001068669A5 JP2001068669A5 (enExample) 2006-04-20

Family

ID=17093779

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24275499A Pending JP2001068669A (ja) 1999-08-30 1999-08-30 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US6380053B1 (enExample)
JP (1) JP2001068669A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002280548A (ja) * 2001-03-21 2002-09-27 Fujitsu Ltd 電界効果型半導体装置の製造方法
JP2004537856A (ja) * 2001-08-01 2004-12-16 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド キセノン（Ｘｅ）による事前非晶質化のためのインプランテーション

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100463953B1 (ko) * 2001-06-25 2004-12-30 주식회사 하이닉스반도체 반도체 소자의 트랜지스터 및 그 제조 방법
JP2003086807A (ja) * 2001-09-10 2003-03-20 Oki Electric Ind Co Ltd 電界効果トランジスタの製造方法
KR100423904B1 (ko) * 2002-03-26 2004-03-22 삼성전자주식회사 모스 트랜지스터에 접속되는 콘택을 가진 반도체 장치의제조방법
JP2004014941A (ja) * 2002-06-10 2004-01-15 Nec Corp 半導体装置、これを用いた回路、および半導体装置の製造方法
CN100590887C (zh) * 2003-01-31 2010-02-17 富士通微电子株式会社 半导体器件的制造方法
CN101777496B (zh) * 2003-01-31 2012-05-30 富士通半导体股份有限公司 nMOS晶体管的制造方法
US7163867B2 (en) * 2003-07-28 2007-01-16 International Business Machines Corporation Method for slowing down dopant-enhanced diffusion in substrates and devices fabricated therefrom
EP1678750A1 (en) * 2003-10-17 2006-07-12 Koninklijke Philips Electronics N.V. Semiconductor device and method of manufacturing such a semiconductor device
TWI241023B (en) * 2004-03-18 2005-10-01 United Microelectronics Corp Method for fabricating semiconductor device
US7638400B2 (en) * 2004-04-07 2009-12-29 United Microelectronics Corp. Method for fabricating semiconductor device
US7157343B2 (en) * 2004-04-07 2007-01-02 United Microelectronics Corp. Method for fabricating semiconductor device
CN100377321C (zh) * 2004-06-28 2008-03-26 中芯国际集成电路制造(上海)有限公司 用于高电压操作的金属氧化物半导体器件及其制造方法
US20060286730A1 (en) * 2005-06-15 2006-12-21 Liu Alex Liu Yi-Cheng Semiconductor structure and method for forming thereof
JP5076557B2 (ja) * 2007-03-06 2012-11-21 富士通セミコンダクター株式会社 半導体装置の製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63308382A (ja) * 1987-06-10 1988-12-15 Fujitsu Ltd Ｌｄｄ構造を有するトランジスタの製造方法
US5895955A (en) * 1997-01-10 1999-04-20 Advanced Micro Devices, Inc. MOS transistor employing a removable, dual layer etch stop to protect implant regions from sidewall spacer overetch
US5989966A (en) * 1997-12-15 1999-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method and a deep sub-micron field effect transistor structure for suppressing short channel effects
US6087234A (en) * 1997-12-19 2000-07-11 Texas Instruments - Acer Incorporated Method of forming a self-aligned silicide MOSFET with an extended ultra-shallow S/D junction
US6121100A (en) * 1997-12-31 2000-09-19 Intel Corporation Method of fabricating a MOS transistor with a raised source/drain extension
US6103563A (en) * 1999-03-17 2000-08-15 Advanced Micro Devices, Inc. Nitride disposable spacer to reduce mask count in CMOS transistor formation
US6171919B1 (en) * 1999-07-27 2001-01-09 Advanced Micro Devices, Inc. MOS Transistor formation process including post-spacer etch surface treatment for improved silicide formation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002280548A (ja) * 2001-03-21 2002-09-27 Fujitsu Ltd 電界効果型半導体装置の製造方法
JP2004537856A (ja) * 2001-08-01 2004-12-16 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド キセノン（Ｘｅ）による事前非晶質化のためのインプランテーション

Also Published As

Publication number Publication date
US6380053B1 (en) 2002-04-30

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