JP2001046710A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure the storage of necessary data in a game machine in which the necessary data is stored in case of a power source interruption to restart a game from the state in the power source interruption when the power source is restored, by performing a data refuge processing when the power source voltage drops by a prescribed quantity, and setting a corresponding flag. SOLUTION: When a power source monitoring IC 902 detects a drop of power source voltage, a CPU 56 is interrupted to transfer the content of each resistor to a backup RAM, and an NMI flag is set. The RAM access is prohibited, and the level of an input port 570 to which the output of the power source monitoring IC 092 is introduced is continuously monitored. When the level of the input port 570 is returned to a general level, an initial reset signal is transmitted from an initial reset circuit 905 to a CPU 56 to start a main processing. When the set of the NMI flag is confirmed, the resistor value stored in the backup RAM is returned to the original resistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine such as a pachinko gaming machine, and more particularly to a game machine in which a game medium is shot by a player's operation and the game medium wins a prize area provided in the game area. A predetermined value is given to the player, and a special game is performed by the entry of the game medium into the specific winning section, and the predetermined game value is given to the player based on the result of the special game being in a predetermined mode. The present invention relates to a gaming machine that can be provided.

[0002]

2. Description of the Related Art As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of prize balls are obtained. Are paid out to players.
Furthermore, a variable display unit capable of changing the display state is provided,
There is a configuration in which a predetermined game value is provided to a player when a display result of the variable display unit has a predetermined specific display mode.

[0003] When the display result of the variable display section for displaying a special symbol is a combination of a predetermined specific display mode, it is usually called a "big hit". In addition, the game value is a right to make the state of the variable prize ball device provided in the game area of the gaming machine advantageous for a player who is easy to win a hit ball, or a right for the player to be in an advantageous state. Or to generate.

[0004] When a big hit occurs, for example, a big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state in which a hit ball is easy to win. Then, in each open period, when a predetermined number (for example, 10) of winning prizes is won, the winning prize opening is closed. The number of opening of the special winning opening is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. If the predetermined condition (for example, winning in the V zone provided in the special winning opening) is not satisfied at the time when the special winning opening is closed, the big hit gaming state ends.

[0005] In addition, among the combinations of display modes other than the "big hit" combination, at a stage where some of the display results of the plurality of variable display portions have not been derived and displayed yet, the display results have already been derived and displayed. The state in which the display mode of the variable display unit that satisfies the display condition that is a combination of the specific display modes is called “reach”. If the display result of the identification information variably displayed on the variable display unit does not satisfy the condition of “reach”, the result is “out” and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

The progress of the game in the gaming machine is controlled by game control means such as a microcomputer. The identification information, the character image, and the background image displayed on the variable display device are controlled by display control means operating according to display control command data from the game control means.
The identification information, the character image, and the background image displayed on the variable display device generally include a display control microcomputer and a video display processor (FIG. 1) that generates image data in accordance with instructions from the microcomputer and transfers the image data to the variable display device side. VDP), and the display control microcomputer has a large program capacity.

Therefore, the microcomputer of the game control means, which has a limited program capacity, cannot control the identification information and the like displayed on the variable display device, and is different from the microcomputer of the game control means for display control. A microcomputer (display control means) is used. Therefore, the game control means for controlling the progress of the game needs to transmit a command for display control to the display control means.

[0008] Further, a player generally borrows a game medium through a game machine. In that case, a gaming medium lending mechanism is provided in the gaming machine. The game media lending mechanism is often shared with a payout mechanism for paying out prize balls. Since the game media lending mechanism and the prize ball payout mechanism are both common or separately provided, they both perform an operation of paying out game media. It is controlled by prize ball control means mounted on the substrate.

Since the progress of the game is controlled by the game control means mounted on the main board, the number of prize balls based on the winning is determined by the game control means and transmitted to the prize ball control board. On the other hand, since the lending of the game medium is not related to the progress of the game, it is generally controlled by the prize ball control means without passing through the game control means.

[0010]

As described above, the gaming machine is equipped with various control means in addition to the game control means. Generally, each control means is constituted by a microcomputer. That is, a program is stored in a ROM or the like, and data that temporarily occurs in control or data that changes as the control progresses is stored in the RAM. Then, when a power-off state occurs due to a power failure or the like in the gaming machine, data in the RAM is lost. Therefore, at the time of recovery from a power failure or the like, the player must return to the initial state (for example, a state in which the power of the gaming machine is first turned on at the game store for the first time), which may cause disadvantage to the player. There is.
For example, if a power failure occurs during a jackpot game and the gaming machine returns to the initial state, the player will not be able to enjoy the benefits based on the occurrence of the jackpot.

In order to avoid such a situation, necessary data is stored in a power supply backup RAM when an unexpected power failure such as a power failure occurs, and data stored when power is restored is restored. And then resume the game. However, if the way of saving and the way of restoring necessary data when the power is turned off are improper, the restored data may not match the data when the power is turned off. In such a case, unexpected disadvantages may still be given to the player.

[0012] Therefore, the present invention is required when a game is configured so that necessary data can be saved when an unexpected power failure such as a power failure occurs and the game can be resumed from the power-off state when the power is restored. It is an object of the present invention to provide a gaming machine capable of surely storing important data and reliably utilizing the stored data after the power is restored.

[0013]

A gaming machine according to the present invention comprises:
Performing a predetermined game, a gaming machine controllable to a gaming state advantageous to the player according to the progress of the game, comprising a gaming device control board for controlling a gaming device provided for the game, The gaming machine control board is equipped with a gaming machine control microcomputer, and at least a part of the volatile storage means in the gaming machine control board can be backed up by a backup power supply even when the power of the gaming machine is turned off. It is possible to retain the game state memory required to restore the game state when the power of the machine is restored,
The gaming machine control microcomputer introduces a signal indicating that the power supply voltage of the gaming machine has decreased by a predetermined amount to the non-maskable interrupt terminal, and performs data saving processing in response to the signal being input to the non-maskable interrupt terminal. And a flag indicating that the data saving process has been performed is set. If the flag is set at the time of return, the data recovery process is performed. If the flag is not set, the initial setting process (in response to the reset to the microcomputer, (A RAM clear process or the like that is normally executed).

The data restoration process includes at least a process of resetting a flag indicating that the data saving process has been performed,
The game state may be configured to include a game state storage readout process for restoring the game state.

[0015] The gaming machine control microcomputer comprises:
In the case of a game control microcomputer in the game control means for controlling the progress of the game, the game state storage may be configured to include a processing address by a stack pointer.

The game state storage in the game control means may be configured to include at least the contents stored in a register.

[0017] The gaming machine control microcomputer comprises:
In the case of the game control microcomputer in the game control means for controlling the progress of the game, the game state storage may be configured to include at least a flag for selectively performing a process according to the game state. Good.

A gaming machine control microcomputer is
In the case of the prize ball control microcomputer in the prize ball control means for performing the prize ball payout control according to the prize, at least the memory relating to the remaining number of prize balls is backed up so that it can be stored even if the power supply to the gaming machine is cut off. It is preferred that

The game state storage in the winning ball control means may include a processing address by a stack pointer.

The gaming machine control microcomputer comprises:
A signal indicating that the power supply voltage of the gaming machine has dropped by a predetermined amount is also introduced into the input port, and when the signal returns to a level indicating a normal state, a flag indicating that data saving processing has been performed is reset. May be. The input port may be a built-in port of the microcomputer or an external port.

The gaming machine has a power supply board which is provided separately from the gaming machine control board and generates each voltage used in the gaming machine control board. The power board is a power supply of the RAM in the gaming machine control board. A configuration including a backup power supply for performing backup may be employed.

[0022]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of the pachinko gaming machine 1 as viewed from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the pachinko gaming machine 1 as viewed from the back. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine. Further, the present invention can be applied to an image-type gaming machine or a slot machine.

As shown in FIG. 1, the pachinko gaming machine 1
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing prize balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, a variable display section 9 for variably displaying a plurality of types of symbols and a 7-segment L
A variable display device 8 including a variable display 10 using an ED is provided. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In a passage between the passage gate 11 and the ball outlet 13, there is a gate switch 12 for detecting a hit ball that has passed through the passage gate 11. In addition, the winning ball that entered the starting winning port 14 is
It is guided to the back of the game board 6 and is detected by the starting port switch 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16.

Below the variable winning ball device 15, there is provided an opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state). In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. The winning ball that enters one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V count switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. Variable display device 8
A start winning prize storage display 18 having four display sections for displaying the number of winning balls entering the starting winning prize port 14 is provided below. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The game board 6 is provided with a plurality of winning ports 19 and 24. Decorative lamps 25 are provided around the left and right sides of the game area 7 so as to blink during the game.
There is an out port 26 for absorbing a hit ball that does not win. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. A game effect LED 28a and a game effect lamp 2
8b and 28c are provided.

In this example, one of the speakers 27
Is provided with a prize ball lamp 51 which is lit when a prize ball is paid out, and a ball out lamp 52 which is lit when a supply ball is out is provided near the other speaker 27. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming table 1 and enables lending of balls by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card can be used. If there is a fraction (less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter, the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passage gate 11, the display number of the variable display 10 is changed continuously. Further, when a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17, the symbol in the variable display section 9 starts rotating if the symbol can be changed. If it is not possible to start changing the symbol, the start winning memory is increased by one.

The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the specific winning area while the opening and closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols accompanied by a probability change, the probability of the next big hit increases. That is, a high probability state, which is more advantageous for the player, is obtained. Also, when the stop symbol on the variable display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the variable display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. On the back of the variable display device 8, as shown in FIG. 2, a prize ball tank 38 is provided above the mechanism plate 36, and when the pachinko gaming machine 1 is installed on the gaming machine installation island, a prize ball is provided from above. Premium ball tank 3
8 is supplied. The prize ball in the prize ball tank 38 reaches the ball payout device through the guide gutter 39.

On the mechanism board 36, a variable display control unit 29 for controlling the variable display section 9 via the relay board 30, and a game control board (main board) covered with a board case 32 and mounted with a game control microcomputer and the like. ) 31, a relay board 33 for relaying a signal between the variable display control unit 29 and the game control board 31, and a prize ball control board on which a prize ball control microcomputer for controlling the payout of prize balls is mounted. 37 are installed. Further, a ball is hit on the lower part of the mechanism plate 36 by using the rotating force of the motor in the game area 7.
Ball launching device 34 that launches on a game effect lamp / LE
D28a, 28b, 28c, a prize ball lamp 51 and a lamp control board 35 for sending signals to the ball out lamp 52 are provided.

FIG. 3 is a rear view of the gaming board of the pachinko gaming machine 1 as viewed from the rear. The ball that passed through the induction gutter 39
As shown in FIG. 3, the ball cut detectors 187a, 187
b, and reaches the ball dispensing device 97 via the ball supply gutters 186a and 186b. The prize ball paid out from the ball payout device 97 is supplied to the hit ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the communication port 45. On the side of the communication port 45, an excess ball passage 46 communicating with the excess ball tray 4 provided on the front of the pachinko gaming machine 1 is formed. A large number of prize balls based on the prize are paid out, and the ball supply tray 3 becomes full. Finally, after the prize balls reach the communication port 45, further prize balls are paid out. It is led to the ball tray 4. When the prize ball is further paid out, the sensing lever 47 is set to the full switch 4.
By pressing 8, the full tank switch 48 is turned on. In this state, the rotation of the stepping motor in the ball discharging device 97 stops, the operation of the ball discharging device 97 stops, and the driving of the hitting ball firing device 34 also stops as necessary.

Signals from a winning ball detection switch (not shown), a starting port switch 17 and a V count switch 22 are sent to the main board 31 in order to control the winning ball payout. The winning is detected by the winning ball detection switch. When the ON signal of the winning ball detection switch is sent to the main board 31, a winning ball control command is sent from the main board 31 to the winning ball control board 37. For example, when the winning ball detection switch is turned on in response to the turning on of the starting port switch 17, a winning ball control command indicating the number of winning balls “6” is output, and in response to the turning on of the count switch 23 or the V count switch 22, When the winning ball detection switch is turned on, the number of winning balls is “1”.
A prize ball control command indicating "5" is output. When the winning ball detection switch is turned on when these switches are not turned on, a winning ball control command indicating the number of winning balls "10" is output.

FIG. 4 is a block diagram showing an example of a circuit configuration of the main board 31. FIG. 4 also shows the prize ball control board 37, the lamp control board 35, the sound control board 70, the emission control board 91, and the display control board 80. On the main board 31, a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 12,
A switch circuit 58 that supplies signals from the starting port switch 17, the V count switch 22, the count switch 23, and the winning ball detection switch 99 to the basic circuit 53, a solenoid 16 that opens and closes the variable winning ball device 15, and the opening and closing plate 2.
A solenoid circuit 59 for driving the solenoid 21 for opening and closing the 0 according to a command from the basic circuit 53;
It includes a lamp / LED circuit 60 for driving the variable display 10 by ED and the decorative lamp 25.

According to the data supplied from the basic circuit 53, jackpot information indicating the occurrence of a jackpot, effective start information indicating the number of start winning balls used to start displaying an image on the variable display section 9, and probability fluctuation have occurred. And an information output circuit 64 that outputs probability change information or the like indicating the fact to a host computer such as a hall management computer.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 used as a work memory, a CPU 56 for performing a control operation according to the control program, and an I / O port unit 57. In this embodiment, the ROM 54 and the RAM 55 are
6 is built in. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to include at least the RAM 55, and the ROM 54 and the I / O port unit 57 may be externally provided.

Further, the main board 31 has an initial reset circuit 65 for resetting the basic circuit 53 when the power is turned on.
And an address decode circuit 67 that decodes an address signal provided from the basic circuit 53 and outputs a signal for selecting one of the I / O ports in the I / O port unit 57. Although there is switch information input from the ball dispensing device 97 to the main board 31, FIG.
Then they are omitted.

A hit ball firing device that hits and fires a game ball is driven by a drive motor 94 controlled by a circuit on a firing control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

FIG. 5 shows the circuit configuration in the display control board 80 by using the CRT 82 as an example of the variable display section 9 and the output ports (ports A and B) 571 and 572 of the main board 31.
FIG. 9 is a block diagram shown together with an output buffer circuit 63. The output port 571 outputs 8-bit data, and the output port 572 outputs a 1-bit strobe signal (INT signal).

The display control CPU 101 controls the control data R
It operates according to the program stored in the OM 102, and receives a display control command via the input buffer circuit 105 when a strobe signal is input from the main board 31 via the noise filter 107 and the input buffer circuit 105. As the input buffer circuit 105, for example, a general-purpose IC
74HC244 can be used. In addition,
When the display control CPU 101 does not include an I / O port, the input buffer circuit 105 and the display control CP
An I / O port is provided between U101.

The display control CPU 101 controls display of a screen displayed on the CRT 82 in accordance with the received display control command. Specifically, a command corresponding to the display control command is given to the VDP 103. VDP103
Reads necessary data from the character ROM 86. The VDP 103 generates a CRT 8 according to the input data.
2 is generated, and the image data is stored in the VRAM 87. Then, the image data in the VRAM 87 is converted into R, G, B signals, converted into analog signals by the DA converter 104, and output to the CRT 82.

FIG. 5 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, an animal, or an image composed of characters, graphics, or symbols displayed on the CRT 82. In this embodiment, the display control C
PU 101 is a one-chip microcomputer,
At least a RAM is built-in.

The input buffer circuit 105 can pass signals only in the direction from the main board 31 to the display control board 80. Therefore, there is no room for a signal to be transmitted from the display control board 80 side to the main board 31 side. Display control board 80
Even if the internal circuits are modified illegally, the signal output by the illegal modification is not transmitted to the main board 31 side. The outputs of the output ports 571 and 572 may be output to the display control board 80 as they are. However, by providing the output buffer circuit 63 capable of transmitting a signal in only one direction, the output from the main board 31 to the display control board 80 is provided. One-way signal transmission can be further ensured. Further, for example, a three-terminal capacitor or a ferrite bead is used as the noise filter 107 that cuts off a high-frequency signal. However, even if noise is present between display control commands between substrates due to the presence of the noise filter 107, the effect is eliminated. Is done.

FIG. 6 is a block diagram showing components related to the prize ball, such as the components of the prize ball control board 37 and the ball payout device 97. As shown in FIG. 6, the detection signals from the winning ball detection switch 99 and the full tank switch 48 are:
The signal is input to the I / O port 57 of the main board 31 via the relay board 71. The prize ball discharge solenoid 127 drives a ball stop member provided in the middle of the prize ball flow path on the back of the game board. The prize ball detection switch is provided when the prize ball is stopped on the ball stop member. A winning ball is detected by 99. In addition, the full tank switch 48 is used to
Is a switch that detects when the tank is full.

The detection signals from the ball-out detection switch 167 and the ball-out switch 187 (187a, 187b) are transmitted to the main board 3 via the relay boards 72 and 71.
1 is input to the I / O port 57. The out-of-ball detection switch 167 is a switch for detecting a shortage of replenishment balls in the prize ball tank 38, and the out-of-ball switch 187 is a switch for detecting the presence or absence of a prize ball in the prize ball passage.

The CPU 56 of the main board 31 indicates that the detection signal from the out-of-ball detection switch 167 or the out-of-ball switch 187 indicates the out-of-ball state, or the detection signal from the full switch 48 indicates the full state. If it is, a prize ball control command for instructing ball lending is sent. When receiving the award ball control command instructing the ball lending prohibition, the award ball control CPU 371 of the award ball control board 37 stops the ball lending process.

Further, the detection signal from the prize ball count switch 301A is also input to the I / O port 57 of the main board 31 via the relay board 72 and the relay board 71. A drive signal from the I / O port 57 of the main board 31 to the winning ball discharging solenoid 127 is supplied to the winning ball discharging solenoid 127 via the relay board 71. The prize ball count switch 301A is provided in the prize ball mechanism portion of the ball payout device 97, and detects an actually paid prize ball.

When a prize is won, the output ports (ports G, H) 577, 578 of the main board 31 are provided on the prize ball control board 37.
, A prize ball control command indicating the number of prize balls is input. The output port 577 outputs 8-bit data, and the output port 578 outputs a 1-bit strobe signal (INT signal). The award ball control command indicating the number of award balls is input to the I / O port 372a via the input buffer circuit 373. The CPU 371 for controlling the prize ball includes an I / O port 37.
A prize ball control command is input via 2a, and the ball payout device 97 is driven according to the prize ball control command to perform a prize ball payout. In this embodiment, the CPU 37 for controlling the prize ball
Reference numeral 1 denotes a one-chip microcomputer having at least a RAM.

Each buffer in the input buffer circuit 373 can pass a signal only in the direction from the main board 31 to the prize ball control board 37. Therefore, there is no room for a signal to be transmitted from the award ball control board 37 side to the main board 31 side. Even if the circuit in the prize ball control board 37 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuit 373.

On the main board 31, a buffer circuit 68 is provided outside the output ports 577 and 578 for outputting award ball control commands. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be given from the prize ball control board 37 to the main board 31 is more reliably formed. Can be eliminated.

The prize ball controlling CPU 371 outputs a ball lending number signal indicating the number of lending balls to the terminal board 160 and a buzzer driving signal to the buzzer board 75 via the output port 372g. A buzzer is mounted on the buzzer board 75. Further, an error signal is output to the error display LED 374 via the output port 372e.

Further, the input port 3 of the prize ball control board 37
The detection signal of the prize ball count switch 301A and the detection signal of the ball lending count switch 301B are input to 72b via the relay board 72. The ball lending count switch 301B detects a game ball actually lent. The drive signal from the prize ball control board 37 to the payout motor 289 is output from the payout motor 2 in the prize ball mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72.
It is told to 89.

The card unit 50 has a microcomputer for controlling the card unit. Also,
The card unit 50 is provided with a fraction display switch 152, a connection board direction indicator 153, a card insertion indicator lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected to a frequency display LED, a ball lending switch, and a return switch provided near the hit ball supply tray 3.

From the balance display board 74 to the card unit 50
In response to the player's operation, a ball lending switch signal and a return switch signal are provided via the prize ball control board 37. In addition, the balance display board 74 is provided from the card unit 50.
, A card balance display signal indicating the balance of the prepaid card and a ball lending possible display signal are given via the prize ball control board 37. Between the card unit 50 and the prize ball control board 37, a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal)
A pachinko machine operation signal (PRDY signal) is exchanged via the I / O port 372f.

When the power of the pachinko gaming machine 1 is turned on,
The prize ball control CPU 371 of the prize ball control board 37 outputs a PRDY signal to the card unit 50. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the microcomputer for controlling the card unit outputs a BRDY signal to the prize ball control board 37. When a predetermined delay time elapses from this point, the microcomputer for controlling the card unit outputs a BRQ signal to the prize ball control board 37. The CPU 37 for controlling the prize ball on the prize ball control board 37
1 drives the payout motor 289 and pays out a predetermined number of lending balls to the player. Then, when the payout is completed, the prize ball controlling CPU 371 outputs an EXS signal to the card unit 50.

As described above, all signals from the card unit 50 are input to the prize ball control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input from 0 to the main board 31, and there is no room for a signal to be incorrectly input from the card unit 50 side to the basic circuit 53 of the main board 31. Although the main board 31 and the prize ball control board 37 are provided with a solenoid and a driver circuit for driving a motor and a lamp, these circuits are omitted in FIG.

In this embodiment, at least the main substrate 3
A part of the RAM included in the CPU 56 and the CPU 371 for controlling the prize ball is backed up by a backup power supply. In other words, even if the power supply to the gaming machine is stopped, the backup RAM can retain the stored contents by the backup power supply. And each CPU:
When a drop in the power supply voltage is detected, a predetermined process is performed, and then the power supply wait state is restored.

FIG. 7 is a block diagram showing an example of a configuration around the CPU 56 for power supply monitoring and power supply backup. As shown in FIG. 7, the power supply monitoring IC 902
The occurrence of power interruption is detected by introducing a 30V voltage and monitoring the + 30V voltage. Specifically, when the voltage of +30 V becomes equal to or lower than a predetermined value (for example, 80% of +30 V), it is determined that the power is cut off and an interrupt signal is given to the CPU 56. In the CPU 56, this interrupt is input to a non-maskable interrupt (NMI) terminal. Also, N
The signal input to the MI terminal is also input to the input port 570. Therefore, the CPU 56 can confirm the power-off state by confirming the level of the input port in the NMI process. The input port is input to a vacant bit of the input port for inputting output signals of various switches provided in the gaming machine.

The predetermined value for the power supply monitoring IC 902 to detect the power-off is lower than the normal voltage.
Is a voltage that can operate for a while. Further, since the power supply monitoring IC 902 is configured to monitor a voltage higher than the voltage required by the CPU 56 (+5 V in this example) and immediately after conversion from AC to DC, the CPU 56 is required. It is possible to extend the monitoring range with respect to the voltage. Therefore, more precise monitoring can be performed. Further, when +30 V is used as the monitoring voltage, the voltage supplied to various switches of the gaming machine is +1.
Since it is 2 V, prevention of erroneous switch-on detection at the moment of a power interruption can be expected. That is, by monitoring the voltage of the +30 V power supply, it is possible to detect a decrease in the voltage of +12 V generated after the generation of +30 V before the voltage starts to drop. Therefore, when the voltage of the + 12V power supply decreases, the switch output comes to the on state. However, if the + 30V power supply voltage that drops faster than + 12V is monitored and the power cutoff is recognized, the power supply is turned on before the switch output turns on. It is possible to enter a state of waiting for restoration and to enter a state where the switch output is not detected.

While no power is supplied from the + 5V power supply, at least a part of the RAM is backed up by a backup power supply supplied from a power supply board, and its contents are preserved even when the power to the gaming machine is cut off. And +
When the 5V power is restored, a reset signal is issued from the initial reset circuit 65, and the CPU 56 returns to the normal operation state. At that time, since the necessary data is backed up, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovering from a power failure or the like.

FIG. 8 is a block diagram showing a configuration example of the power supply board 910. The power supply board 910 includes the main board 31, the display control board 80, the audio control board 70, and the lamp control board 3.
5 and installed independently of the control board such as the prize ball control board 37, and generates a voltage used by each control board and mechanical components in the gaming machine. In this example, AC24V, DC + 30
V, + 21V DC, + 12V DC and + 5V DC. Also, a capacitor 91 serving as a backup power supply
6 is charged from DC + 5V, that is, a power supply line for driving ICs and the like on each substrate.

The transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
The C converter 913 has + 21V, + 12V and + 5V.
V is generated and output to the connector 915. Connector 91
Reference numeral 5 is connected to, for example, a relay board, from which power of a voltage required for each control board and mechanical components is supplied.

+5 V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 serves as a backup power supply for the backup RAM of each control board when the power supply to the gaming machine is cut off. Also, a diode 91 for preventing backflow is provided between the + 5V line and the backup + 5V line.
7 is inserted.

Note that a battery that can be charged from a +5 V power supply may be used as a backup power supply. In the case of using a battery, a rechargeable battery is used which runs out of capacity when power is not supplied from a + 5V power supply for a predetermined time.

Next, the operation of the gaming machine will be described. FIG.
Is a flowchart showing a game control process of the CPU 56 on the main board 31. FIG. 9A shows a main process executed by the CPU 56, and FIG. 9B shows an interrupt process. When the power-on reset is released, the CPU 56
First, in order to make the clock monitor control operable, the built-in clock monitor register is set to the clock monitor enable state (step S1). The clock monitor control is a control for automatically generating a reset inside the CPU 56 when detecting a drop or stop of an input clock signal. Next, the CPU 56
Performs an initialization process (step S2). In the initialization process, a timer setting process is performed so that the timer is interrupted after a predetermined period (for example, after 2 ms). Thereafter, the process of updating the display random number such as the random number for determining the type of the stop symbol is repeatedly executed (step S17).

The processing shown in FIG.
Triggered by an internal timer interrupt. In the interrupt processing, the CPU 56 firstly sets a predetermined period (for example, 2 ms).
After that, a timer setting process is performed so that the timer is again interrupted (step S20).

Next, after performing processing for setting a display control command sent to the display control board 80 in a predetermined area of the RAM 55 (display control data setting processing: step S
4) A process for outputting a display control command is performed (display control data output process: step S5).

Next, a process of outputting the contents of the storage area for various output data to each output port is performed (data output process: step S6). Further, an output data setting process for setting output data such as jackpot information, start information, and probability variation information output to the hall management computer in the storage area is performed (step S8). Further, various abnormality diagnosis processes are performed by a self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S9).

Next, a process of updating each counter indicating a random number for determination such as a random number for big hit determination used in game control is performed (step S10).

Next, the CPU 56 performs a special symbol process (step S11). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Further, a normal symbol process is performed (step S12). In normal symbol processing, 7 segments L
A corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 by the ED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

The CPU 56 further includes a switch circuit 58
, The state of the gate sensor 12, the starting port sensor 17, and the count sensor 23 are input, and it is determined whether or not there is a prize for each prize port or prize device (switch processing: step S13). The CPU 56 further performs a process of updating a display random number such as a random number for determining the type of stop symbol (step S15).

The CPU 56 performs signal processing between the CPU 56 and the award ball control board 37 (step S16). That is,
When a predetermined condition is satisfied, a prize ball control command is output to the prize ball control board 37. The prize ball control CPU mounted on the prize ball control board 37 drives the ball payout device 97 according to the prize ball control command.

FIG. 10 is a flowchart showing the NMI interrupt processing of the CPU 56. As described above, when the power supply monitoring IC 902 detects a drop in the power supply voltage, the CPU 5
6 receives an NMI interrupt. Further, as shown in FIG. 7, the output of the power supply monitoring IC 902 is introduced to the input port.

In the NMI interrupt process based on the power supply voltage drop, the CPU 56 first transfers the contents of the register to the backup RAM (step S31). Then N
The MI flag is set (step S32). The NMI flag is an internal flag indicating that an interrupt has occurred due to a drop in power supply voltage. The NMI flag is set in the backup RAM area. The CPU 56 further disables the RAM access (step S3).
3) Continue to monitor the level of the input port to which the output of the power monitoring IC 902 is introduced (step S34).
In this state, the power supply voltage further decreases, and finally,
The operation of the CPU 56 stops.

However, when the level of the input port has returned to the normal level, the CPU 56 enables the RAM access (step S35), and stores the register value stored in the backup RAM into the original register. It is returned (step S36). Then, the NMI flag is reset (step S37), and the address returns to the address where the NMI interrupt was interrupted.

As described above, upon detecting that the power supply voltage has returned to normal, the CPU 56 restores the state of the register and returns to the address at which the NMI interrupt has occurred. Therefore, control can be returned to a normal state even when noise or the like is present on the NMI line.

FIG. 11 is a flowchart showing an example of the initialization process (step S2) in the main process shown in FIG. When the power supply to the gaming machine is restarted, an initial reset signal is input from the initial reset circuit 65 to the CPU 56. The CPU 56 starts the main process in response to the initial reset signal. In the system check process, first, it is checked whether or not the power is turned on (step S41). From the viewpoint of the CPU 56, the time when the power supply to the gaming machine is restarted after the unexpected power-off is also when the power is turned on.

Whether or not the power is turned on is determined by, for example, whether or not the contents of the RAM which has not been backed up are destroyed. In other words, if the content of the RAM that has not been backed up is destroyed, it can be determined that the power is turned on. At this time, if it is necessary to set the RAM access permission state, that is, if the RAM access permission state is not automatically set when the reset is performed, the CPU 56 sets the RAM access permission state.

When the power is turned on, the CPU 56
It is determined whether or not the I flag has been set (step S42). If not set, register and R
All the AM areas are cleared (step S46), and necessary initial values are set (step S47). Then, a power-on screen display command transmission request is set (step S4).
8), the stack pointer is initialized (step S4)
9), end the initialization processing.

When the power-on screen display command transmission request is set, the power-on screen display command is transmitted to the display control board 80 by, for example, the display control data output process (step S5) shown in FIG. Is done. When the display control CPU 101 of the display control board 80 receives the power-on screen display command, the display control CPU 101
Next, a screen that is determined in advance as a screen displayed when the power is turned on is displayed.

When it is confirmed at step S42 that the NMI flag is set, the CPU 56 restores the register value stored in the backup RAM to the original register (step S43). Then, the NMI flag is reset (step S44), and an error screen display command transmission request is set (step S45).

When an error screen display command transmission request is set, an error screen display command is transmitted to the display control board 80 by, for example, display control data output processing (step S5). Upon receiving the power-on screen display command, the display control CPU 101 of the display control board 80 displays a predetermined error screen on the variable display unit 9.

Then, the CPU 56 jumps to the value of the stack area indicated by the stack pointer as a jump destination. Since the stack pointer is one of the registers, the stack pointer has been restored to the value at the time of power-off by the processing in step S43. Also, in this embodiment,
The stack area is formed in the backup RAM area. That is, it is preserved even when the power is turned off. Therefore, the control state returns to the state when the power was turned off.

For example, it is assumed that the display control CPU 101 of the display control board 80 is performing symbol variation display on the variable display section 9 when the power is turned off. Then, when the power is restored, the display control CPU 101 receives the error screen display command, and displays an error screen on the variable display unit 9. On the other hand, the CPU 56 of the main board 31 returns to the state when the power is turned off, that is, the gaming state in which the special symbol is changing. Then, when the gaming state in which the special symbol is changed ends, a command indicating a symbol stop or a command indicating a big hit display is transmitted. At this stage, the display control CPU 101 can stop the error display and continue the subsequent display control.

As described above, the CPU 56 sets N
If the MI flag has been set, data recovery processing is performed, and if the NMI flag has not been set, normal initialization processing (steps S46 and S47) is performed. And
In the data restoration processing, the restoration processing of the saved register and the reset processing of the NMI flag are performed. Also,
Since the return to the return address stored in the stack area in the RAM area where the power is backed up is returned, the game control means can return to the game state when the power is turned off.

FIG. 12 is an explanatory diagram showing a configuration example of a display control command. As shown in FIG. 12, the display control command is composed of 8-bit data and a 1-bit strobe signal (INT signal).

FIG. 13 is an explanatory diagram showing a configuration example of display control command data using 8-bit data. FIG.
As shown in (1), for example, the higher 4 bits of the 8 bits indicate the type of control, and the lower 4 bits indicate the specific control content. For example, in this example, if the upper 4 bits are [0, 0, 0, 1], the reach type, stop of all symbols, and the like are indicated by the numerical values of the lower 4 bits. If the upper four bits are [1,0,0,0], [1,0,0,1] or [1,0,1,0], the variable display unit 9 displays the numerical values of the lower four bits. A stop symbol of the left symbol, the middle symbol or the right symbol which is variably displayed is instructed.

The upper 4 bits are [1,1,0,1].
If it is, it indicates that the command is an error screen display request command. If the upper 4 bits are [1,1,1,1], it indicates that the command is a power-on screen display request command. In these commands, the lower 4 bits are set to, for example, 0.

FIG. 14 is a flow chart showing an example of a special symbol processing program executed by the CPU 56. The special symbol process process shown in FIG. 14 is a specific process of step S11 in the flowchart of FIG. When performing the special symbol process processing, the CPU 56 performs any one of steps S300 to S309 shown in FIG. 14 according to the value of the special symbol process flag. In each process, the following processes are performed.

Special symbol change waiting process (step S30)
0): The start winning port 14 (in this embodiment, the winning port of the variable winning ball device 15) is hit and the start port sensor 17 is turned on. When the starting port sensor 17 is turned on, the starting winning memory number is increased by + if the starting winning memory number is not full.
1 and a big hit determination random number is extracted.

Special symbol determination processing (step S301):
When the state in which the variable display of the special symbol can be started, the number of start winning prize stored is confirmed. If the starting prize memory number is not 0,
It is determined whether to be a big hit or an out-of-big hit according to the value of the extracted big hit determination random number. Stop symbol setting process (step S302): A stop symbol for the left and right middle symbols is determined.

Reach operation setting processing (step S30)
3): Whether or not the reach operation is performed is determined according to the value of the reach determination random number, and the variation mode of the reach operation is determined according to the value of the reach random number.

All symbols change start process (step S30)
4): In the variable display section 9, control is performed so that all symbols start to change. At this time, with respect to the display control board 80,
The left and right middle final stop symbols and information instructing the variation mode are transmitted. When a background or a character is also displayed on the variable display unit 9, control is performed so that display control command data corresponding to the background or character is transmitted to the display control board 80.

All symbols stop waiting processing (step S30)
5): Control is performed so that all symbols displayed on the variable display section 9 are stopped after a predetermined time has elapsed. Also, control is performed so that the left and right symbols are stopped at a predetermined timing until the timing of stopping all symbols.

Big hit display processing (step S306): If the stop symbol is a combination of big hit symbols, control is performed so that the big hit display control command data is sent to the display control board 80, and the internal state (process flag) ) Is updated so as to shift to step S307. Otherwise, the internal state is changed to step S309.
Update to move to. The combination of the big hit symbols is a combination in which the right and left middle symbols are aligned. Also,
The display control CPU 101 of the game control board 80 displays a big hit on the variable display unit 9 according to the display control command data. The jackpot display is made to notify the player of the occurrence of the jackpot.

Big winning opening opening process (step S30)
7): Control for opening the special winning opening is started. Specifically, the counter and the flag are initialized, and the solenoid 21 is driven to open the special winning opening.

Processing during opening of the special winning opening (step S30)
8): Control for transmitting display control command data of the special winning opening round display to the display control board 80, processing for confirming establishment of the closing condition of the special winning opening, and the like are performed. If the closing condition of the special winning opening is satisfied, the internal state is updated to shift to step S307 unless the end condition of the big hit gaming state is satisfied. If the jackpot gaming state end condition is satisfied, the internal state is updated to shift to step S309.

Big hit end processing (step S309):
A display for notifying the player that the jackpot gaming state has ended is performed. When the display is completed, the internal flags and the like are returned to the initial state, and the internal state is updated so as to shift to step S300.

The module (step S5 in FIG. 9) which performs the processing of transmitting the display control command in the game control program according to the processing of each of the above steps outputs the corresponding display control command data to the output port and Turn on the strobe signal.

In the above embodiment, when the power is turned off, the CPU
The register 56 saves the contents of each register in the backup RAM. However, if a predetermined return control is performed when the power is restored, such a register save control may not be performed. FIGS. 15 and 16 are flowcharts showing control in a mode in which the contents of each register are not stored in the backup RAM when the power is turned off.

FIG. 15 is a flowchart showing the NMI interrupt processing. In this case, the CPU 56 first sets N
The MI flag is set (step S32). Also, R
The AM access is prohibited (step S33), and the level of the input port to which the output of the power monitoring IC 902 is introduced is continuously monitored (step S34).

When the level of the input port has returned to the normal level, the CPU 56 enables the RAM access (step S35), resets the NMI flag (step S37), and interrupts the NMI. Return to address.

FIG. 16 is a flowchart showing the initialization processing in the main processing. In this case, the CPU 5
6 first checks whether or not the power is turned on (step S4).
1). If the power is turned on, the CPU 56 checks whether or not the NMI flag is set (step S4).
2). Register and RAM if not set
The entire area is cleared (step S46), and necessary initial values are set (step S47). Then, a power-on screen display command transmission request is set (step S4).
8), the stack pointer is initialized (step S4)
9), end the initialization processing.

In this embodiment, a special symbol process flag is formed in the backup RAM area. When it is confirmed in step S42 that the NMI flag is set, the CPU 56 reads the value of the backed-up special symbol process flag, and from the value at that time (indicating the gaming state), the gaming state at that time. Is restored (step S50). Then, the NMI flag is reset (step S44), and the value of the stack area pointed to by the stack pointer is jumped to the jump area. In this embodiment, the value of each general-purpose register is set to the value of the backup R when the power is turned off.
It does not need to be stored in the AM, but the stack pointer needs to be stored. In addition, it is preferable that the normal symbol process flag used in the variation control of the normal symbol variably displayed on the variable display 10 is also formed in the backup RAM area.

As described above, in this example, the special symbol process flag which is a flag for selectively performing a process according to the game state is stored even when the power to the gaming machine is turned off.
In the data restoration process, the game state is restored according to the value of the special symbol process flag stored.

For example, it is assumed that the display control CPU 101 of the display control board 80 is performing symbol variation display on the variable display section 9 when the power is turned off. Then, when the power is restored, the CPU 56 can return to the game state at the time of starting the symbol change, which was performed when the power was turned off, according to the value of the special symbol process flag. At this stage, the display control command for starting the symbol change is sent to the display control board 80, so that the display control CPU 101 executes the symbol change again from the state at the start of the symbol change. .

FIG. 17 shows the main board 31 to the prize ball control board 3.
FIG. 7 is an explanatory diagram showing a bit configuration of a prize ball control command transmitted to No. 7; As shown in FIG.
The bits are used as a control designation section, and the lower 4 bits are used as an area indicating the number of award balls.

As shown in FIG. 18, if bits 7, 6, 5, and 4 are "0, 1, 0, 0" in the control designation section, it indicates that the command is a payout number designation command. ,
"0, 1" indicates a payout designation command.
The payout number designation command is sent to the prize ball control board 37 immediately after the CPU 56 of the main board 31 detects a winning.

Bits 7, 6, 5, and 4 are "1, 0, 0,
The command “0” is sent from the main board 31 when the cutout detection switch 167 or the cutout switch 187 is turned on (when the cutout state flag is turned on). Also, bits 7, 6, 5, and 4 are "1, 0,
The firing stop designation command of “0, 1”
Is transmitted from the main board 31 when is full and the full switch 48 is turned on (when the full state flag is turned on).

The award ball control command is output from the main board 31 to the award ball control board 37 as 1-byte (8 bits: award ball control commands D7 to D0) data. The winning ball control commands D7 to D0 are output in positive logic. When the award ball control commands D7 to D0 are output, a negative logic award ball control INT signal is output.

As shown in FIG. 6, the award ball control command is transmitted through the output port 577. In this embodiment, as shown in FIG. 19, when the prize ball control commands D7 to D0 are output from the main board 31, the prize ball control INT signal becomes low level for 5 μs or more. The award ball control INT signal is connected to an interrupt terminal of the award ball control CPU 371 on the award ball control board 37. Therefore, when there is an interrupt, the award ball control CPU 371 can recognize that the award ball control commands D7 to D0 have been transmitted from the main board 31, and perform the award ball control command receiving process in the interrupt process.

Note that the command configuration shown in FIG. 17 is an example, and another configuration may be used. For example, the upper and lower bits in one byte may be reversed from the configuration shown in FIG. In this embodiment, all the prize ball control commands sent from the main board 31 to the prize ball control board 37 are:
The data is transferred by the same eight signal lines (D7 to D0). Therefore, the number of wires does not increase even if the number of commands increases. And
As shown in FIG. 17, one display control command includes a data part indicating the number of winning balls and a control designating part. Therefore, the CPU 371 for controlling the prize ball of the prize ball control board 37 can recognize immediately what kind of control command has been received upon receiving the command.

FIG. 20 is a block diagram showing an example of a configuration around the CPU 371 for controlling the prize ball for monitoring and backing up the power supply. As shown in FIG. 20, the power supply monitoring IC 932 detects the occurrence of power interruption by introducing a +30 V voltage and monitoring the +30 V voltage. Specifically, the voltage of +30 V is a predetermined value (for example, 80 of +30 V).
%), It is determined that the power is cut off, and an interrupt signal is given to the CPU 371 for controlling the prize ball. C for prize ball control
In the PU 371, this interrupt is input to a non-maskable interrupt (NMI) terminal. The signal input to the NMI terminal is also input to the input port. Therefore, in the NMI processing, the CPU 371 for controlling the prize ball can confirm the power-off state by confirming the level of the input port.

The predetermined value for the power supply monitoring IC 932 to detect the power-off is lower than the normal voltage, but is a voltage at which the prize ball control CPU 371 can operate for a while.
The power supply monitoring IC 932 is connected to the CPU 37 for controlling the prize ball.
1 is configured to monitor a voltage higher than the required voltage (+5 V in this example).
The monitoring range can be extended for the voltage required by the PU 371. Therefore, more precise monitoring can be performed.

While no power is supplied from the + 5V power supply, at least a part of the built-in RAM of the prize ball control CPU 371 is backed up by connecting the backup power supply supplied from the power supply board to the backup terminal, and the gaming machine The contents are preserved even if the power supply to is turned off. Then, when the +5 V power supply is restored, a reset signal is issued from the initial reset circuit 935, so that the award ball control CPU 371 returns to the normal operation state. At that time, since the necessary data is backed up, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovering from a power failure or the like.

FIG. 21 is a flowchart showing the main processing of the award ball control CPU 371. In the main processing,
The winning ball control CPU 371 first performs an initial value setting process such as clearing the RAM area (step S701).
If data is set in the RAM area (backup area) of the internal RAM that has been backed up by power, those areas are not cleared. afterwards,
In this embodiment, the prize ball control CPU 371 performs prize ball payout control by an interrupt process by a timer interrupt generated every predetermined period (for example, 2 ms) (step S702). In the timer interrupt processing, as shown in FIG.
The PU 371 executes a prize ball payout control process (Step S711).

FIG. 23 is an explanatory diagram showing counters formed in the backup RAM of the prize ball control board 37. As shown in FIG. 23, 1 counter to 15 counters are prepared. Each number counter is provided on the main board 31.
Corresponds to each payout number instruction command indicating the payout number received from the CPU 56, that is, the game control means. For example, when a payout number instruction command instructing the payout of 15 prize balls is received, the value of the 15 counter is incremented by one. Also,
In this embodiment, only the six counters, the ten counters and the fifteen counters are used. However, if counters corresponding to other kinds of numbers are prepared in this way, the number of prize balls corresponding to the prize can be increased. The prize ball control means can be easily diverted to other different games.

It is not necessary that all the work areas used by the prize ball control CPU 371 are backed up by a power supply. It is sufficient that at least each counter shown in FIG. 23 and an address for saving data of flags or registers described later are formed in the backup RAM area.

FIGS. 24 to 30 show the CPU 37 for controlling the prize ball.
It is a flowchart which shows the prize ball payout control processing which 1 performs. In this embodiment, the award ball payout control process is configured to be executed by a timer interrupt process.
Instead of such a configuration, it may be configured to be executed by a normal process (not an interrupt process).

In the award ball payout control process, the award ball control C
The PU 371 checks whether or not a prize ball control command has been received (Step S480). If received
It moves to step S511. If not,
It is confirmed whether or not an error state is currently occurring (step S4).
81). If an error occurs, error processing is performed. If there is no error, the ball is awarded (or the compensation is being paid out)
Is determined (step S482). If the ball is not being awarded, it is checked whether or not a ball lending process is being performed (step S483). If the ball is being lent, the process proceeds to the process of lending a ball.

If no balls are being lent, it is checked whether the values of all the counters are 0 (step S48).
4). If all are 0, that is, if it is not necessary to pay out the prize balls, it is checked whether or not the BRQ signal which is a ball lending request signal from the card unit 50 as an external device of the gaming machine is turned on ( Step S491).

Here, the number of prize balls is stored in the number counter provided for the prize balls in response to the prize ball instruction notified from the game control means. However, one counter is prepared. The number of prize balls notified from the game control means may be added to the counter.

If the BRQ signal is on, a process for starting ball lending is performed (step S492), and the process shifts to a ball lending process. Preferably, a counter for ball lending control is also formed in the backup RAM area.

If it is determined in step S484 that all the number counters have not become zero, the processing in step S500 is performed.

In step S500, if the corrected payout flag is ON, that is, if it is determined that the corrected payout is to be performed, the process proceeds to step S507. If the corrected payout flag is not on, the CPU 371 for controlling the winning ball controls all the number counters (15 in this example).
The counter values of the individual counter to one counter are checked in ascending order (step S50).
1). Then, the number corresponding to the number counter whose value is not 0 is set in the payout number counter (step S50).
3). Further, the award ball processing flag is turned on (step S
503), and turns on the payout motor 289 (step S5).
07). Then, the processing shifts to a prize ball payout processing.

If a prize ball control command (payout number instruction command) is received, the process of step S511 is started. In step S511, the prize ball control CP
U371 increments the value of the number counter corresponding to the number indicated by the number-of-payouts instruction command by +1 (step S51).
2).

As described above, the prize ball control CPU 371 mounted on the prize ball control board 37 is
The number of award balls included in the payout number instruction command sent from 6 is stored in the backup RAM area.

Although there are other award ball control commands other than the payout number instruction command, FIG. 26 omits the processing for receiving these commands.

As described above, in the prize ball control processing, if the payout number instruction command is received from the game control means in the processing after step S511, the corresponding number counter is incremented by +1. Then, at the time of starting the next prize ball control processing, this is detected in step S484, and step S50 is performed.
In the processing after 0, a predetermined value is set in the number-of-payouts counter, and the prize ball processing is being performed. Then, at the time of starting the prize ball control process next time, it is detected that the prize ball process is being performed, and the process of paying out the prize ball after step S532 is executed.

As shown in FIG. 24, here,
Although the payout instruction with the largest number of winning balls is prioritized regardless of the order in which the commands are received, processing may be performed in the order with the smallest number of winning balls. Also, the corresponding prize ball processing may be started in the order in which the commands are received. If the payout process is performed in the descending order of the number of award balls, the game balls are quickly replenished to the player, so that the player does not need to borrow balls unnecessarily.
That is, it is possible to provide a game environment that is advantageous for the player.

The process after step S532 is a process during payout of award balls. In the processing during the prize ball payout, first, a state check is performed (step S532). The prize ball control CPU 371 checks whether the prize ball payout is normally performed by monitoring the payout motor position sensor and the prize ball count switch 301A. The state check is a process of determining whether the payout motor position sensor is currently monitored for ON or the payout motor position sensor is monitored for OFF.

In this embodiment, the following timer is used for monitoring the payout motor position sensor and the prize ball count switch 301A. (1) Timer T11: For monitoring the payout motor position sensor on (2) Timer T12: For monitoring the payoff motor position sensor off (3) Timer T13: For monitoring on the award ball count switch 301A (4) Timer T14: Award For monitoring off of ball count switch 301A

After the number of payouts is confirmed by the payout motor position sensor, the prize ball count switch 301A
There is a delay time required for several game balls to flow down until the actual payout ball is detected, and the following timer is used to wait for that time. (5) Timer T15: Waiting for the time from when the last payout ball is confirmed by the payout motor position sensor to when the ball passes through the prize ball count switch 301A.

Here, a state check is performed by confirming that these timers are operating. In step S532, when the timer T11 is in operation, the wait motor position sensor is turned on (step S53).
534), and when the timer T12 is operating, the wait motor position sensor is turned off (step S
542). When the timer 15 is operating, the timer 15 waits for a timeout (step S57).
Go to 3). When none of the timers is operating, the timer T11 is started (step S53).
3).

In step S534, the prize ball control C
The PU 371 waits for the payout motor position sensor to turn on. If the timer T11 times out before turning on, the process proceeds to error processing (steps S535 and S536).
When the payout motor position sensor is turned on, the timer T11 is stopped (step S537), and the timer T12 is started (step S541). After that, the CPU 37 for controlling the prize ball
1 waits for the delivery motor position sensor to be turned off (step S542). If the timer T12 times out before turning off, the processing shifts to error processing (step S543,
S545). Note that while the timers T11 and T12 have not timed out, the winning ball count switch check subroutine is executed (step S547).

When the payout motor position sensor is turned off, the timer T12 is stopped (step S546), and the payout number counter is decremented by one (step S551). Then, the prize ball controlling CPU 371 checks whether or not the value of the number-of-payouts counter has become 0 (step S552). Being zero means that payout control has been performed for a predetermined number. Therefore, the correction is not being paid out (step S55).
3), a number counter (1
The value of one of the five counters to one counter) is decremented by one (step S554). Further, the dispensing motor 289 is stopped (step S571), and the timer T15
Is started (step S572).

Thereafter, the process waits for the timeout of the timer T15 (step S573). While not timed out,
An award ball count switch check subroutine is executed (step S574).

When the timer T15 times out, if the corrected payout is not being performed (step S574), the number of the current prize ball payout is compared with the value of the prize ball counter (step S574).
575).

The prize ball counter is incremented each time the prize ball count switch 301A located below the payout motor position sensor is turned on once in the prize ball count switch check subroutine. When the ball payout is performed normally when the timer T15 times out, the value of the prize ball number counter matches the number of times the payout motor position sensor is turned on. For example, when 15 prize balls are being played, the number of times the payout motor position sensor is turned on is 1
When it becomes 5, the value of the number-of-payouts counter becomes 0 in step S552, and after that, when the time of T15 elapses, the value of the number-of-prize-ball counter should become 15.

If the determination results in step S575 do not match, the prize ball shortage number (planned prize ball number−prize ball number counter value)
Is set in the payout number counter (step S583), the payout motor 289 is turned on (step S584), and the corrected payout flag is turned on (step S585). It should be noted that the prize ball shortage number is stored as the scheduled correction number.

If the corrected payout has been performed, it is checked whether or not the value of the prize ball number counter matches the expected number of corrections (step S581). If not, the flow proceeds to step S586. If they match, the corrected payout flag is reset (step S582), and the process ends.

If the judgment results in step S575 are coincident, it is checked whether all the number counters are 0 (step S586), and if they are 0, the award ball processing flag is reset. (Step S587), the processing of this time is ended.

As described above, the CPU 371 for controlling the prize ball.
Recognizes, based on the value of the payout number counter, whether or not a predetermined number of winning balls have been completed, and when completed, decrements the value of the corresponding number counter by one. Then, after a lapse of a predetermined time, the number of detections by the prize ball count switch 301A is confirmed, and when it is detected that the number of game balls passing through the prize ball count switch 301A is less than the expected number of payouts, a correction payout process is started. .

Since each number counter and the number-of-payout counter are formed in the backup RAM area,
It is saved even if the power is cut off due to a power failure or the like. Further, a flag indicating that a prize ball is being formed is also formed in the backup RAM area. Therefore, at the time of recovery from a power failure, etc.,
371 can continue the prize ball payout control based on the stored data. That is, upon recovery from the power failure, the CPU 371 for controlling the prize ball can immediately resume the prize ball payout process by detecting that the flag indicating that the prize ball is being set is set.

Further, a correction number counter and the like are also formed in the backup RAM area. Further, a flag indicating that the correction is being paid out is also formed in the backup RAM area. Therefore, even if a power failure or the like occurs during the corrected payout process, the prize ball control CPU 371 can continue the corrected payout control based on the stored data when the power is restored from the power failure or the like.

Even if the flags are not set in the backup RAM area, if the number counter is set in the backup RAM area, the CPU 37 for controlling the prize ball.
1 can detect whether or not there is an unpaid prize ball by checking the set value of each number counter when the power is restored. When it is detected that there is an unpaid prize ball, for example, the prize ball payout process can be restarted by setting the prize ball paying flag.

FIG. 30 is a flowchart showing the award ball count switch check subroutine. In the prize ball count switch check, first, a state check is performed (step S511). In step S511, when the timer T13 is operating, the on-wait processing of the winning ball count switch 301A (step S51)
When the process proceeds to 3) and the timer T14 is operating,
The process proceeds to an off wait process for the award ball count switch 301A (step S518). When none of the timers is operating, the timer T13 is started (step S512).

Then, it waits until the award ball count switch 301A is turned on (step S513). If the timer T13 times out before the output of the winning ball count switch 301A is turned on, the process shifts to error processing (step S).
514, S515).

When the output of the award ball count switch 301A is turned on, the timer T13 is stopped (step S13).
516), and start the timer T14 (step S51).
7). Then, it waits for the award ball count switch 301A to be turned off (step S518). If the timer T14 times out before the award ball count switch 301A is turned off, the process shifts to error processing (steps S519, S5).
20). If the prize ball count switch 301A is turned off before the timer T14 times out, the timer T1
4 is stopped (step S521). Then, the value of the award ball number counter is incremented by 1 (step S522).

In this embodiment, the number of prize balls is stored in the number counter provided for the prize ball in response to the prize ball instruction notified from the game control means. Alternatively, the number of prize balls notified from the game control means may be added to the counter. In such a configuration, the number of counters can be reduced and the RAM area to be backed up can be reduced.

In this embodiment, the payout motor 2
If the payout motor position sensor does not turn on or off within a predetermined time while driving the 89,
An error is determined. This is because if the payout motor position sensor does not turn on or does not turn off, there may be a case where clogging occurs.

If the output of the payout motor position sensor is normal but the prize ball count switch provided below the sensor is not turned on,
Since there is a possibility of the failure of the prize ball counting switch 301A or the like, it is also determined to be an error. If the prize ball count switch 301A is not turned off, it is possible that a ball is jammed in the ball guide path near the prize ball count switch 301A, and so it is also determined to be an error.

FIG. 31 is a flow chart showing the NMI interrupt processing executed by the CPU 371 for controlling a prize ball. In this case, the award ball control CPU 371 first sets the NMI flag (step S801). Also, RAM
The access is prohibited (step S802), and the level of the input port to which the output of the power monitoring IC 932 is introduced is continuously monitored (step S803).

When the level of the input port has returned to the normal level, the power supply monitoring IC 932 sets the RAM access to a permitted state (step S804), resets the NMI flag (step S805), and sets the NMI interrupt. Returns to the address where

As described above, the CPU 371 for controlling the prize ball
When it is detected that the power supply voltage has returned to normal, the state of the register is returned to the original state, and the address returns to the address where the NMI interrupt was interrupted. Therefore, control can be returned to a normal state even when noise or the like is present on the NMI line.

FIG. 32 is a flowchart showing the initialization processing in the main processing executed by the CPU 371 for controlling a prize ball. In this case, the award ball control CPU 37 first checks whether or not the power is on (step S811).
Whether the power is turned on or not is determined, for example, based on whether or not the contents of the RAM that has not been backed up are destroyed. In other words, if the content of the RAM that has not been backed up is destroyed, it can be determined that the power is turned on. At this time, if it is necessary to set the RAM access permission state, that is, if the RAM access permission state is not automatically set when the reset is performed, the prize ball control CPU 371 sets the RAM access permission state. I do.

When the power is turned on, the CPU 3 for controlling the prize ball
7 checks whether the NMI flag is set (step S812). If not set, the register and the RAM area are all cleared (step S81).
4), necessary initial values are set (step S815).
Then, the stack pointer is initialized (step S8).
16) End the initialization process.

When it is confirmed in step S812 that the NMI flag has been set, the CPU 56 sets the NMI flag.
The flag is reset (step S813), and a jump is made to the value of the stack area pointed to by the stack pointer as a jump destination. In this embodiment, it is not necessary to save the value of each general-purpose register in the backup RAM when the power is turned off, but the stack pointer needs to be saved. Since the stack area is formed in the backup RAM area, the CPU 371 for controlling the prize ball controls
By detecting that the NMI flag is set when the power is turned on, it is possible to reliably return to the control state when the power is turned off.

For example, if the award ball flag is set to backup RA
If it is formed in the M area, it is detected that a flag indicating that a prize ball is being set is set, and the CPU 371 for controlling the prize ball.
Can immediately restart the prize ball payout process based on the value of each number counter stored in the backup RAM area.

Even if the flags are not set in the backup RAM area, the number counter is set to the backup RAM area.
If the area is set, the CPU 371 for controlling the prize ball
When the power is restored, the game state memory is read out,
That is, by reading the set value of each number counter, it is possible to detect whether or not there are unpaid prize balls. And
When it is detected that there is an unpaid prize ball, for example, the prize ball payout process can be restarted by setting the prize ball paying flag.

FIG. 33 is a flowchart showing another example of the NMI interrupt processing executed by the award ball control CPU 371. In this case, the CPU 371 for controlling the prize ball first
It is checked whether the number of unpaid prize balls or the number of unpaid ball lending is stored (step S821). If there is such a storage, the NMI flag is set (step S8).
22). In addition, the RAM access is prohibited (step S823), and the level of the input port to which the output of the power monitoring IC 932 is introduced is continuously monitored (step S803).

When the level of the input port returns to the normal level, the power supply monitoring IC 932 sets the RAM access to a permitted state (step S804), resets the NMI flag (step S805), and sets the NMI interrupt. Returns to the address where

If there is no storage of the number of unpaid prize balls or the number of unpaid ball lending, the RAM access is prohibited (step S823), and the flow shifts to step S803.
According to such control, the preparation for the return of the control state when the power is restored is performed only when the power is cut off in the unpaid state, that is, only when necessary.

[0166]

As described above, according to the present invention, a gaming machine, a gaming machine control microcomputer, introduces a signal indicating that a power supply voltage of the gaming machine has decreased by a predetermined amount to a non-maskable interrupt terminal. Then, in response to the signal being input to the non-maskable interrupt terminal, the data saving process is performed, and a flag indicating that the data saving process was performed is set. If the flag is set at the time of the return, the data restoring process is performed. Because it is configured to perform the data saving process, it is possible to determine whether to perform the data restoration process according to the ON / OFF of the flag indicating that the data evacuation process has been performed, and to reliably use the stored data after the power is restored. There is an effect that can be.

In the case where the data restoring process is configured to include a process of resetting a flag indicating that the data saving process has been performed and a process of reading a game state storage for restoring the game state, In addition, the control state can be reliably returned to the state at the time of power-off by the processing of reading out the game state memory, so that no disadvantage is given to the player.

When the game state storage in the game control means for controlling the progress of the game is configured to include the processing address by the stack pointer, it is possible to accurately return to the state at the time of power restoration when the power is restored. it can.

Also, even when the game state storage in the game control means is configured to include at least the contents of the register storage, it is possible to accurately return to the power-off state when the power is restored.

When the game state storage in the game control means is configured to include a flag for selectively performing a process in accordance with the game state, the game state can be divided based on the flag. Can be resumed from.

If the storage related to the remaining number of prize balls in the game state memory in the prize ball control means is backed up so that it can be saved even when the power supply to the gaming machine is cut off, there is no unpaid prize ball when the power is cut off. Even when the power is restored, the award ball payout can be continued based on the stored contents.

If the game state storage in the award ball control means is configured to include the processing address by the stack pointer, it is possible to accurately return to the state at the time of power supply restoration when the power is restored.

The microcomputer for controlling the gaming machine is
A signal indicating that the power supply voltage of the gaming machine has dropped by a predetermined amount is also introduced into the input port, and when the signal returns to a level indicating a normal state, a flag indicating that data saving processing has been performed is reset. In this case, when the power supply voltage returns to normal even if the power supply voltage temporarily drops, the register state can be returned to the original state and the interrupted address can be returned.

When the power supply board is provided with a backup power supply for backing up the power supply of the RAM in the gaming machine control board, it is not necessary to provide a backup power supply for each gaming machine control board, and the cost of the gaming machine is reduced. After reducing the power, the game state can be returned to the state at the time of power-off at the time of restoration from the power-off, and effects such as eliminating disadvantages to the player can be obtained.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is a front view of the gaming board of the pachinko gaming machine as viewed from the front.

FIG. 3 is a rear view of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a block diagram showing a circuit configuration example of a game control board (main board).

FIG. 5 is a block diagram illustrating a circuit configuration example of a display control board.

FIG. 6 is a block diagram illustrating a circuit configuration example of a winning ball control board.

FIG. 7: C for power supply monitoring and power supply backup
FIG. 3 is a block diagram illustrating a configuration example around a PU.

FIG. 8 is a block diagram illustrating a configuration example of a power supply board.

FIG. 9 is a flowchart showing the operation of the basic circuit on the main board.

FIG. 10 is a flowchart showing NMI interrupt processing of a CPU.

FIG. 11 is a flowchart illustrating an example of an initialization process.

FIG. 12 is an explanatory diagram illustrating a configuration example of a display control command.

FIG. 13 is an explanatory diagram showing a configuration example of display control command data.

FIG. 14 is a flowchart showing an example of a special symbol processing program.

FIG. 15 is a flowchart showing another example of the NMI interrupt processing of the CPU.

FIG. 16 is a flowchart illustrating another example of the initialization processing.

FIG. 17 is an explanatory diagram showing a configuration example of a winning ball control command.

FIG. 18 is an explanatory diagram showing a bit configuration of a winning ball control command.

FIG. 19 is a timing chart showing how the award ball control command data is output.

FIG. 20 is a block diagram illustrating an example of a configuration around a CPU for controlling a prize ball for monitoring and backing up a power supply.

FIG. 21 is a flowchart showing a main process executed by a winning ball control CPU.

FIG. 22 is a flowchart showing a 2 ms timer interrupt process of the winning ball control CPU.

FIG. 23 is an explanatory diagram showing each counter in the winning ball control means.

FIG. 24 is a flowchart showing a prize ball control process of a prize ball control CPU.

FIG. 25 is a flowchart showing a prize ball control process of a prize ball control CPU.

FIG. 26 is a flowchart showing a prize ball control process of a prize ball control CPU.

FIG. 27 is a flowchart showing a prize ball control process of a prize ball control CPU.

FIG. 28 is a flowchart showing a prize ball control process of a prize ball control CPU.

FIG. 29 is a flowchart showing a prize ball control process of a prize ball control CPU.

FIG. 30 is a flowchart showing a winning ball count switch check subroutine.

FIG. 31 is a flowchart showing an NMI interrupt process of a winning ball control CPU.

FIG. 32 is a flowchart illustrating an example of initialization processing of a winning ball control CPU.

FIG. 33 is a flowchart showing an NMI interrupt process of a winning ball control CPU.

[Explanation of symbols]

 1 Pachinko gaming machine 31 Main board 37 Prize ball control board 53 Basic circuit 56 CPU 80 Display control board 101 Display control CPU 371 Prize ball control CPU 901 CPU 902, 932 Power supply monitoring IC 910 Power supply board 916 Capacitor

Claims (9)

[Claims] 1. A gaming machine for performing a predetermined game and controlling a gaming state advantageous to a player in accordance with the progress of the game, wherein the gaming machine controls a gaming device provided for the game. A control board, a gaming machine control microcomputer is mounted on the gaming machine control board, and at least a part of the volatile storage means in the gaming machine control board is turned off by a backup power supply. Can be backed up even when the power of the gaming machine is restored, it is possible to retain the gaming state storage required to restore the gaming state when the power of the gaming machine is restored, the gaming machine control microcomputer, the power supply of the gaming machine A signal indicating that the voltage has decreased by a predetermined amount is introduced to the non-maskable interrupt terminal, and data saving processing is performed in response to the signal being input to the non-maskable interrupt terminal. Sets a flag indicating that performing the data saving processing, the gaming machine wherein the flag performs data restoration processing when I set the flag which is characterized in that the initialization processing is not set at the time of return. 2. The data restoring process includes at least a process of resetting a flag indicating that the data saving process has been performed and a process of reading a game state storage for restoring the game state. Gaming machine. 3. The gaming machine according to claim 2, wherein the gaming machine control microcomputer is a gaming control microcomputer in a gaming control means for controlling the progress of the gaming, and the gaming state storage includes a processing address by a stack pointer. . 4. The gaming machine according to claim 3, wherein the game state storage includes at least register contents. 5. A game device control microcomputer, which is a game control microcomputer in a game control means for controlling the progress of a game, wherein the game state storage is for selectively performing processing at least according to the game state. 3. The gaming machine according to claim 2, including a flag. 6. The gaming machine control microcomputer is a microcomputer for controlling a prize ball in a prize ball control means for performing a prize ball payout control in accordance with a prize. The gaming machine according to claim 1, wherein the gaming machine is backed up so that it can be stored even if the supply is cut off. 7. The gaming machine according to claim 6, wherein the gaming state storage includes a processing address based on a stack pointer. 8. The gaming machine control microcomputer also introduces a signal indicating that the power supply voltage of the gaming machine has dropped by a predetermined amount to an input port, and when the signal returns to a level indicating a normal state, performs a data saving process. The gaming machine according to claim 1, wherein a flag indicating that the game has been performed is reset. 9. The gaming machine includes a power supply board that is provided separately from the gaming machine control board and generates each voltage used in the gaming machine control board, wherein the power supply board is provided in the gaming machine control board. 9. The gaming machine according to claim 1, further comprising a backup power supply for backing up a power supply of the RAM.