JP2001149536A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely preserve data required for restoring a game state in a game machine for controlling the recovery of the game state to recover the game state based on held data when a power source is supplied. SOLUTION: A game control base board is provided with a power source monitor IC 902 for generating a first voltage reduction signal to permit a game control CPU 56 to start a power supply stop time processing and the CPU 56 introduces a first voltage reduction signal to an NMI terminal to perform a data preservation processing. The board is also provided with a power source monitor IC 904 for generating a second voltage reduction signal to permit the CPU 56 to be in a reset state in the final loop part of the processing. Then the power supply stop time processing is surely performed and also data to be preserved during power source interruption are surely preserved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko game machine, a coin game machine, a slot machine, etc., in which a game is played in accordance with a player's operation. A gaming machine in which a game is played in accordance with a game machine.

[0002]

2. Description of the Related Art As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of prize balls are obtained. Are paid out to players.
Furthermore, a variable display unit capable of changing the display state is provided,
There is a configuration in which a predetermined game value is provided to a player when a display result of the variable display unit has a predetermined specific display mode.

[0003] The game value means that the state of the variable prize ball device provided in the game area of the gaming machine is in an advantageous state for a player who is likely to win a hit ball, or in an advantageous state for the player. Or a condition in which the conditions for paying out prize game media are easily satisfied.

In a pachinko gaming machine, when a display result of a variable display section for displaying a special symbol is a combination of a predetermined specific display mode, it is generally called a "big hit". When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state in which a hit ball is easy to win. In each open period, a predetermined number (for example, 10
) Will be closed when there is a prize in the special winning opening.
The number of opening of the special winning opening is a predetermined number (for example, 16
Round). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. Further, at the time when the special winning opening is closed, predetermined conditions (for example, winning in the V zone provided in the special winning opening)
Is not established, the big hit gaming state ends.

[0005] In addition, among the combinations of display modes other than the "big hit" combination, at a stage where some of the display results of the plurality of variable display portions have not been derived and displayed yet, the display results have already been derived and displayed. The state in which the display mode of the variable display unit that satisfies the display condition that is a combination of the specific display modes is called “reach”. If the display result of the identification information variably displayed on the variable display unit does not satisfy the condition of “reach”, the result is “out” and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

When a game ball wins a winning opening provided on the game board, a predetermined number of award balls are paid out. Since the progress of the game is controlled by the game control means mounted on the main board, the number of winning balls based on the winning is determined by the game control means,
Sent to the prize ball control board. Hereinafter, the game control means and the other control means may be respectively referred to as electric component control means.

[0007]

As described above, a gaming machine is equipped with various electric component control means including game control means. Generally, each electric component control means is constituted by a microcomputer. That is, a program is stored in a ROM or the like, and data that temporarily occurs in control or data that changes as the control progresses is stored in the RAM. Then, when a power-off state occurs due to a power failure or the like in the gaming machine, data in the RAM is lost. Therefore,
At the time of recovery from a power failure or the like, the player must return to the initial state (for example, the state when the game machine is first turned on at the game store for the day), which may be disadvantageous to the player. . For example, if a power failure occurs during a jackpot game and the gaming machine returns to the initial state, the player will not be able to enjoy the benefits based on the occurrence of the jackpot.

In order to avoid such a situation, necessary data is stored in a RAM which is held by a backup power supply when an unexpected power failure such as a power failure occurs, and is stored when the power is restored. The game may be resumed by restoring the data that was being played. However, if the storage method is not appropriate, the state may be recovered based on incorrect stored data. If the state is restored based on the erroneous saved data, the player may still be disadvantaged.

Therefore, the present invention is directed to a gaming machine capable of restarting control based on data held in storage means capable of holding the contents immediately before power supply is stopped at the time of starting power supply. It is another object of the present invention to provide a gaming machine capable of reliably storing data necessary for restarting control.

[0010]

A gaming machine according to the present invention comprises:
A gaming machine in which a player can play a predetermined game, and performs processing for controlling electric components provided in the gaming machine, and at the time of starting power supply, retaining contents immediately before stopping power supply. Electrical component control means capable of resuming control based on data held in a storage means capable of performing the control, and monitoring a voltage drop of a predetermined potential power supply used in the gaming machine to satisfy a first detection condition. A first power supply monitoring means for outputting a detection signal when the first power supply monitoring means detects a voltage drop of a potential power supply which is the same as or different from the predetermined potential power supply, and at least a predetermined time period from the establishment of the first detection condition in the first power supply monitoring means. A second set to hold after
A second power supply monitoring unit that outputs a detection signal when a detection condition is satisfied, wherein the first power supply monitoring unit and the second power supply monitoring unit are mounted on a board on which the electric component control unit is mounted; The electric component control means performs a predetermined power supply stop processing which can be executed within a predetermined period according to the detection signal from the first power supply monitoring means, and responds to the input of the detection signal from the second power supply monitoring means. The system is reset. Examples of the electric component control means include a game control means for controlling the progress of the game and a payout control means for controlling the payout of the game medium.

The first power supply monitoring means and the second power supply monitoring means monitor the voltage of the same predetermined potential power supply, and the voltage of the predetermined potential power supply at which the second power supply monitoring means outputs a detection signal is The first power supply monitoring means may be configured to be lower than the voltage at which the detection signal is output.

The predetermined potential power supply monitored by the first power supply monitoring means may be configured to be a power supply having a higher potential than an element driving power supply on a substrate on which the electric component control means is mounted.

[0013] The predetermined potential power supply monitored by the first power supply monitoring means may be configured to be a potential power supply immediately after conversion from AC to DC.

The electric component control means includes a microcomputer, and a detection signal from the first power supply monitoring means is input to an interrupt terminal of the microcomputer, and the microcomputer controls the power supply when the power supply is stopped based on the input to the interrupt terminal. It may be configured to execute processing.

The storage means capable of holding the contents immediately before the stop of the power supply may be configured to be included in the electric component control means. That is, the storage means is, for example, a memory (RAM) built in the microcomputer.
It may be.

The processing at the time of power supply stop may be configured to include processing for preventing access to the storage means.

The process at the time of power supply stop includes a process of storing check data obtained as a result of an operation related to the storage contents of the storage means in the storage means.
A check based on the check data may be performed at the start of power supply, and if the check result is normal, the control may be restarted based on the held data held in the storage unit.

The electric component control means may be configured to execute an initialization process if the check result is not normal.

The first power supply monitoring means is mounted on a substrate different from the substrate on which the electric component control means requiring the detection output is mounted, and the electric component control means is connected via the input buffer to the first power supply monitoring means. It may be configured to input a detection signal of the power supply monitoring unit.

The input buffer is an irreversible means capable of transmitting a signal only in a direction from the outside to the inside of the board on which the electric component control means requiring the detection output of the first power supply monitoring means is mounted. Preferably, there is.

The first power supply monitoring means and the second power supply monitoring means may be constituted by a single IC.

[0022]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of the pachinko gaming machine 1 as viewed from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the pachinko gaming machine 1 as viewed from the back. In the following embodiments, a description will be given of a pachinko gaming machine as an example, but the gaming machine according to the present invention is not limited to a pachinko gaming machine,
For example, a coin gaming machine or the like may be used. Further, the present invention can be applied to an image-type gaming machine or a slot machine.

As shown in FIG. 1, the pachinko gaming machine 1
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing prize balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, a variable display section 9 for variably displaying a plurality of types of symbols and a 7-segment L
A variable display device 8 including a variable display 10 using an ED is provided. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In a passage between the passage gate 11 and the ball outlet 13, there is a gate switch 12 for detecting a hit ball that has passed through the passage gate 11. In addition, the winning ball that entered the starting winning port 14 is
It is guided to the back of the game board 6 and is detected by the starting port switch 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16.

Below the variable winning ball device 15, there is provided an opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state). In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. The winning ball that enters one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V count switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. Variable display device 8
A start winning prize storage display 18 having four display sections for displaying the number of winning balls entering the starting winning prize port 14 is provided below. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The gaming board 6 is provided with a plurality of winning ports 19 and 24, and winning of the game balls to the winning ports 19 and 24 is detected by the winning port switches 19a and 24a. At the left and right sides of the game area 7, there are provided decorative lamps 25 which are displayed blinking during the game, and at the lower part there is an out port 26 for absorbing hit balls which have not won. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. A gaming effect LED 2 is provided on the outer periphery of the gaming area 7.
8a and gaming effect lamps 28b and 28c are provided.

In this example, one of the speakers 27
Is provided with a prize ball lamp 51 which is lit when a prize ball is paid out, and a ball out lamp 52 which is lit when a supply ball is out is provided near the other speaker 27. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming table 1 and enables lending of balls by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card can be used. If there is a fraction (less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter, the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passage gate 11, the display number of the variable display 10 is changed continuously. Further, when a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17, the symbol in the variable display section 9 starts rotating if the symbol can be changed. If it is not possible to start changing the symbol, the start winning memory is increased by one.

The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the specific winning area while the opening and closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols accompanied by a probability change, the probability of the next big hit increases. That is, a high probability state, which is more advantageous for the player, is obtained. Also, when the stop symbol on the variable display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the variable display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. On the back of the variable display device 8, as shown in FIG. 2, a prize ball tank 38 is provided above the mechanism plate 36, and when the pachinko gaming machine 1 is installed on the gaming machine installation island, a prize ball is provided from above. Premium ball tank 3
8 is supplied. The prize ball in the prize ball tank 38 reaches the ball payout device through the guide gutter 39.

On the mechanism board 36, a variable display control unit 29 for controlling the variable display section 9 via the relay board 30, and a game control board (main board) covered with a board case 32 and mounted with a game control microcomputer and the like. ) 31, a relay board 33 for relaying a signal between the variable display control unit 29 and the game control board 31, and a prize ball control board on which a prize ball control microcomputer for controlling the payout of prize balls is mounted. 37 are installed. Further, a ball is hit on the lower part of the mechanism plate 36 by using the rotating force of the motor in the game area 7.
Ball launching device 34 that launches on a game effect lamp / LE
D28a, 28b, 28c, a prize ball lamp 51 and a lamp control board 35 for sending signals to the ball out lamp 52 are provided.

FIG. 3 is a rear view of the gaming board of the pachinko gaming machine 1 as viewed from the rear. The ball that passed through the induction gutter 39
As shown in FIG. 3, the ball cut detectors 187a, 187
b, and reaches the ball dispensing device 97 via the ball supply gutters 186a and 186b. The prize ball paid out from the ball payout device 97 is supplied to the hit ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the communication port 45. On the side of the communication port 45, an excess ball passage 46 communicating with the excess ball tray 4 provided on the front of the pachinko gaming machine 1 is formed. A large number of prize balls based on the prize are paid out, and the ball supply tray 3 becomes full. Finally, after the prize balls reach the communication port 45, further prize balls are paid out. It is led to the ball tray 4. When the prize ball is further paid out, the sensing lever 47 is set to the full switch 4.
By pressing 8, the full tank switch 48 is turned on. In this state, the rotation of the stepping motor in the ball discharging device 97 stops, the operation of the ball discharging device 97 stops, and the driving of the hitting ball firing device 34 also stops as necessary. In addition,
In this embodiment, a ball payout device 97 in which game balls are paid out by rotation of a stepping motor is illustrated as a ball payout device that pays out game balls by driving an electric drive source. A ball payout device having a structure of sending out a ball may be used, or a ball payout device having a structure in which a stopper is removed by driving an electric drive source and payout is performed by the weight of the game ball may be used.

Signals from the winning opening switches 19a and 24a, the starting opening switch 17 and the V count switch 22 are sent to the main board 31 in order to perform the prize ball payout control.
When the starting port switch 17 is turned on, the CPU 56 of the main board 31 knows that a winning corresponding to the payout of six winning balls has occurred. Further, when the count switch 23 is turned on, it is known that a winning corresponding to the payout of 15 prize balls has occurred. Then, when the winning opening switch is turned on, it is known that a winning corresponding to the payout of 10 prize balls has occurred. In this embodiment, for example, a game ball that has won the winning opening 24 is detected by the winning opening switch 24 a provided in the winning ball flow path from the winning opening 24, and the game ball that has won the winning opening 19 is detected. Is
It is detected by a winning opening switch 19a provided in a winning ball flow path from the winning opening 19.

FIG. 4 is a block diagram showing an example of a circuit configuration of the main board 31. FIG. 4 also shows the prize ball control board 37, the lamp control board 35, the sound control board 70, the emission control board 91, and the display control board 80.
The pachinko machine 1 is provided on the main board 31 according to the program.
, A switch circuit 58 for giving signals from the gate switch 12, the starting port switch 17, the V count switch 22, the count switch 23, and the winning port switches 19a, 24a to the basic circuit 53, and a variable winning ball device. A solenoid circuit 59 for driving a solenoid 16 for opening and closing the opening 15 and a solenoid 21 for opening and closing the opening and closing plate 20 in accordance with a command from the basic circuit 53; A lamp / LED circuit 60 for driving the lamp 10 and the decorative lamp 25 is mounted.

According to the data supplied from the basic circuit 53, jackpot information indicating the occurrence of a jackpot, effective start information indicating the number of start winning balls used to start displaying an image on the variable display section 9, and probability fluctuation have occurred. And an information output circuit 64 that outputs probability change information or the like indicating the fact to a host computer such as a hall management computer.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as an example of a storage means used as a work memory, a CPU 56 for performing a control operation according to a control program, and an I / O port unit 57. including. In this embodiment, the ROM 54,
The RAM 55 is built in the CPU 56. That is,
The CPU 56 is a one-chip microcomputer.
The one-chip microcomputer has at least R
It is sufficient if the AM 55 is built-in.
The / O port section 57 may be externally mounted or built-in. The I / O port unit 57 is a terminal capable of inputting and outputting information in the microcomputer.

Further, the main board 31 has an initial reset circuit 65 for resetting the basic circuit 53 when the power is turned on.
And an address decode circuit 67 that decodes an address signal provided from the basic circuit 53 and outputs a signal for selecting one of the I / O ports in the I / O port unit 57. Although there is switch information input from the ball dispensing device 97 to the main board 31, FIG.
Then they are omitted.

A hit ball firing device that hits and fires a game ball is driven by a drive motor 94 controlled by a circuit on a firing control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

FIG. 5 is a block diagram showing components related to the prize ball, such as the components of the prize ball control board 37 and the ball payout device 97. As shown in FIG. 5, the detection signal from the full tank switch 48 is transmitted to the main board 3 via the relay board 71.
1 is input to the I / O port 57. Full tank switch 4
Reference numeral 8 denotes a switch that detects whether the surplus ball tray 4 is full.

The detection signals from the ball-out detection switch 167 and the ball-out switch 187 (187a, 187b) are transmitted to the main board 3 via the relay board 72 and the relay board 71.
1 is input to the I / O port 57. The out-of-ball detection switch 167 is a switch for detecting a shortage of replenishment balls in the prize ball tank 38, and the out-of-ball switch 187 is a switch for detecting the presence or absence of a prize ball in the prize ball passage.

The CPU 56 of the main board 31 determines whether the detection signal from the ball out detection switch 167 or the ball out switch 187 indicates that the ball is out, or the detection signal from the full switch 48 indicates the full state. If it is, a prize ball control command for instructing ball lending is sent. When receiving the award ball control command instructing the ball lending prohibition, the award ball control CPU 371 of the award ball control board 37 stops the ball lending process.

Further, detection signals from the prize ball count switch 301A and the ball lending count switch 301B are also transmitted to the main board 3 via the relay boards 72 and 71.
1 is input to the I / O port 57. The prize ball count switch 301A and the ball lending count switch 30
1B is provided in the prize ball mechanism portion of the ball payout device 97, and detects the prize balls actually paid out.

When there is a prize, the output ports (ports G, H) 577, 578 of the main board 31 are provided on the prize ball control board 37.
, A prize ball control command indicating the number of prize balls is input. The output port 577 outputs 8-bit data, and the output port 578 outputs a 1-bit strobe signal (INT signal). The award ball control command indicating the number of award balls is input to the I / O port 372a via the input buffer circuit 373. The CPU 371 for controlling the prize ball includes an I / O port 37.
A prize ball control command is input via 2a, and the ball payout device 97 is driven according to the prize ball control command to perform a prize ball payout. In this embodiment, the CPU 37 for controlling the prize ball
Reference numeral 1 denotes a one-chip microcomputer having at least a RAM.

The prize ball control CPU 371 is connected to the output port 3
Via 72g, a ball lending number signal indicating the lending ball number is output to the terminal board 160, and a buzzer drive signal is output to the buzzer board 75. A buzzer is mounted on the buzzer board 75. Further, an error signal is output to the error display LED 374 via the output port 372e.

Further, the input port 3 of the prize ball control board 37
The detection signal of the detection signal of the winning ball count switch 301A is input to 72b via the relay board 72. The drive signal from the prize ball control board 37 to the payout motor 289 is
The output is transmitted to the payout motor 289 in the winning ball mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72.

The card unit 50 is provided with a microcomputer for controlling the card unit. Also,
The card unit 50 is provided with a fraction display switch 152, a connection board direction indicator 153, a card insertion indicator lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected to a frequency display LED, a ball lending switch, and a return switch provided near the hit ball supply tray 3.

From the balance display board 74 to the card unit 50
In response to the player's operation, a ball lending switch signal and a return switch signal are provided via the prize ball control board 37. In addition, the balance display board 74 is provided from the card unit 50.
, A card balance display signal indicating the balance of the prepaid card and a ball lending possible display signal are given via the prize ball control board 37. Between the card unit 50 and the prize ball control board 37, a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal)
A pachinko machine operation signal (PRDY signal) is exchanged via the I / O port 372f.

When the power of the pachinko gaming machine 1 is turned on,
The prize ball control CPU 371 of the prize ball control board 37 outputs a PRDY signal to the card unit 50. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the microcomputer for controlling the card unit outputs a BRDY signal to the prize ball control board 37. When a predetermined delay time elapses from this point, the microcomputer for controlling the card unit outputs a BRQ signal to the prize ball control board 37. The CPU 37 for controlling the prize ball on the prize ball control board 37
1 drives the payout motor 289 and pays out a predetermined number of lending balls to the player. Then, when the payout is completed, the prize ball controlling CPU 371 outputs an EXS signal to the card unit 50.

As described above, all signals from the card unit 50 are input to the prize ball control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input from 0 to the main board 31, and there is no room for a signal to be incorrectly input from the card unit 50 side to the basic circuit 53 of the main board 31. The main board 31 and the prize ball control board 37 are provided with a solenoid and a driver circuit for driving a motor or a lamp, but those circuits are omitted in FIG.

In this embodiment, the case where the card unit 50 is provided is described as an example. However, the present invention can be applied to a case where a game ball is lent according to the amount of money when a coin is inserted.

FIG. 6 is a block diagram showing an example of a configuration around the CPU 56 for power supply monitoring and power supply backup. As shown in FIG. 6, a voltage drop signal from a power supply monitoring IC 902 constituting a first power supply monitoring circuit (first power supply monitoring means) is supplied to a non-maskable interrupt terminal (N
MI terminal). The first power supply monitoring circuit is
This circuit monitors the voltage of any one of various DC power supplies used by the gaming machine and detects a drop in the power supply voltage.
Therefore, the CPU 56 can confirm the occurrence of power interruption by the interrupt processing.

The power supply monitoring IC 902 detects the occurrence of power interruption by introducing a +30 V power supply voltage and monitoring the +30 V power supply voltage. Specifically, when the +30 V power supply voltage becomes equal to or lower than a predetermined value (+21 V in this example), a voltage drop signal is output assuming that power supply is cut off. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, +30 V, which is a voltage immediately after conversion from AC to DC, is used.

The predetermined value for the power supply monitoring IC 902 to detect the power-off is lower than the normal voltage.
Is a voltage that can operate for a while. The power supply monitoring IC 902 is set to monitor a voltage higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and a voltage immediately after conversion from AC to DC. Is preferred. When the monitoring voltage is set to such a voltage, the monitoring range can be expanded with respect to the voltage required by the CPU. Therefore, more precise monitoring can be performed.

Further, when +30 V is used as the monitoring voltage, the voltage supplied to various switches of the gaming machine is +
Since the voltage is 12 V, prevention of erroneous switch-on detection at the moment of power interruption can be expected. That is, when monitoring the voltage of the + 30V power supply, the + 12V generated after the + 30V generation
Can be detected before it begins to fall. Therefore, when the voltage of the + 12V power supply drops, the switch output comes to an on state. However, if the + 30V power supply voltage that drops earlier than the + 12V is monitored and the power cutoff is recognized,
It is possible to enter a state of waiting for a power supply recovery before the switch output is turned on, so that the switch output is not detected.

A power supply monitoring IC 904 constituting a second power supply monitoring circuit is also mounted on the main board 31. In this example, the power supply monitoring IC 904 monitors a +30 V power supply voltage, which is a power supply voltage equal to the power supply voltage monitored by the first power supply monitoring circuit, and generates a low-level voltage drop signal when the voltage value falls below a predetermined value. I do. Then, for example, the detection voltage of the first power supply monitoring circuit (the voltage at which a voltage drop signal is output) is set to +21 V, and the detection voltage of the power supply monitoring IC 904 is set to +9 V.

Therefore, in this example, the first detection condition under which the first power supply monitoring means outputs a detection signal is +30.
V power supply voltage has dropped to +21 V, and the second
The second detection condition under which the power supply monitoring means outputs a detection signal is that the +30 V power supply voltage has dropped to +9 V. However, the voltage value used here is an example, and another value may be used.

In such a configuration, since the same voltage is monitored, the timing at which the first voltage monitoring circuit outputs a voltage drop signal and the timing at which the second voltage monitoring circuit outputs the voltage drop signal are determined. The difference can be reliably set to a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop processing in response to the voltage drop signal from the first power supply monitoring circuit until the power supply stop processing is completely completed.

However, although the monitoring range is narrowed, the monitoring voltage of the first voltage monitoring circuit and the second voltage monitoring circuit is +
It is also possible to use a 5V power supply voltage. Also in that case, the detection voltage of the first voltage monitoring circuit is set higher than the detection voltage of the second voltage monitoring circuit.

The voltage drop signal from the power monitoring IC 904 is logically ORed with the initial reset signal from the initial reset circuit 65 and then input to the reset terminal of the CPU 56. Therefore, the CPU 56 sets the initial reset circuit 65
The reset state (non-operating state) is established when the initial reset signal from the IC has a low level, or when the voltage drop signal from the power supply monitoring IC 904 has a low level.

The reset I of the initial reset circuit 65
When the power of the gaming machine is turned on and the voltage of the + 5V power supply rises, the C651 sets the output signal to a high level when the + 5V power supply voltage exceeds a predetermined value. That is, the initial reset signal is turned off.

While power is not supplied from the +5 V power supply which is the driving power supply of the CPU 56 and the like, at least a part of the RAM is backed up by the backup power supply supplied from the power supply board, and the contents are maintained even if the power supply to the gaming machine is cut off Is saved. Then, when the +5 V power supply is restored, a reset signal is issued from the initial reset circuit 65, and the CPU 56 returns to the normal operation state. At that time, since the necessary data is backed up, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovering from a power failure or the like.

FIG. 7 is a block diagram showing a configuration example of a power supply board 910 of a gaming machine. The power supply board 910 is installed independently of the electric component control boards such as the main board 31, the display control board 80, the sound control board 70, the lamp control board 35, and the prize ball control board 37, and controls each electric component control board in the gaming machine. And the voltages used by the mechanical components. In this example,
AC24V, DC + 30V, DC + 21V, DC + 12
V and + 5V DC. Further, the capacitor 916 serving as a backup power supply is charged from DC + 5V, that is, a power supply line for driving an IC or the like on each substrate.

The transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
The C converter 913 has + 21V, + 12V and + 5V.
V is generated and output to the connector 915. Connector 91
5 is connected to, for example, a relay board, from which electric power of a voltage required for each electric component control board and mechanism components is supplied. A power switch 918 for stopping and starting power supply to the gaming machine is provided on the input side of the transformer 911.

+5 V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is provided with an electric power so as to be able to hold a storage state in a backup RAM (power-backed-up RAM, that is, storage means that can be in a storage state) when the power supply to the gaming machine is cut off. Backup power supply. Also,
A diode 917 for preventing backflow is inserted between the + 5V line and the backup + 5V line.

Note that a battery that can be charged from a + 5V power supply may be used as a backup power supply. In the case of using a battery, a rechargeable battery is used which runs out of capacity when power is not supplied from a + 5V power supply for a predetermined time.

Next, the operation of the gaming machine will be described. FIG.
9 is a flowchart showing a main process executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main processing, the CPU 56 first checks whether or not the power has been restored from the power failure (step S1). Whether or not recovery from a power failure has occurred is confirmed by, for example, a power-off flag set in the backup RAM area when the power is turned off.

If it is time to recover from a power failure, a data check (parity check in this example) of the backup RAM area is performed (step S3). If the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, and the check result becomes normal. If the check result is not normal, since the internal state cannot be returned to the state at the time of power failure, an initialization process executed at the time of power-on without power recovery is executed (steps S4 and S2).

If the check result is normal, the CPU 56
Performs the game state restoring process for returning the internal state to the state at the time of power-off (step S5), and clears the power-off flag (step S6).

When not recovering from a power failure, the CPU
56 executes a normal initialization process (step S1,
S2). Thereafter, in the main process, the process shifts to a loop process in which the monitoring of the timer interrupt flag (step S6) is confirmed. In the loop, a display random number update process (step S7) is also executed.

Here, in step S1, it is confirmed whether or not the power is restored from the power failure. If the power is restored from the power failure, the parity check is performed. First, the parity check is executed and the check result is normal. Otherwise, it is determined that it is not the recovery from the power failure, and the initialization processing of step S2 is executed, and if the check result is normal, the game state return processing may be performed. That is, it may be determined based on the result of the parity check whether recovery from a power failure has occurred.

When determining whether or not to execute the power failure recovery processing, that is, when determining whether or not to recover the gaming state, the special process flag or the like in the stored RAM data and the number of start winning prizes are stored. According to the data, the gaming machine is in the game waiting state (the symbol is not changing, the jackpot is not playing, the probability is not changing, and there is no start winning memory)
When it is confirmed that the game state is restored, the initialization processing may be executed without performing the game state restoration processing.

In the normal initialization process, as shown in FIG. 9, the register and RAM are cleared (step S2).
a) and the initial setting (timeout is 2 ms) of the timer register provided in the CPU 56 so that the timer is periodically interrupted every 2 ms after the necessary initial value setting processing (step S2b) is performed. And a setting for operating the repetition timer) is performed (step S2c). That is, in step S2c, a process of activating a timer interrupt and a process of setting a timer interrupt interval are executed.

Therefore, in this embodiment, the CPU 56
Is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is 2 ms
Is set to Then, as shown in FIG. 10, when a timer interrupt occurs, the CPU 56 sets a timer interrupt flag (step S11).

When detecting that the timer interrupt flag is set in step S8, the CPU 56 resets the timer interrupt flag (step S8).
9), a game control process is executed (step S10). According to the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the game control process is executed in the main process.
The game control process may be executed by a timer interrupt process.

FIG. 11 is a flowchart showing the game control processing in step S10. In the game control process,
The CPU 56 first performs processing for setting a display control command sent to the display control board 80 in a predetermined area of the RAM 55 (display control data setting processing: step S
21), a process of outputting a display control command is performed (display control data output process: step S22).

Next, processing for outputting the contents of the storage area for various output data to each output port is performed (data output processing: step S23). Further, an output data setting process for setting output data such as big hit information, start information, and probability variation information output to the hall management computer in the storage area is performed (step S24). Further, various abnormality diagnosis processes are performed by the self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S25).

Next, a process of updating each counter indicating a random number for determination such as a random number for big hit determination used in game control is performed (step S26).

Further, the CPU 56 performs a special symbol process (step S27). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Further, a normal symbol process is performed (step S28). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

Further, the CPU 56 includes a switch circuit 58
, The state of the gate sensor 12, the starting port sensor 17, the count sensor 23, and the winning port switches 19a and 24a are input, and it is determined whether or not each of the winning ports and the winning device has a winning (switch processing: step S29). .
The CPU 56 further performs a process of updating a display random number such as a random number that determines the type of stop symbol (step S3).
0).

The CPU 56 performs signal processing between the CPU 56 and the award ball control board 37 (step S31). That is,
When a predetermined condition is satisfied, a prize ball control command is output to the prize ball control board 37. The prize ball control CPU mounted on the prize ball control board 37 drives the ball payout device 97 according to the prize ball control command.

As described above, the main processing includes the processing for determining whether or not to shift to the game control processing.
Since a flag is set to determine whether or not to shift to the game control process in the timer interrupt process based on the timer interrupt that is periodically generated by the 56 internal timers, all the game control processes are reliably executed. Is done. In other words, until all of the game control processes have been executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all processes in the game control process will be completed. ing.

In the conventional general game control processing, the game machine is forcibly returned to the initial state by an external interrupt that occurs periodically. Describing with reference to the example shown in FIG. 11, for example, even during the process of step S31, the process is forcibly returned to the process of step S21. In other words, there is a possibility that the next game control process will be started before all the processes in the game control process are completed.

Here, the CPU 56 of the main board 31
Is executed in response to a flag set in a timer interrupt process based on a timer interrupt that is periodically generated by an internal timer of the CPU 56, but the signal is periodically (for example, every 2 ms). A hardware circuit which generates the signal may be provided, a signal from the circuit may be introduced to an external interrupt terminal of the CPU 56, and a flag for determining whether or not to shift to the game control process based on the interrupt signal may be set. Good.

Even in such a configuration, the flag is not determined until all the game control processes have been executed, so that execution of all the processes in the game control process is guaranteed to be completed. You.

FIG. 12 is a flowchart showing an example of the power failure occurrence NMI process executed in response to the NMI based on the voltage drop signal from the first power supply monitoring circuit. In the power failure occurrence NMI process, the CPU 56 first sets interrupt prohibition (step S41). In the power failure occurrence NMI process, a checksum generation process is performed to ensure that the contents of the RAM are preserved. If another interrupt process is performed during the process, the CP is generated before the checksum generation process is completed.
Since it is conceivable that the voltage of U may be reduced to a voltage at which it cannot operate, first, settings are made so that other interrupts do not occur. Steps S43 to S49 in the power failure occurrence NMI process are an example of a power supply stop process.

When a CPU having a specification that does not cause another interrupt during the interrupt processing is used, the processing in step S41 is unnecessary.

Next, the CPU 56 checks whether or not the power-off flag has already been set (step S4).
2). If the power-off flag has already been set, no further processing is performed. If the power-off flag is not set, the following power supply stop processing is executed. That is,
The processing from step S43 to step S49 is executed.

First, all output ports are turned off (step S43). If necessary, the contents of each register are stored in the backup RAM area (Step S).
44). Further, an appropriate initial value is set in the backup check data area of the backup RAM area (step S45), and exclusive OR is sequentially performed on the initial value and the data of the backup RAM area (step S4).
6), the final operation value is set in the backup parity data area (step S47). Thereafter, a power-off flag is set (step S48). Further, the RAM access is prohibited (step S49). When the power supply voltage decreases, the levels of various signal lines may become unstable and the contents of the RAM may be corrupted.
If AM access is prohibited, backup RA
The data in M will not be corrupted.

Next, the CPU 56 enters a loop process. That is, no processing is performed. Therefore, before the operation is disabled from the outside by the reset signal from the power supply monitoring IC 904 shown in FIG. 6, the operation is internally stopped. Therefore, when the power is turned off, the operation of the CPU 56 is reliably stopped. As a result, the RAM
The access prohibition control and the operation stop control can reliably prevent the contents of the RAM from being destroyed due to an abnormal operation that may occur as the power supply voltage decreases.

In this embodiment, the power failure occurrence NM
In I processing, the program was looped in the last part,
It may be configured to issue a HALT instruction.

The power-off flag set before the RAM access is prohibited is used to determine whether or not recovery from a power failure has occurred at power-on, as described above. Further, the processing of steps S41 to S49 is completed before the second power supply monitoring unit generates the voltage drop signal.
In other words, the detection voltages of the first voltage monitoring means and the second voltage monitoring means are set so that the detection is completed before the second power supply monitoring means generates the voltage drop signal.

In this embodiment, the power-off flag is checked at the start of the power-supply-stop processing. If the power-off flag has already been set, the power supply stop processing is not executed. As described above, the power-off flag is a flag indicating that the power-supply-stop processing has been completed. Therefore, for example, even if the NMI occurs again for some reason in the reset waiting loop state, the power supply stop processing will not be repeatedly executed.

However, if a CPU having a specification that does not cause another interrupt during the interrupt processing is used, the determination in step S42 is unnecessary.

FIG. 13 is an explanatory diagram for explaining a backup parity data creating method. However, FIG.
In the example shown in FIG.
The size of the data in the M area is 3 bytes. In the power failure generation process based on the power supply voltage drop, as shown in FIG. 13A, initial data (00H in this example) is set in the backup check data area. Next, "00
The exclusive OR of “H” and “F0H” is calculated, and the result is exclusive ORed with “16H”. Further, an exclusive OR of the result and “DFH” is obtained. Then, the result (“39H” in this example) is set in the backup parity data area.

When the power is turned on again, the parity diagnosis is performed in the power failure recovery processing. FIG. 13B is an explanatory diagram showing an example of the parity diagnosis. If all the data in the backup area is stored as it is, the data as shown in FIG. 13A is set in the backup area when the power is turned on again.

In the process of step S51, the CPU 5
6 is the data set in the backup parity data area of the backup RAM area (in this example, “39”).
H)) as initial data, a process of sequentially taking an exclusive OR for each data in the backup data area is performed.
If all the data in the backup area is stored as it is, the final calculation result is “00H”, that is, the same as the data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final calculation result is “00”.
H ".

Therefore, the CPU 56 compares the final operation result with the data set in the backup check data area, and if they match, determines that the parity diagnosis is normal. If they do not match, it is determined that the parity diagnosis is abnormal.

As described above, in this embodiment, the game control means is provided with the storage means (backup RAM in this example) which is backed up for a predetermined period even if the power of the game machine is turned off. At the time of insertion, the CPU 56 (specifically, a program executed by the CPU 56) is configured to perform a game state restoration process (step S5) for restoring the game state based on the backup data if the storage means is in the backup state. .

As described above, in this embodiment, FIG.
As shown in (1), the first power supply monitoring means and the second power supply monitoring means are mounted on the main board 31. When the power supply voltage decreases, the time at which the second power supply monitoring means (power supply monitoring IC 904 in this example) generates the voltage drop signal is determined by the first power supply monitoring means (power supply monitoring in this example). The IC 902) is set to be later than the time at which the voltage drop signal is generated. Further, a voltage drop signal from the second power supply monitoring means is input to a reset terminal of the CPU 56.

Then, the CPU 56 enters the loop state after executing the power failure generation processing (power supply stop processing) based on the voltage drop signal from the first power supply monitoring means (power supply monitoring IC 902). In a loop state, a reset state is entered. That is, CPU
The operation at 56 stops completely. + In loop state
Since the 5V power supply voltage value gradually decreases, the input / output state becomes unstable. However, since the CPU 56 is in the reset state, abnormal operation based on the unstable data is prevented.

As described above, in this embodiment, the CPU
56 is configured so as to enter a loop state in response to the input of the detection output from the first power supply monitoring means and to be system reset in response to the input of the detection output from the second power supply monitoring means. It is possible to reliably store data at the time of disconnection, and prevent disadvantages from being brought to the player.

In this embodiment, the power monitoring I
Although C902 and 904 monitor the same power supply voltage, they may monitor different power supply voltages. For example, the power supply monitoring IC 902 constituting the first power supply monitoring circuit is +30
The V power supply voltage may be monitored, and the power supply monitoring IC 904 constituting the second power supply monitoring circuit may monitor the + 5V power supply voltage. The threshold of the power supply monitoring IC 904 is set such that the timing at which the second power supply monitoring circuit generates the low-level voltage drop signal is later than the timing at which the first power supply monitoring circuit generates the voltage drop signal. The level (voltage level at which a voltage drop signal is generated) is set. For example, the threshold is 4.25V. 4.25 V is a voltage lower than the normal voltage, but a voltage at which the CPU 56 can operate for a while.

In the above embodiment, the CPU 56
Detected the first voltage drop signal (voltage drop signal from the first power supply monitoring means) via the non-maskable interrupt terminal (NMI terminal), but detected the first voltage drop signal as a maskable interrupt. May be introduced to the input terminal (IRQ terminal). In that case, the power supply stop processing is executed in the interrupt processing (IRQ processing). Further, the first voltage drop signal may be detected through the input port. In that case, the input port is monitored in the main processing.

When the first voltage drop signal is detected via the IRQ terminal, an IRQ interrupt mask is set at the start of the game control processing in step S10 of the main processing,
At the end of the game control process, the IRQ interrupt mask may be released. In such a case, an interruption occurs before and after the start of the game control process, so that the game control process is not interrupted halfway. Therefore, there is no possibility that the command transmission is interrupted when the award ball control command is transmitted to the award ball control board 37 or the like.
Therefore, even when a power failure occurs, the transmission of the prize ball control command or the like is surely completed.

Hereinafter, the game state restoring process will be described. First, in this embodiment, the CP of the main substrate 31
A display control command, a sound control command, and a lamp control command that the U56 sends to the display control board 80, the sound control board 70, and the lamp control board 35 will be described.
Each control command is determined to be sent according to the progress of the game in the special symbol process process (step S27) in the game control process shown in FIG. 11, and specific data is displayed in the display control data setting process (step S21). Is set, and is transmitted by being output from the output port in the display control data output process (step S22).

FIG. 14A is an explanatory diagram showing an example of the transmission timing of each control command relating to the symbol variation on the variable display section 9. In this embodiment, the C
When starting the symbol change, the PU 56 sends a change start command to each of the display control board 80, the sound control board 70, and the lamp control board 35. To the display control board 80, a symbol designating command indicating a fixed symbol of the middle left and right symbols is further transmitted.

When the symbol variation is determined, a variation stop command is sent to each of the display control board 80, the sound control board 70, and the lamp control board 35.
Each CPU mounted on the display control board 80, the sound control board 70, and the lamp control board 35 performs display control, sound generation control, and lamp lighting control according to the variation mode specified by the variation start command. The change start command includes information indicating the change time.

FIG. 14B is an explanatory diagram showing an example of the transmission timing of each control command relating to the big hit game executed when the display result of the variable display section 9 is a predetermined big hit symbol. In this embodiment, the CPU of the main board 31
56 sends a big hit start command to each of the display control board 80, the sound control board 70, and the lamp control board 35 at the start of the big hit game. After a lapse of a predetermined time, a one-round (1R) designation command is transmitted. When each CPU mounted on the display control board 80, the sound control board 70, and the lamp control board 35 receives the big hit start command, it performs display control, sound generation control, and lamp lighting control at the start of the big hit. When a one-round designation command is received, display control, sound generation control, and lamp lighting control during a big hit are performed. However, the display control board 80
CPU performs the first round of display.

Thereafter, the CPU 56 of the main board 31 sequentially sends commands indicating each round to the display control board 80. The CPU of the display control board 80 performs corresponding display control according to these commands.

At the end of the big hit game, the CPU 56 of the main board 31 sends a big hit end command to each of the display control board 80, the sound control board 70, and the lamp control board 35. Then, after a predetermined time has elapsed, a normal screen display command is transmitted. Upon receiving the normal screen display command, each electric component control means changes the control state to a game waiting state.

FIG. 15 is a flowchart showing an example of the game state restoring process performed in the power failure restoring process shown in FIG. In this example, if it is necessary to restore the contents of the register, the CPU 56 restores the value stored in the backup RAM to the register (step S61). Then, the game state at the time of the power failure is confirmed based on the data stored in the backup RAM. For example, the gaming state can be confirmed by the value of the special symbol process flag corresponding to the progress of the special symbol process.

If the game state is changing symbols (step S62), control is performed to send a change start command to the display control board 80, the sound control board 70, and the lamp control board 35 (step S63). If the gaming state is a jackpot game (step S64), the last transmitted control command before the power failure is displayed on the display control board 8.
0, control to send to the sound control board 70 and the lamp control board 35 is performed (step S65). When the game state is other than the above, for example, the normal screen display command is transmitted to the display control board 80 and the sound control board 7.
0 and control to send to the lamp control board 35 is performed (step S66). In addition, for example, the state of the variable prize ball device 15 when the big hit is in progress is automatically performed in a later game control process because the data in the RAM is stored.

Here, the game state restoring processing program is configured to return to the main processing when the game state restoring processing is completed, but the stack area pointed to by the stack pointer stored in the power supply stop processing is set. The address stored in the backup RAM area (in the backup RAM area) (the address executed when the NMI interrupt occurs when the power is turned off) may be returned.

FIG. 16 is an explanatory diagram showing an example of a control state when the power is restored after a power failure has occurred. In FIG. 16, the state of the variable display is realized by the CPU (display control means) of the display control board 80, and the state of the sound is the sound control board 7
0 is realized by the CPU (sound control means), and the state of the lamp is controlled by the CPU (lamp control means) of the lamp control board 35.
It is realized by.

FIG. 16A shows an example in which the power is restored after a power failure occurs during the symbol change. In this case, when the power is restored, a change start command is sent from the main board 31 (step S63 in FIG. 16). Since the change start command is a command sent at the start of the symbol change,
The states of the variable display control, the sound control, and the lamp control return to the states at the start of the change. In this embodiment, the fluctuation start command includes information for specifying the fluctuation time, and the main board 3
After transmitting the fluctuation start command, the first CPU 56 does not transmit anything (except for the symbol designation command) until the finalization command at the end of fluctuation (fluctuation stop command). Therefore, if a power failure occurs during the symbol change, the change cannot be restarted from the state in the middle of the change, but the display control, sound control, and lamp control are synchronized by resending the change start command. Return to

Note that, on the main board 31, various parameters used at the start of the fluctuation are stored in the backup RAM. Therefore, the display results (fixed symbols) and the like in the fluctuations after the restoration of the power supply are the same as the display results and the like that would have been made in the fluctuations interrupted by the power failure. Therefore, there is no disadvantage to the player.

FIG. 16B shows an example of a case where the power is restored after a power failure occurs during the big hit game. In this case, when the power is restored, the command sent from the main board 31 to the display control board 80, the sound control board 70, and the lamp control board 35 last before the power failure is sent again (step S65 in FIG. 15). Therefore, the sound control and the lamp control return to the control state during the big hit game. In addition, the display control also returns to the state performed at the time of the power failure.

In the main board 31, various parameters during the big hit game (number of times of opening of the special winning opening, number of winning balls of the special winning opening, etc.) are stored in the backup RAM. Therefore, since the game state for the player also returns to the state before the power failure, there is no disadvantage to the player.

In the above-described embodiment, the case has been described where the game control means performs the data saving processing and the recovery processing.
May be backed up by a power source, and the prize ball control means, the display control means, the sound control means, and the lamp control means may also perform the processing described above. However, the prize ball control means, the display control means, the sound control means, and the lamp control means do not need to perform the command transmission processing at the time of restoration.

In this embodiment, in the power failure generation processing (power supply suspension processing), when the power supply interruption flag indicating that the power supply suspension processing has already been executed is set, the power supply suspension processing is performed. It is configured not to execute processing. In the process of turning off the power, the power supply voltage generally becomes unstable, so NMI may occur again.
Then, when the power-off flag is not confirmed in the power failure occurrence processing, the power supply stop processing is executed again by the NMI that has occurred again.

In the normal power supply stop processing executed first, for example, processing for storing the contents of the register in the backup RAM is performed (step S4 in FIG. 12).
4). Since the power supply voltage gradually decreases in the state of waiting for reset after the normal power supply stoppage processing executed first, the contents of the register may be destroyed.
That is, the register value may have changed from the state at the time when the power-off was detected (when NMI first occurred). If the power supply stop processing is executed again in such a state, a value different from the register value in the state at the time when the power-off is detected is stored in the backup RAM. Then, in the power failure recovery processing executed at the time of power recovery, a value different from the register value in the state at the time when the power failure is detected is restored to the register. As a result, there is a possibility that a game state different from the game state when the power is turned off is reproduced.

Next, the operation of the prize ball control means when a power failure occurs will be described. FIG. 17 is a block diagram showing an example of a configuration around the CPU 371 for controlling the prize ball for monitoring and backing up the power supply. As shown in FIG. 17, the voltage drop signal from the power supply monitoring IC 932 constituting the first power supply monitoring circuit (first power supply monitoring means) is transmitted to the prize ball control CP.
It is input to the non-maskable interrupt terminal (NMI terminal) of U371. Therefore, the CPU 371 for controlling the award ball controls the NMI
The occurrence of power interruption can be confirmed by the processing.

The power supply monitoring IC 932 detects the occurrence of power interruption by introducing a +30 V power supply voltage and monitoring the +30 V power supply voltage. Specifically, when the +30 V power supply voltage becomes equal to or lower than a predetermined value (for example, +21 V), it is determined that the power supply is cut off and a voltage drop signal is output. The monitoring power supply voltage is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, +30 V, which is a voltage immediately after conversion from AC to DC, is used.

The predetermined value for the power supply monitoring IC 932 to detect the power-off is lower than the normal voltage.
This is a voltage at which the PU 371 can operate for a while. The power supply monitoring IC 932 is set to monitor a voltage higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and a voltage immediately after conversion from AC to DC. Is preferred.

While power is not supplied from the + 5V power supply which is the drive power supply for the prize ball control CPU 371 and the like, at least a part of the internal RAM of the prize ball control CPU 371 uses the backup power supplied from the power supply board 910 as a backup. Backed up by connecting to the terminal,
The contents are preserved even if the power to the gaming machine is turned off. When the + 5V power supply is restored, the initial reset circuit 935
Generates a reset signal from the CPU for controlling the prize ball.
371 returns to the normal operating state. At that time, since the necessary data is backed up, the payout control can be restarted from the state at the time of the power failure at the time of recovery from a power failure or the like.

A power supply monitoring IC 934 constituting a second power supply monitoring circuit is also mounted on the prize ball control board 37.
In this example, the power supply monitoring IC 934 monitors a +30 V power supply voltage, which is the same voltage as the power supply voltage monitored by the first power supply monitoring circuit, and generates a low-level voltage drop signal when the voltage value falls below a predetermined value. . The detection voltage (the voltage at which the voltage drop signal is output) of the second power supply monitoring circuit is
It is set lower than the detection voltage of the first power supply monitoring circuit.

The voltage drop signal from the power supply monitoring IC 934 is logically ORed with the initial reset signal from the initial reset circuit 935 and then input to the reset terminal of the prize ball control CPU 371. Therefore, the CPU 37 for controlling the prize ball.
1 indicates a reset state (non-operating state) when the initial reset signal from the initial reset circuit 935 has a low level, or when the voltage drop signal from the second power supply monitoring circuit has a low level. )become.

FIG. 18 shows the main board 31 to the prize ball control board 3.
7 is an explanatory diagram showing an example of a bit configuration of a prize ball control command transmitted to No. 7; FIG. As shown in FIG. 18, the upper four bits in one byte are used as a control designator, and the lower four bits are used as an area indicating the number of award balls.

As shown in FIG. 19, if bits 7, 6, 5, and 4 are "0, 1, 0, 0" in the control designation section, it indicates that the command is a payout number designation command. ,
"0, 1" indicates a payout designation command.
The payout number designation command is sent to the prize ball control board 37 immediately after the CPU 56 of the main board 31 detects a winning.

Bits 7, 6, 5, and 4 are "1, 0, 0,
The ball-out designation command of “0” is transmitted from the main board 31 when it is detected that there is no more supply ball. The firing stop designation command in which the bits 7, 6, 5, and 4 are "1, 0, 0, 1" indicates that the surplus ball tray 4 is full and the full switch 48 is turned on (the full tank state). (When the flag is turned on).

The award ball control command is output from the main board 31 to the award ball control board 37 as 1-byte (8 bits: award ball control commands D7 to D0) data. The winning ball control commands D7 to D0 are output in positive logic. When the award ball control commands D7 to D0 are output, a negative logic award ball control INT signal is output.

In this embodiment, as shown in FIG. 20, when the prize ball control commands D7 to D0 are output from the main board 31, the prize ball control INT signal goes low for at least 5 μs. The prize ball control INT signal is transmitted to the prize ball control board 37.
Is connected to the interrupt terminal of the CPU 371 for controlling the prize ball. Therefore, when there is an interrupt, the award ball control CPU 371 transmits the award ball control commands D7 to D0 to the main board 31.
And recognizes that it has been sent from the CPU, and performs a prize ball control command receiving process in the interrupt process.

The command configuration shown in FIG. 18 is an example, and another configuration may be used. For example, the upper and lower parts in one byte may be reversed from the configuration shown in FIG. Also, the command configuration may be a multi-byte configuration instead of a 1-byte configuration.

FIG. 21 is a flowchart showing the main processing of the award ball control CPU 371. In the main processing,
The winning ball control CPU 371 first performs an initial value setting process such as clearing the RAM area (step S701).
If data is set in the RAM area (backup RAM area) of the built-in RAM where the power is backed up, those areas are not cleared. After that, in this embodiment, the CPU 371 for controlling the prize ball.
Shifts to a loop process for checking the monitoring of the timer interrupt flag (step S702).

In the initialization processing of step S701, when the value of the total number storage described later is not 0, the non-backup RAM area is cleared. Then, setting for restarting the prize ball is performed. For example, a flag during processing of a prize ball is set. If the backup RAM area is an area irrespective of the number of prize balls, those addresses may be designated and cleared. Furthermore, in addition to these processes, initial settings of a timer register provided in the CPU for controlling a prize ball 371 so that a timer interrupt is periodically performed every 2 ms (setting that the timeout is 2 ms and setting of the repetition timer operating) ) Is performed. That is, a process of activating a timer interrupt and a process of setting a timer interrupt interval are executed.

Therefore, in this embodiment, the internal timer of the prize ball control CPU 371 is set so as to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. Then, as shown in FIG. 22, when a timer interrupt occurs, the CPU 371 for controlling the prize ball.
Sets the timer interrupt flag (step S71)
1).

The award ball control CPU 371 proceeds to step S7.
In 02, when it is detected that the timer interrupt flag has been set, the timer interrupt flag is reset (step S703), and a prize ball control process and a ball lending control process are executed (steps S705 and S706). According to the above control, in this embodiment, the prize ball control process and the ball lending control process are started every 2 ms. In this embodiment, only the flag is set in the timer interruption processing, and the prize ball control processing and the like are executed in the main processing. However, the prize ball control processing and the like may be executed in the timer interruption processing.

FIG. 23 is an explanatory diagram showing an example of use of a RAM built in the CPU 371 for controlling a prize ball. In this example,
In the backup RAM area, a total number storage (for example, 2 bytes) and a rental ball number storage are formed. The total number storage stores the total number of payouts instructed from the main board 31 side. The lending ball number storage stores the number of unpaid ball lending.

FIG. 24 is a flowchart showing a prize ball control command receiving process by the interrupt process. The award ball control INT signal from the main board 31 is input to the interrupt terminal of the award ball control CPU 371. Therefore, when the award ball control INT signal from the main board 31 is turned on, the award ball control CP
U371 is interrupted, and the receiving process of the award ball control command shown in FIG. 24 is started.

In the receiving process of the award ball control command, the award ball control CPU 371 first reads 1-byte data from the input port assigned to the input of the award ball control command data (step S852). If the read data is a payout number instruction command (step S8)
53), the number specified by the payout number instruction command is added to the total number storage (step S855). Otherwise, a communication end flag is set (step S85).
4). In this example, the communication end flag is a flag indicating that a command other than the payout number instruction command has been received.

As described above, the prize ball control CPU 371 mounted on the prize ball control board 37 is
The number of award balls included in the payout number instruction command sent from 6 is stored in the backup RAM area (total number storage).

FIG. 25 shows a prize ball control process (step S71).
It is a flowchart which shows 1). In the prize ball control processing, the prize ball control CPU 371 checks whether or not the total number storage is not 0 (step S511). If the total number storage is not 0, the award ball control CPU 371 performs an award ball payout process (step S512). In the prize ball payout process, if the payout motor 289 is not turned on, it is turned on, and the detection output of the prize ball count switch 301A is used to confirm whether or not the game balls have been paid out. When it is confirmed that one payout has been made (step S513), the value of the total number storage is decremented by one (step S513).
514). When the value of the total number storage becomes 0 (step S515), the payout motor 289 is turned off (step S516).

The contents of the total number storage are retained by the backup power supply of the power supply board 910 for a predetermined period even if the power of the gaming machine is turned off. Therefore, when the power is restored during the predetermined period, the award ball control CPU 371 can continue the award ball payout process based on the contents of the total number storage.

When the power is turned on, the CPU 371 for controlling the prize ball can determine whether to perform the normal initialization processing or to restore the state during the prize ball simply by checking the data in the backup RAM area. That is, with a simple judgment,
The prize ball processing can be restarted for the unpaid prize balls.

The CPU for controlling prize balls 371 manages the number of prize balls instructed from the main board 31 as a total number by storing the total number of prize balls.
). For example, a number counter corresponding to each prize ball number is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by one. When the payout of each prize ball is completed, the corresponding number counter is decremented by one. Also in this case, each number counter is formed in the backup RAM area. Therefore, even if the power of the gaming machine is turned off, if the power is restored during the predetermined period, the prize ball control CPU 371 can continue the prize ball payout process based on the content of each number counter.

FIG. 26 shows a ball lending control process (step S7).
It is a flowchart which shows 06). In the ball lending control processing, the prize ball control CPU 371 checks whether or not a prize ball is being paid out (step S531). If the prize balls are not being paid out, it is confirmed whether or not the stored number of lending balls is not 0 (step S532). If the lending ball number storage is not 0, the award ball control CPU 371 performs a ball lending process (step S533). In the ball lending process, the payout motor 2
If 89 has not been turned on, it is turned on, and it is checked whether or not a game ball has been paid out based on the detection output of the ball lending count switch 301B. Then, when it is confirmed that one payout has been made (step S534), the value of the stored number of lending balls is decremented by one (step S535). Further, when the value of the number of stored lending balls becomes 0 (step S5).
36), and turns off the payout motor 289 (step S53).
7). In this embodiment, the prize ball and the ball lending are performed by the same payout device.

Next, it is confirmed whether or not there is a ball lending request from the card unit 50 (step S538), and if there is a request, the number corresponding to the requested unit number is added to the value of the lending ball number storage (step S539). .

The contents of the number-of-lending-balls storage are retained by the backup power supply of the power supply board 910 for a predetermined period even if the power of the gaming machine is turned off. Therefore, when the power is restored during the predetermined period, the prize ball controlling CPU 371 can continue the ball lending process based on the content of the lending ball number storage.

Note that the prize ball control CPU 371 manages the number of lent balls requested from the card unit 50 in units (for example, in units of 100 yen) as a total number in the lent ball number storage. Good. For example, a ball lending counter is provided, and when a ball lending request is issued, the ball lending counter is incremented by one. When the payout of the number of units is completed, the ball lending counter is decremented by one. Also in that case, the ball lending counter is formed in the backup RAM area. Therefore, even if the power of the gaming machine is turned off, if the power is restored during the predetermined period, the prize ball controlling CPU 371 can continue the ball lending process based on the content of the ball lending counter.

FIG. 27 shows that the CPU 371 for controlling the prize ball controls the first
7 is a flowchart showing a power failure occurrence interrupt process executed in response to an interrupt from a power monitoring unit. Power supply monitoring IC
When 932 detects a drop in the power supply voltage, the voltage drop signal indicates a voltage drop, and the power failure occurrence interrupt processing is started. In the power failure occurrence interrupt processing, the CPU 37 for controlling the prize ball
1 sets interrupt prohibition (step S801), and sets
An access prohibition state is set (step S802), and a loop process is started. That is, no processing is performed.

Therefore, the power supply monitoring IC shown in FIG.
Before the operation is disabled from the outside by the reset signal from 934, the operation is stopped internally. Thus, the operation of the award ball control CPU 371 is reliably stopped when the power is turned off. As a result, it is possible to reliably prevent the contents of the RAM from being destroyed due to an abnormal operation that may occur as the power supply voltage decreases.

In this embodiment, the power failure occurrence NM
In I processing, the program was looped in the last part,
It may be configured to issue a HALT instruction. If a CPU having a specification that does not cause another interrupt during the interrupt processing is used, the processing in step S801 is unnecessary.

FIG. 28 is a flowchart showing a part of the initialization processing (step S701) executed by the CPU 371 for controlling the prize ball when the power is turned on. When the power is turned on or the power is restored, the CPU 371 for controlling the prize ball
First, it is checked whether the value of the total number storage or the lending ball number storage formed in the backup RAM area is not 0 (step S901). If it is 0,
Since there was no unpaid prize ball when the power was last turned off, normal initialization processing is performed. That is, the register and all RAM areas are cleared (step S903),
Initialize the stack pointer (step S90)
4).

When the value of the storage of the total number or the storage of the number of lending balls is not 0, the address is designated to clear the register and the non-backup RAM area (step S90).
5). Then, setting for restarting the prize ball is performed. For example,
The in-prize ball processing flag is set (step S90).
6). If the backup RAM area is an area irrespective of the number of prize balls, those addresses may be designated and cleared.

As described above, the CPU 371 for controlling the prize ball
When the power is turned on, it is possible to determine whether to perform the normal initial setting process or to restore the state during the prize ball only by checking the data in the backup RAM area. In other words, the prize ball processing can be restarted for the unpaid prize balls by a simple judgment.

Note that the CPU 371 for controlling the prize ball may determine whether or not to perform the initialization processing based on the power-off flag, similarly to the CPU 56 of the main board 31. In addition, the main substrate 31
As in the case of the CPU 56, it is possible to ensure the storage of the stored contents by using a parity check code.

In this embodiment, the prize ball control C
PU 371 is a non-maskable external interrupt terminal (NMI terminal)
, The first voltage drop signal (voltage drop signal from the first power supply monitoring means) is detected, but even if the first voltage drop signal is introduced to the maskable interrupt terminal (IRQ terminal). Good. In that case, the power failure occurrence interrupt processing shown in FIG. 27 is executed by the IRQ processing. Further, the first voltage drop signal may be detected through the input port. In that case, the input port is monitored in the main processing executed by the award ball control CPU 371.

As described above, according to the present invention, the first power supply monitor for generating the first voltage drop signal for starting the power supply stop processing by the electric component control microcomputer mounted on the electric component control board is provided. Means and a second power supply monitoring means for generating a second brownout signal for resetting the electrical component control microcomputer in a final loop portion (or after entering the HALT state) of the power supply stop processing Is provided in the gaming machine, so that the processing at the time of power supply stop is performed reliably, and the data to be stored during the power-off is reliably stored.

In particular, since the first power supply monitoring means and the second power supply monitoring means are installed on the electric component control board,
It is easy to set the detection voltage (voltage at which a voltage drop signal is output) of the first power supply monitoring means and the second power supply monitoring means to a value appropriate for the control means mounted on the electric component control board. It is. For example, if it is desired to shift the power supply stop processing start timing between the game control means on the main board 31 and the award ball control means on the award ball control board 37, the first power supply monitoring means on the main board 31 and the award ball control This can be dealt with by changing the detection voltage of the first power supply monitoring means on the substrate 37, but such a measure can be easily made.

In each of the above embodiments, the first power supply monitoring means and the second power supply monitoring means are separate. However, the first voltage drop signal and the second voltage drop signal described above are generated. If possible, an integrated configuration may be used. For example, as shown in FIG. 29, the first power supply monitoring means and the second power supply monitoring means are realized by a single IC by using a power supply monitoring IC 905 capable of setting two types of detection voltages. can do. Although FIG. 29 illustrates the case of the main board 31, the same IC can be used for other electric component control boards.

Further, in the above embodiment, the first power supply monitoring means and the second power supply monitoring means are provided with an electric component control microcomputer which requires their detection output (voltage drop signal). Although it was mounted on the board, if it was mounted on any of the electrical component control boards, it was mounted on a different electrical component control board from the board on which the electrical component control microcomputer that required the detection output was mounted. Is also good.

FIG. 30 is a block diagram showing an example in which the first power supply monitoring means is mounted on an electric component control board different from the board on which the electric component control microcomputer requiring the detection output is mounted. In this example, the first power supply monitoring circuit 901 mounted on the main board 31 also supplies a detection output to the prize ball control CPU 371 of the prize ball control board 37. In the main board 31, the first power supply monitoring circuit 9
01 is output to the outside of the board via the output buffer 900.

In the award ball control board 37, the detection output from the first power supply monitoring means is supplied to the input buffer circuit 93.
0 is input to the CPU 371 for controlling the prize ball. Here, 74HC is used as the input buffer circuit 930.
Although 244 is exemplified, any circuit may be used as long as the circuit has an input buffer function. The input buffer circuit 930 is an irreversible element that allows a signal to pass only in a direction toward the inside of the award ball control board 37.

Even in the configuration illustrated in FIG. 30, the CPU 56 of the main board 31 and the CPU 371 for controlling the prize ball of the prize ball control board 37 can perform the above-described power supply stoppage processing. , The system is reset in response to the detection output (voltage drop signal) of the second power supply monitoring means.

Here, the case where the first power supply monitoring means is mounted on the main board 31 has been illustrated, but the first power supply monitoring means may be mounted on another electric component control board. . Also, the second power supply monitoring means can be mounted on an electrical component control board different from the board on which the electrical component control microcomputer requiring the detection output is mounted.

The first power supply monitoring circuit 901 shown in FIG. 30 is similar to the power supply monitoring IC 90 shown in FIG.
2 is realized. Second power supply monitoring circuits 903 and 933
Is a power supply monitoring IC 90 as shown in FIGS.
4,934. Note that the initial reset circuit is omitted in FIG.

As described above, when the power supply monitoring means is mounted on an electric component control board different from the board on which the electric component control microcomputer requiring the detection output is mounted, the power supply monitoring means is provided. Can be supplied to a plurality of electric component control means. Therefore, the configuration of the electric component control board can be simplified and cost can be reduced.

In each of the above embodiments, the case where the RAM is used as the storage means has been described. However, if the storage means is an electrically rewritable storage means, the RAM may be used.
Other than these may be used.

Furthermore, here, the prize ball control means has been exemplified as an electric component control means other than the game control means.
The display control unit, the sound control unit, and the lamp control unit may be configured to perform the above-described control.

The pachinko gaming machine 1 of each of the above embodiments
Is a first-class pachinko gaming machine in which a predetermined game value can be given to a player when a stop symbol of a special symbol variably displayed on the variable display portion 9 based on a start winning prize is a predetermined symbol combination. However, if there is a prize in a predetermined area of the electric accessory that is opened based on a winning start, a second-type pachinko gaming machine that can give a predetermined game value to a player, or is variably displayed based on a starting prize. The present invention can be applied to a third-type pachinko gaming machine in which a predetermined right is generated or continued when there is a prize for a predetermined electric accessory which is opened when a symbol combination of a predetermined symbol is released.

Furthermore, not only in pachinko gaming machines, but also in slot machines and the like, when the power is cut off due to a power failure or the like, the data immediately before the power is cut off is stored in a backup RAM or the like, and when the power is restored, control restart processing based on the stored data is performed. The present invention can be applied to such a configuration.

[0174]

As described above, according to the present invention, a gaming machine monitors a voltage drop of a predetermined potential power supply used in the gaming machine and outputs a detection signal when a first detection condition is satisfied. The first power supply monitoring means monitors a voltage drop of the same or different potential power supply as the predetermined potential power supply, and the first power supply monitoring means is set to be satisfied at least after a lapse of a predetermined period from the establishment of the first detection condition. A second power supply monitoring unit that outputs a detection signal when the second detection condition is satisfied, wherein the first power supply monitoring unit and the second power supply monitoring unit are mounted on a board on which the electric component control unit is mounted. The electric component control means performs a predetermined power supply stop process executable within a predetermined period based on the detection signal from the first power supply monitoring means, and performs an input of the detection signal from the second power supply monitoring means. System reset according to Since a configuration is bets, there is an effect that it is possible to reliably store data necessary for the game state recovery. In particular, since the first power supply monitoring means and the second power supply monitoring means are mounted on the board on which the electrical component control means is mounted, the first power supply monitoring means and the second power supply monitoring means are compared with the case where they are mounted on the power supply board, for example. The effect of reducing the noise on the detection outputs of the power supply monitoring means and the second power supply monitoring means can also be expected.

The first power supply monitoring means and the second power supply monitoring means monitor the voltage of the same predetermined potential power supply, and the voltage of the predetermined potential power supply at which the second power supply monitoring means outputs a detection signal is When the first power supply monitoring means is configured to be lower than the voltage at which the detection signal is output, the first power supply monitoring means monitors the same power supply voltage. The predetermined period, which is the difference between the output timing and the timing at which the second voltage monitoring means outputs the voltage drop signal, can be reliably set to a desired value.

In the case where the predetermined potential power supply monitored by the first power supply monitoring means is configured to be a power supply having a higher potential than the element driving power supply on the substrate on which the electric component control means is mounted, The monitoring range can be extended for the voltage required by the electric component control means, and more precise monitoring can be performed.

In the case where the predetermined potential power supply monitored by the first power supply monitoring means is a potential power supply immediately after conversion from AC to DC, the predetermined potential power supply is set to a voltage required by the electric component control means. On the other hand, the monitoring range can be expanded, and more precise monitoring can be performed.

The detection signal from the first power supply monitoring means is input to the interrupt terminal of the microcomputer of the electric component control means, and the microcomputer executes the power supply stop processing based on the input to the interrupt terminal. In this case, the predetermined power supply stop processing can be started without increasing the load on the software.

In the case where the electric component control means includes a storage means capable of holding the contents immediately before the power supply is stopped, the storage means is integrated with the electric component control means, so that the electric component control means is controlled. The cost of the means can be reduced.

When the power supply stop processing is configured to include processing for preventing access to the storage means, the data to be stored is not destroyed when the power is turned off. There is.

The process at the time of power supply stop includes a process of storing check data obtained as a result of an operation related to the storage contents of the storage means in the storage means.
When power is restored, a check based on the check data is performed, and if the check result is normal, control is restarted.If power is restored, check whether the data has been destroyed based on the check data. And the reliability of the stored data can be improved.

If the electric component control means is configured to execute the initialization process if the check result is not normal, it is prevented that the gaming state is restored based on abnormal data. .

The first power supply monitoring means is on a substrate different from the substrate on which the electric component control means requiring the detection signal is mounted, and the electric component control means is connected to the first power supply via an input buffer. In the case where the detection output of the monitoring means is inputted, even when the detection output of the first power supply monitoring means is transmitted between the boards, stabilization of the detection output input to the electric component control means is achieved. Can be achieved.

In the case where the input buffer is an irreversible means capable of transmitting a signal only from the outside to the inside of the board on which the electric component control means is mounted, the input part of the detection signal is an electric component. Since it is always in an input state to the control means, on the side of the board on which the electric component control means is mounted,
The detection output of the first power supply monitoring means can be easily taken in.

When the first power supply monitoring means and the second power supply monitoring means are formed of a single IC, the cost of the electric component control board can be reduced, and as a result, Cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is a front view of the gaming board of the pachinko gaming machine as viewed from the front.

FIG. 3 is a rear view of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a block diagram showing a circuit configuration example of a game control board (main board).

FIG. 5 is a block diagram illustrating a circuit configuration example of a winning ball control board.

[Fig. 6] C for power supply monitoring and power supply backup
FIG. 3 is a block diagram illustrating a configuration example around a PU.

FIG. 7 is a block diagram illustrating a configuration example of a power supply board.

FIG. 8 is a flowchart showing main processing executed by a CPU on a main board.

FIG. 9 is a flowchart showing an initialization process.

FIG. 10 is a flowchart showing a 2 ms timer interrupt process.

FIG. 11 is a flowchart showing a game control process.

FIG. 12 is a flowchart illustrating a power failure occurrence NMI process.

FIG. 13 is an explanatory diagram for describing a backup parity data creation method.

FIG. 14 is an explanatory diagram showing an example of transmission timing of each control command from the main board.

FIG. 15 is a flowchart illustrating an example of a game state restoration process.

FIG. 16 is an explanatory diagram illustrating an example of a control state when the power is restored after a power failure occurs.

FIG. 17 is a block diagram showing an example of a configuration around a CPU for controlling a prize ball for power supply monitoring and power supply backup.

FIG. 18 is an explanatory diagram showing a configuration example of a winning ball control command.

FIG. 19 is an explanatory diagram showing a bit configuration of a winning ball control command.

FIG. 20 is a timing chart showing how the award ball control command data is output.

FIG. 21 is a flowchart showing a main process executed by a winning ball control CPU.

FIG. 22 is a flowchart showing a timer interrupt process of a winning ball control CPU.

FIG. 23 is an explanatory diagram showing one configuration example of a RAM in the winning ball control means.

FIG. 24 is a flowchart showing a command receiving process of the winning ball control CPU.

FIG. 25 is a flowchart showing a prize ball control process.

FIG. 26 is a flowchart showing a power failure generation process executed by the winning ball control CPU.

FIG. 27 is a flowchart showing a ball lending control process.

FIG. 28 is a flowchart illustrating an example of initialization processing of a winning ball control CPU.

FIG. 29 is a block diagram showing another configuration example around a CPU for power supply monitoring and power supply backup.

FIG. 30 is a block diagram showing a mode in which the first power supply monitoring means is mounted on another board.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pachinko gaming machine 31 Main board 37 Prize ball control board 53 Basic circuit 56 CPU 371 Prize ball control CPU 902,904,932,934 Power supply monitoring IC

Claims (12)

[Claims] 1. A game machine in which a player can play a predetermined game. The game machine performs a process for controlling an electric component provided in the game machine. An electrical component control means capable of resuming control based on the held data held in the storage means capable of holding the contents; and a monitor for monitoring a voltage drop of a predetermined potential power supply used in the gaming machine. A first power supply monitoring unit that outputs a detection signal when one detection condition is satisfied, and monitors a voltage drop of a potential power supply that is the same as or different from the predetermined potential power supply, and performs a first detection in the first power supply monitoring unit. A second power supply monitoring unit that outputs a detection signal when a second detection condition set to be satisfied at least after a lapse of a predetermined period from the satisfaction of the condition; The second power supply monitoring means is mounted on a board on which the electric component control means is mounted, and the electric component control means has a predetermined power executable within the predetermined period according to a detection signal from the first power supply monitoring means. A gaming machine which performs a process at the time of supply stop and is reset in response to a detection signal input from the second power supply monitoring means. 2. The first power supply monitoring means and the second power supply monitoring means monitor the voltage of the same predetermined potential power supply, and the second power supply monitoring means outputs a detection signal. 2. The gaming machine according to claim 1, wherein the voltage is lower than a voltage at which the first power supply monitoring means outputs a detection signal. 3. The power supply of claim 1, wherein the predetermined potential power supply monitored by the first power supply monitoring means is a power supply having a higher potential than an element driving power supply on a substrate on which the electric component control means is mounted. Gaming machine. 4. The gaming machine according to claim 3, wherein the predetermined potential power supply monitored by the first power supply monitoring means is a potential power supply immediately after conversion from AC to DC. 5. The electric component control means includes a microcomputer, a detection signal from the first power supply monitoring means is input to an interrupt terminal of the microcomputer, and the microcomputer is configured to input a signal to the interrupt terminal. The gaming machine according to claim 1, wherein the power supply stop processing is executed based on the processing. 6. The gaming machine according to claim 1, wherein the storage means capable of holding the contents immediately before the stop of the power supply is included in the electric component control means. 7. The gaming machine according to claim 1, wherein the process at the time of stopping power supply includes a process of preventing access to the storage unit. 8. The power supply stop processing includes processing for storing check data obtained as a result of an operation related to the storage content of the storage means in the storage means. 8. The gaming machine according to claim 1, wherein a check is performed based on the data, and if the check result is normal, the control is restarted based on the data held in the storage means. 9. The gaming machine according to claim 8, wherein the electric component control means executes an initialization process if the check result is not normal. 10. The first power supply monitoring means is provided on a substrate different from a substrate on which an electric component control means requiring the detection signal is mounted, and the electric component control means is provided via an input buffer. The gaming machine according to claim 1, wherein a detection signal of the first power supply monitoring unit is input. 11. The irreversible input buffer is capable of transmitting a signal only in a direction from an external side to an internal side of a board on which an electric component control unit requiring a detection signal of a first power supply monitoring unit is mounted. The gaming machine according to claim 10, wherein the gaming machine is sexual means. 12. The gaming machine according to claim 1, wherein the first power supply monitoring means and the second power supply monitoring means are constituted by a single IC.