JP3782416B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine or a coin gaming machine in which a game is performed in accordance with a player's operation, and more particularly to a gaming machine in which a game is performed in accordance with a player's operation in a gaming area on a gaming board. .

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Further, a variable display unit capable of changing the display state is provided, and is configured to give a predetermined game value to the player when the display result of the variable display unit becomes a predetermined specific display mode There is.

  The display result of the variable display unit that displays the special symbol is a combination of a specific display mode that is determined in advance. Note that the game value is the right that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous for a player who is likely to win a ball, or the advantageous state for a player. It is to generate.

  When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state in which a hit ball is easy to win. And in each open period, if there is a prize for a predetermined number (for example, 10) of the big prize opening, the big prize opening is closed. And the number of times the special winning opening is opened is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and even if the number of winnings does not reach a predetermined number, the big winning opening is closed when the opening time elapses. If a predetermined condition (for example, winning in the V zone provided in the big prize opening) is not established at the time when the big prize opening is closed, the big hit gaming state is ended.

  In addition, among the combinations of display modes other than the “big hit” combination, the variable display in which the display result has already been derived and displayed at the stage where some of the display results of the plurality of variable display units have not yet been derived and displayed. A state in which the display mode of the part satisfies a display condition that is a combination of specific display modes is referred to as “reach”. Then, if the display result of the identification information variably displayed on the variable display portion does not satisfy the condition of “reach”, it becomes “missing”, and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

  When a game ball wins a winning opening provided on the game board, a predetermined number of prize balls are paid out. Since the progress of the game is controlled by game control means mounted on the main board, the number of winning balls based on winning is determined by the game control means and transmitted to the winning ball control board. Hereinafter, the game control means and other control means may be referred to as game device control means, respectively.

As a prior art document describing a conventional gaming machine, for example, Patent Document 1 is cited. Further, as a document published after the filing date of the present application that is a divisional application (that is, the so-called filing date of the parent application, October 4, 1999), for example, Japanese Patent No. 3354534 is cited.
Japanese Utility Model Publication No. 6-17458

  As described above, the gaming machine is equipped with various game device control means including game control means. Generally, each gaming device control means is constituted by a microcomputer. That is, a program is stored in a ROM or the like, and data temporarily generated for control or data that changes as control proceeds is stored in the RAM. Then, when the power-off state due to a power failure or the like occurs in the gaming machine, the data in the RAM is lost. Therefore, when recovering from a power outage or the like, the player must return to the initial state (for example, the state when the game machine was first turned on at the game store for the first time in the day), which may cause a disadvantage to the player. There is. For example, if a power failure occurs during a jackpot game and the gaming machine returns to the initial state, the player cannot enjoy the benefits based on the jackpot.

  In order to avoid such a situation, when an unexpected power cut such as a power failure occurs, the necessary data is saved in the power backup RAM, and the data saved when the power is restored is restored. Can be resumed. However, if an error occurs in the data stored in the power backup RAM when the power is cut off, an erroneous state restoration process is performed when the power is restored. For example, when the power is restored, a gaming state different from the gaming state when the power is turned off is set, or award ball payout is resumed based on the number of prize balls different from the original number of prize balls. In such a case, an unexpected disadvantage is given to the player.

  Therefore, according to the present invention, in a gaming machine capable of performing the game state return control for returning the game state based on the contents backed up when the power is turned on, it is possible to perform reliable data storage when the power is turned off. An object of the present invention is to provide a gaming machine that can prevent the player from being disadvantaged.

The gaming machine according to the present invention is provided with a variable display section (for example, the variable display section 9) in which a game is played using a game ball and the display state can be changed, and the display result of the variable display section is specified in advance. This is a gaming machine that gives a player a predetermined game value (for example, payout of a game ball) by becoming a display mode (for example, jackpot symbol), and the display result of the variable display unit becomes a specific display mode And a start winning opening (for example, a starting winning opening 14 for starting a change of symbols in the variable display portion by winning a game ball). ), A winning port (for example, start ports 19 and 24) for paying out the winning ball by winning the game ball, and a count switch (for example, the count switch 23) for detecting the winning of the gaming ball to the big winning port And a start port switch (for example, start port switch 17) for detecting the winning of the game ball to the start winning port, and a winning port switch (for example, the winning port switches 19a, 24a) for detecting the winning of the game ball to the winning port. ) And a game control board equipped with a game control microcomputer (e.g., CPU 56) that outputs a payout number instruction command for instructing the number of payout balls when the count switch, start port switch, and winning port switch detect winning. (For example, main board 53), a ball paying device (for example, a ball paying device 97) for paying out a prize ball, and a prize ball control microcomputer (for example, a prize for driving the ball paying device in response to a payout number instruction command) A prize ball control board (for example, prize ball control board 37) equipped with a ball control CPU 371) and a game control microcomputer. Display control board (e.g., a display control board 80) equipped with a microcomputer for display control for controlling the display of the variable display unit based on de the, count switch, starting opening switch and the voltage supplied to the winning port switch (e.g. , + 12V) higher than a predetermined potential power supply (for example, + 30V power supply voltage), and a power supply monitoring circuit (for example, power supply monitoring IC 902) for detecting a voltage drop of the predetermined potential power supply. Is input to the winning ball control microcomputer, and the winning ball control microcomputer stores the total number of payouts instructed by the payout number instruction command and saves the contents even if the power to the gaming machine is cut off. Backup RAM area (for example, the backup RAM area shown in FIG. 26) The total number of payouts stored in the RAM area is added to the payout number specified by the payout number instruction command, and the payout number stored in the backup RAM area each time one payout is completed by driving the ball payout device. The game control microcomputer mounted on the game control board is set in the RAM access prohibited state by subtracting 1 from the total number of values and the detection output from the power supply monitoring circuit is input. When starting to change, output a change start command including information indicating the change time of the symbol, and then output a display result designation command indicating the display result, and stop the change when confirming the symbol change in the variable display section. It is characterized by outputting a command.

According to the first aspect of the present invention, it is possible to prevent erroneous detection of the switch when the power is cut off . In addition, reliable data storage can be performed when the power is turned off, and a disadvantage to the player can be prevented.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. 1 is a front view of the pachinko gaming machine 1 as seen from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the gaming board of the pachinko gaming machine 1 as seen from the back. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine. It can also be applied to image-type gaming machines and slot machines.

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. There is a hitting ball supply tray 3 on the lower surface of the glass door frame 2. Below the hitting ball supply tray 3, there are provided an extra ball receiving tray 4 for storing prize balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing the hitting ball. A game board 6 is detachably attached to the rear side of the glass door frame 2. A game area 7 is provided in front of the game board 6.

  Near the center of the game area 7, there is provided a variable display device 8 including a variable display unit 9 for variably displaying a plurality of types of symbols and a variable display 10 using 7 segment LEDs. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. A passing gate 11 for guiding a hit ball is provided on the side of the variable display device 8. The hit ball that has passed through the passing gate 11 is guided to the start winning opening 14 through the ball outlet 13. In the passage between the passage gate 11 and the ball exit 13, there is a gate switch 12 that detects a hit ball that has passed through the passage gate 11. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 17. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An open / close plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. In this embodiment, the opening / closing plate 20 is a means for opening and closing the special winning opening. Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V zone) is detected by the V count switch 22. A winning ball from the opening / closing plate 20 is detected by the count switch 23. At the bottom of the variable display device 8, a start winning memory display 18 having four display units for displaying the number of winning balls that have entered the start winning opening 14 is provided. In this example, with the upper limit being four, each time there is a start prize, the start prize storage display 18 increases the number of lit display units one by one. Then, each time the variable display of the variable display unit 9 is started, the lit display unit is reduced by one.

  The game board 6 is provided with a plurality of winning openings 19, 24, and winning of the game balls to the winning openings 19, 24 is detected by winning opening switches 19a, 24a. Decorative lamps 25 blinking during the game are provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a hit ball that has not won a prize is provided below. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a game effect LED 28a and game effect lamps 28b and 28c are provided.

  In this example, a prize ball lamp 51 that is lit when the prize ball is paid out is provided in the vicinity of one speaker 27, and a ball break lamp 52 that is lit when the supply ball is cut is provided in the vicinity of the other speaker 27. Is provided. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and enables ball lending by inserting a prepaid card.

  The card unit 50 has a usable indicator lamp 151 indicating whether or not it is in a usable state, and when the remaining amount information recorded in the card has a fraction (a number less than 100 yen), the fraction is indicated as a hitting tray. 3, a fraction display switch 152 for displaying on a frequency display LED provided in the vicinity of 3, a connecting table direction indicator 153 indicating which side of the pachinko gaming machine 1 corresponds to the card unit 50, in the card unit 50 Check the card insertion indicator lamp 154 indicating that a card is inserted, the card insertion slot 155 into which a card as a recording medium is inserted, and the mechanism of the card reader / writer provided on the back of the card insertion slot 155. In some cases, a card unit lock 156 is provided for releasing the card unit 50.

  The hit ball fired from the hit ball launching device enters the game area 7 through the hit ball rail, and then descends the game area 7. When the hit ball is detected by the gate switch 12 through the passing gate 11, the display number of the variable display 10 changes continuously. Further, when the hit ball enters the start winning opening 14 and is detected by the start opening switch 17, the symbol in the variable display portion 9 starts to rotate if the variation of the symbol can be started. If it is not in a state where the change of the symbol can be started, the start winning memory is increased by one.

  The rotation of the image in the variable display unit 9 stops when a certain time has elapsed. If the combination of images at the time of the stop is a combination of jackpot symbols, the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of hit balls wins. When the hit ball enters the specific winning area while the opening / closing plate 20 is opened and is detected by the V count switch 22, a right to continue is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of images in the variable display section 9 at the time of stop is a combination of jackpot symbols with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in a high probability state. Further, when the stop symbol on the variable display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol in the variable display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG.
On the back surface of the variable display device 8, as shown in FIG. 2, a prize ball tank 38 is provided on the top of the mechanism plate 36, and the prize ball is placed from above in a state where the pachinko gaming machine 1 is installed on the gaming machine installation island. It is supplied to the prize ball tank 38. The prize balls in the prize ball tank 38 pass through the guide rod 39 and reach the ball dispensing device.

  The mechanism plate 36 includes a variable display control unit 29 for controlling the variable display unit 9 via the relay board 30, a game control board (main board) 31 covered with a board case 32 and mounted with a game control microcomputer, etc. A relay board 33 for relaying signals between the variable display control unit 29 and the game control board 31, and a prize ball control board 37 on which a prize ball control microcomputer for performing payout control of prizes is mounted. Has been. Further, at the lower part of the mechanism plate 36, a hitting ball launching device 34 that launches a hitting ball into the game area 7 using the rotational force of the motor, game effect lamps / LEDs 28a, 28b, 28c, a prize ball lamp 51, and a ball break lamp A lamp control board 35 for sending a signal to 52 is installed.

  FIG. 3 is a rear view of the game board of the pachinko gaming machine 1 as seen from the back. As shown in FIG. 3, the ball passing through the guide rod 39 passes through the ball break detectors 187a and 187b and reaches the ball dispensing device 97 via the ball supply rods 186a and 186b. The prize balls paid out from the ball payout device 97 are supplied to the hit ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the connection port 45. A surplus ball passage 46 communicating with the surplus ball receiving tray 4 provided on the front surface of the pachinko gaming machine 1 is formed on the side of the communication port 45. A lot of premium balls based on the winnings are paid out and the hitting ball supply tray 3 becomes full. Finally, when the premium balls are paid out after the premium balls reach the contact port 45, the premium balls pass through the surplus ball passage 46 and surplus. It is guided to the ball receiving tray 4. When the prize ball is further paid out, the sensing lever 47 presses the full tank switch 48 and the full tank switch 48 is turned on. In this state, the rotation of the stepping motor in the ball dispensing device 97 is stopped, the operation of the ball dispensing device 97 is stopped, and the driving of the ball striking device 34 is stopped as necessary. In this embodiment, the ball payout device 97 for paying out the game ball by the rotation of the stepping motor is exemplified as the ball payout device for paying out the game ball by driving the electric drive source. A ball dispensing device having a structure for delivering a ball may be used, or a ball dispensing device having a structure in which a stopper is removed by driving of an electric drive source and the game ball is dispensed by its own weight.

  In order to perform prize ball payout control, signals from the prize opening switches 19 a and 24 a, the start opening switch 17 and the V count switch 22 are sent to the main board 31. The CPU 56 of the main board 31 knows that a winning corresponding to six prize ball payout has occurred when the start port switch 17 is turned on. Further, when the count switch 23 is turned on, it is known that a winning corresponding to 15 prize ball payouts has occurred. Then, when the winning opening switch is turned on, it is known that a winning corresponding to ten winning ball payouts has occurred. In this embodiment, for example, a game ball won in the winning opening 24 is detected by a winning opening switch 24 a provided in a winning ball flow path from the winning opening 24 and won in the winning opening 19. Is detected by a winning port switch 19a provided in a winning ball flow path from the winning port 19.

  FIG. 4 is a block diagram illustrating an example of a circuit configuration in the main board 31. 4 also shows a prize ball control board 37, a lamp control board 35, a sound control board 70, a launch control board 91, and a display control board 80. On the main board 31, the basic circuit 53 for controlling the pachinko gaming machine 1 according to the program and the signals from the gate switch 12, the start port switch 17, the V count switch 22, the count switch 23 and the winning port switches 19a and 24a are the basic circuit. 53, a solenoid circuit 59 for driving the solenoid 16 for opening / closing the variable winning ball apparatus 15 and the solenoid 21 for opening / closing the opening / closing plate 20 according to a command from the basic circuit 53, and lighting of the start memory display 18 A lamp / LED circuit 60 that carries out the extinction lamp and drives the variable display 10 using the 7-segment LED and the decorative lamp 25 is mounted.

  Further, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the effective starting information indicating the number of starting winning balls used for starting the image display of the variable display unit 9, and the fact that the probability variation has occurred. An information output circuit 64 is provided for outputting the probability variation information and the like to a host computer such as a hall management computer.

  The basic circuit 53 includes a ROM 54 that stores a game control program and the like, a RAM 55 that is an example of volatile storage means used as a work memory, a CPU 56 that performs a control operation according to a control program, and an I / O port unit 57. Including. In this embodiment, the ROM 54 and RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the RAM 55, and the ROM 54 and the I / O port unit 57 may be externally attached or built-in. The I / O port unit 57 is a terminal capable of inputting and outputting information in the microcomputer.

Further, the main board 31 includes an initial reset circuit 65 for resetting the basic circuit 53 when power is turned on, and an address signal supplied from the basic circuit 53 to decode any I / O port 57. An address decode circuit 67 for outputting a signal for selecting the / O port is provided.
Note that there is also switch information input to the main board 31 from the ball dispensing device 97, but these are omitted in FIG.

  A ball hitting device for hitting and launching a game ball is driven by a drive motor 94 controlled by a circuit on the launch control board 91. Then, the driving force of the drive motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

  FIG. 5 is a block diagram showing an example of the configuration around the CPU 56 for power supply monitoring and power supply backup. As shown in FIG. 5, the voltage drop signal from the first power supply monitoring circuit (first power supply monitoring means) mounted on the power supply board is input to the input port 570 connected to the CPU 56. The first power supply monitoring circuit is a circuit that monitors the voltage of any one of the various DC power supplies used by the gaming machine and detects a power supply voltage drop. Therefore, the CPU 56 can check the power-off state via the input port 570.

  The input port 570 is an output signal of game ball detecting means (in this example, the start port switch 17, the count switch 23, the winning port switches 19a, 24a, etc.) for detecting a game ball provided in the gaming machine. Is input to the empty bit of the input port. That is, the voltage drop signal from the first power supply monitoring circuit provided on the power supply board is input to the input port 570 as detection input means for inputting detection information of the game ball detection means.

  The voltage drop signal from the first power supply monitoring circuit may be connected to the CPU 56 so that information can be transmitted. The input port 570 may be a built-in port of the CPU 56 or an external port. Also good. The input port 570 is also connected to a switch input signal indicating the state of the initialization operation switch installed on the power supply board.

  A second power supply monitoring circuit 903 is mounted on the main board 31. In this example, in the second power supply monitoring circuit 903, the power supply monitoring IC 904 monitors the + 30V power supply voltage, which is the same as the power supply voltage monitored by the first power supply monitoring circuit, and the voltage value falls below a predetermined value. Then, a low level voltage drop signal is generated. For example, the detection voltage of the first power supply monitoring circuit mounted on the power supply board (the voltage that outputs the voltage drop signal) is + 16V, and the detection voltage of the second power supply monitoring circuit 903 is + 8V. In such a configuration, since the same voltage is monitored, the difference between the timing at which the first voltage monitoring circuit outputs the voltage drop signal and the timing at which the second voltage monitoring circuit outputs the voltage drop signal is desired. Can be reliably set in a predetermined period. The desired predetermined period is a period from when the power-off process is started according to the voltage drop signal from the first power supply monitoring circuit until the power-off process is reliably completed.

  The voltage drop signal from the second power supply monitoring circuit 903 is logically summed with the initial reset signal from the initial reset circuit 65 and then input to the reset terminal of the CPU 56. Therefore, when the initial reset signal from the initial reset circuit 65 exhibits a low level, or when the voltage drop signal from the second power supply monitoring circuit 903 exhibits a low level, the CPU 56 Inactive state).

  Note that the reset IC 651 of the initial reset circuit 65 sets the output signal to a high level when the + 5V power supply voltage becomes a predetermined value or more when the gaming machine is turned on and the voltage of the + 5V power supply rises. That is, the initial reset signal is turned off.

  While power is not supplied from the + 5V power source that is the driving power source of the CPU 56 or the like, at least a part of the RAM is backed up by the backup power source supplied from the power supply board, and the contents are preserved even if the power to the gaming machine is cut off. The When the + 5V power supply is restored, a reset signal is issued from the initial reset circuit 65, so that the CPU 56 returns to a normal operation state. At that time, since necessary data is backed up, it is possible to return to the gaming state at the time of the power failure when recovering from the power failure.

  FIG. 6 is a block diagram illustrating a configuration example of the power supply substrate 910. The power supply board 910 is installed independently of control boards for gaming machines such as the main board 31, the display control board 80, the sound control board 70, the lamp control board 35, and the prize ball control board 37, and is used for each gaming machine in the gaming machine. A voltage used by the control board and the mechanical component is generated. In this example, AC24V, DC + 30V, DC + 21V, DC + 12V and DC + 5V are generated. A capacitor 916 serving as a backup power supply is charged from a line of power supply for driving DC + 5V, that is, an IC or the like on each substrate.

  The transformer 911 converts AC voltage from the AC power source into 24V. The AC 24V voltage is output to the connector 915. The rectifier circuit 912 also generates a DC voltage of +30 V from AC 24 V and outputs it to the DC-DC converter 913 and the connector 915. The DC-DC converter 913 generates + 21V, + 12V, and + 5V and outputs them to the connector 915. The connector 915 is connected to, for example, a relay board, and power of a voltage necessary for each gaming machine control board and mechanism parts is supplied from the relay board. Note that a power switch 918 for stopping or starting the power supply to the gaming machine is installed on the input side of the transformer 911.

  The + 5V line from the DC-DC converter 913 branches to form a backup + 5V line. A large-capacitance capacitor 916 is connected between the backup + 5V line and the ground level. Capacitor 916 can hold a storage state with respect to a backup RAM (a RAM that is backed up by power, that is, a volatile storage unit that can be in a storage content holding state) of the gaming machine control board when power supply to the gaming machine is cut off. It becomes a backup power supply that supplies power to Further, a backflow preventing diode 917 is inserted between the + 5V line and the backup + 5V line.

  A battery that can be charged from a + 5V power supply may be used as the backup power supply. In the case of using a battery, a rechargeable battery is used in which the capacity disappears when a state in which no power is supplied from the +5 V power source continues for a predetermined time.

  The power supply board 910 is mounted with a power monitoring IC 902 that constitutes the first power supply circuit described above. The power supply monitoring IC 902 detects the occurrence of power interruption by introducing the + 30V power supply voltage and monitoring the + 30V power supply voltage. Specifically, when the + 30V power supply voltage becomes equal to or lower than a predetermined value (+ 16V in this example), a voltage drop signal is output because the power supply is cut off. The + 30V power supply voltage is a voltage immediately after being converted from AC to DC. The voltage drop signal from the power monitoring IC 902 is supplied to the main board 31, the prize ball control board 37, and the like.

  The predetermined value for the power monitoring IC 902 to detect the power interruption is lower than the normal voltage, but is a voltage that allows the CPU on each gaming device control board to operate for a while. Further, since the power monitoring IC 902 is configured to monitor a voltage that is higher than the voltage for driving the CPU (+5 V in this example) and immediately after being converted from AC to DC, the CPU The monitoring range can be expanded for the required voltage. Therefore, more precise monitoring can be performed. Furthermore, when + 30V is used as the monitoring voltage, since the voltage supplied to the various switches of the gaming machine is + 12V, prevention of erroneous switch-on detection at the moment of power interruption can be expected. That is, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in the level before + 12V created after the creation of + 30V starts to drop. Therefore, when the voltage of the + 12V power supply decreases, the switch output becomes in the on state. However, if the power supply interruption is recognized by monitoring the + 30V power supply voltage that decreases faster than + 12V, the switch output becomes the power It is possible to enter a state of waiting for recovery and not detect switch output.

  Further, since the power monitoring IC 902 is mounted on the power supply board 910 separate from the gaming apparatus control board, a voltage drop signal can be supplied from the first power monitoring circuit to the plurality of gaming apparatus control boards. Even if there are any number of gaming device control boards that require a voltage drop signal, it is only necessary to provide one first power supply monitoring means. Doing so does not increase the cost of the gaming machine.

  An initialization operation switch 919 is mounted on the power supply board 910. A signal indicating the state of the initialization operation switch is input to the main board 31 and its role will be described in detail later. In this embodiment, since the power switch 918 and the initialization operation switch 919 are mounted on the power supply board 910 that is installed independently of the other control boards, the game after replacement in the case of replacement of the game board or the like. Even if the power supply board 910 is used as it is for the board, the power failure processing using the power switch 918 and the initialization operation switch 919 described later can be executed in the replaced game board.

Next, the operation of the gaming machine will be described.
FIG. 7 is a flowchart showing main processing executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main process, the CPU 56 first checks whether or not it is a time of recovery from a power failure (step S1). Whether or not the power failure has been recovered is confirmed by, for example, a power-off flag set in the backup RAM area when the power is turned off. That is, when power is turned on again in a state where the RAM area is backed up, the RAM stores the power-off state, so the power-off flag is accurately stored. If the gaming machine is turned on while the RAM area is not backed up, the contents of the RAM are indeterminate, so the value of the power-off flag is incorrect. Therefore, it can be confirmed whether or not the power failure flag has been restored from the power failure according to the set state of the power-off flag. Even if the power-off flag is set when the gaming machine is turned on when the power is not backed up, it is erroneously assumed that it was at the time of recovery from a power failure by the parity diagnosis described later. It is prevented from being judged.

  If it is during recovery from a power failure, the CPU 56 checks the state of the initialization operation switch 919 via the input port 570 (step S3). In this embodiment, when the initialization operation switch 919 is turned on, its output becomes a low level (see FIG. 6). If the initialization operation switch 919 is on, normal initialization processing is executed (step S2). On the other hand, if the initialization operation switch 919 is in the off state, the CPU 56 executes a power failure recovery process described later (step S4). The initialization operation switch 919 may be set to an on state before the power switch 918 is turned on, or may be pressed simultaneously with the power switch 918. Further, the power switch 918 may be turned on after being pressed. Considering that the power switch 918 is turned on after the power switch 918 is pressed, a delay time may be set before the determination in step S3.

  If it is not time to recover from a power failure, the CPU 56 executes normal initialization processing (steps S1 and S2). Thereafter, in the main process, the process proceeds to a loop process in which the monitoring of the timer interrupt flag (step S6) is confirmed. In the loop, a display random number update process (step S5) is also executed.

  In the normal initialization process, as shown in FIG. 8, after the register and RAM clear process (step S2a) and the necessary initial value setting process (step S2b) are performed, the timer allocation is periodically performed every 2 ms. Initial setting of the timer register provided in the CPU 56 (setting that the time-out is 2 ms and the timer repeatedly operates) is performed so as to cause a delay (step S2c). That is, in step S2c, processing for activating a timer interrupt and processing for setting a timer interrupt interval are executed.

  Therefore, in this embodiment, the internal timer of the CPU 56 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. Then, as shown in FIG. 9, when a timer interrupt occurs, the CPU 56 sets a timer interrupt flag (step S11).

  When detecting that the timer interrupt flag is set in step S6, the CPU 56 resets the timer interrupt flag (step S7) and monitors the voltage abnormality (step S8). The voltage abnormality is monitored by monitoring a voltage drop signal from the power supply monitoring IC 902 via the input port 570. When detecting a voltage abnormality, that is, a drop in the power supply voltage, the CPU 56 executes a power failure generation process (power-off process: step S9) described later.

  When the voltage abnormality is not detected, the CPU 56 executes a game control process (step S9). With the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the game control process is executed in the main process, but the game control process may be executed in the timer interrupt process.

  FIG. 10 is a flowchart showing the game control process. In the game control process, the CPU 56 first performs a process of setting a display control command sent to the display control board 80 in a predetermined area of the RAM 55 (display control data setting process: step S21), and then displays the display control command. An output process is performed (display control data output process: step S22).

  Next, a process of outputting the contents of the storage area for various output data to each output port is performed (data output process: step S23). Also, output data setting processing is performed for setting output data such as jackpot information, start information, probability variation information, etc., output to the hall management computer in the storage area (step S24). Further, various abnormality diagnosis processes are performed by the self-diagnosis function provided in the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S25).

  Next, a process of updating each counter indicating each determination random number such as a big hit determination random number used for game control is performed (step S26).

  Further, the CPU 56 performs special symbol process processing (step S27). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S28). In the normal symbol process, the corresponding process is selected and executed in accordance with the normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Further, the CPU 56 inputs the states of the gate sensor 12, the start port sensor 17, the count sensor 23, and the winning port switches 19a and 24a via the switch circuit 58, and determines whether or not there has been a winning for each winning port or winning device. (Switch processing: step S29). The CPU 56 further performs a process of updating a display random number such as a random number that determines the type of stop symbol (step S30).

  Further, the CPU 56 performs signal processing with the prize ball control board 37 (step S31). That is, when a predetermined condition is satisfied, a prize ball control command is output to the prize ball control board 37. The prize ball control CPU mounted on the prize ball control board 37 drives the ball payout device 97 according to the prize ball control command.

  As described above, the main process includes a process for determining whether or not to shift to the game control process, and the timer control process based on the timer interrupt periodically generated by the internal timer of the CPU 56 is used for the game control process. Since a flag for determining whether or not to shift is set, all the game control processes are executed reliably. In other words, until all the game control processes are executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all the processes in the game control process are completed. ing.

  Conventional general game control processing is forcibly returned to the initial state by an external interrupt that occurs periodically. If it demonstrates in accordance with the example shown by FIG. 10, for example, even if it was during the process of step S31, it was forcibly returned to the process of step S21. In other words, there is a possibility that the next game control process will be started before all the processes in the game control process are completed.

  In this embodiment, the determination of the power supply voltage drop (step S8) is performed before executing the game control process activated by the timer interrupt that occurs periodically, but the game control process is executed. It may be done later. Regardless of the timing, the power supply voltage drop is determined when the game control means is not inputting / outputting information to / from other gaming device control means or gaming devices. The power failure generation process (step S9) is not executed during the operation. That is, information input / output is not interrupted in the middle. For example, a control command sent to another substrate is reliably completed.

  Further, here, the game control process executed by the CPU 56 of the main board 31 is executed according to the flag set in the timer interrupt process based on the timer interrupt that the internal timer of the CPU 56 periodically generates. A hardware circuit that generates a signal periodically (for example, every 2 ms) is provided, a signal from the circuit is introduced into an external interrupt terminal of the CPU 56, and it is determined whether or not to shift to a game control process by the interrupt signal. A flag may be set for this purpose. Even in such a configuration, the determination of the flag is not performed until all of the game control processes are executed, so that it is guaranteed that all the processes in the game control process are completed.

  FIG. 11 is a flowchart illustrating an example of a power failure generation process (step S9). In the power failure generation process, the CPU 56 first sets prohibition of interruption (step S41). In the power failure generation process, a checksum generation process is performed to ensure the storage of the RAM contents. If another interrupt process is performed during the process, the CPU may not be able to operate before the checksum generation process is completed. Settings are made so that no interruption occurs.

  Next, the CPU 56 turns off all output ports (step S42). If necessary, the contents of each register are stored in the backup RAM area (step S43). Further, a power-off flag is set (step S44). Further, an appropriate initial value is set in the backup check data area of the backup RAM area (step S45), the exclusive value is sequentially obtained for the initial value and the data in the backup RAM area (step S46), and the final calculation value is obtained. Is set in the backup parity data area (step S47). Thereafter, the RAM access is prohibited and looped (step S48). When the power supply voltage is lowered, the level of various signal lines may become unstable and the contents of the RAM may be altered, but if the RAM access is prohibited in this manner, the data in the backup RAM will be altered. There is no.

  Note that, as described above, the power-off flag that is set before the RAM access is prohibited is used when determining whether or not to recover from a power failure when the power is turned on. Further, the processing of steps S41 to S48 is completed before the second power supply monitoring unit generates the voltage drop signal. In other words, the detection voltages of the first voltage monitoring means and the second voltage monitoring means are set so that the second power supply monitoring means is completed before generating the voltage drop signal.

  FIG. 12 is a flowchart illustrating an example of a power failure recovery process (step S4). In the power failure recovery process, the CPU 56 first performs data check (parity check in this example) in the backup RAM area (step S51). In the case of recovery after an unexpected power failure, the data in the backup RAM area should have been saved, so the check result is normal. If the check result is not normal, the internal state cannot be returned to the state at the time of power-off, so the initialization process similar to the initialization process (step S2) executed at the time of power-on not at the time of power failure recovery is executed. (Steps S52 and S54).

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state to the state at the time of power-off (step S53) and clears the power-off flag (step S55).

  Here, it is confirmed in step S1 whether or not the recovery from the power failure, and if the recovery from the power failure, the parity check is performed. First, the parity check is performed and the check result is not normal. If it is determined that the power is not recovered from the power failure, the initialization process of step S2 is executed. If the check result is normal, the game state return process may be performed. That is, it may be determined whether or not recovery from a power failure is made based on the result of the parity check.

  FIG. 13 is an explanatory diagram for explaining a backup parity data creation method. However, in the example shown in FIG. 13, for the sake of simplicity, the size of the data in the backup data RAM area is 3 bytes. In the power failure generation process based on the power supply voltage drop, as shown in FIG. 13A, initial data (00H in this example) is set in the backup check data area. Next, an exclusive logical sum of “00H” and “F0H” is taken, and an exclusive logical sum of “16H” is obtained. Further, an exclusive OR of the result and “DFH” is taken. Then, the result (“39H” in this example) is set in the backup parity data area.

  When power is turned on again, parity diagnosis is performed in the power failure recovery process. FIG. 13B is an explanatory diagram illustrating an example of parity diagnosis. If all the data in the backup area is stored as it is, data as shown in FIG. 13A is set in the backup area when the power is turned on again.

  In the processing of step S51, the CPU 56 sequentially performs exclusive OR for each data in the backup data area using the data (in this example, “39H”) set in the backup parity data area in the backup RAM area as initial data. Process. If all the data in the backup area is stored as it is, the final calculation result matches “00H”, that is, the data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final calculation result is not “00H”.

  Therefore, the CPU 56 compares the final calculation result with the data set in the backup check data area, and if they match, the parity diagnosis is normal. If they do not match, the parity diagnosis is abnormal.

  In this embodiment, check data (parity data in this example) is generated in the power failure generation process, but check data is not generated and only the power-off flag is set. Good.

  As described above, in this embodiment, the game control means is provided with a volatile storage means (a backup RAM in this example) that is backed up for a predetermined period of time even when the power of the gaming machine is cut off. Sometimes, the CPU 56 (specifically, a program executed by the CPU 56) is configured to perform a game state recovery process (step S53) for recovering the game state based on the backup data if the volatile storage means is in the backup state. The

  At this time, if the initialization operation switch 919 is in the ON state, the game state restoration process is not executed, and the normal initialization process (step S2) is executed. Accordingly, the game store clerk or the like operates the initialization operation switch 919 when the gaming machine is turned on based on the power switch 918 being turned on, so that the game state restoration process based on the backup data stored in the volatile storage means is performed. Can be selected. Therefore, there is provided a gaming machine that can prevent the player from being disadvantaged even if the power is cut off and can improve the convenience of operating the gaming machine at the gaming store.

  It should be noted that, when the backup data is not stored in the volatile storage means when the power is turned on, the initialization operation switch 919 is in the OFF state even if the backup data is stored in the volatile storage means. The initialization process executed in some cases is also used in the program (see step S2 in FIG. 7). Therefore, even if control for improving convenience in operation at a game store is added, the program capacity does not increase so much.

Hereinafter, the gaming state restoration process will be described.
First, in this embodiment, the display control command, the sound control command, and the lamp control command sent from the CPU 56 of the main board 31 to the display control board 80, the sound control board 70, and the lamp control board 35 will be described. Each control command is determined to be sent according to the game progress in the special symbol process (step S28) in the game control process shown in FIG. 10, and specific data is displayed in the display control data setting process (step S21). Is set and is output by being output from the output port in the display control data output process (step S22).

  FIG. 14A is an explanatory diagram showing an example of the transmission timing of each control command related to symbol variation in the variable display unit 9. In this embodiment, the CPU 56 of the main board 31 sends a change start command to each of the display control board 80, the sound control board 70, and the lamp control board 35 when starting the pattern change. Further, a symbol designating command indicating the determined symbols of the left and right middle symbols is transmitted to the display control board 80.

  When the symbol variation is determined, a variation stop command is sent to each of the display control board 80, the sound control board 70, and the lamp control board 35. Each CPU mounted on the display control board 80, the sound control board 70, and the lamp control board 35 performs display control, sound generation control, and lamp lighting control according to the variation mode specified by the variation start command. The change start command includes information indicating the change time.

  FIG. 14B is an explanatory diagram showing an example of a transmission timing of each control command related to the jackpot game executed when the display result of the variable display unit 9 is a predetermined jackpot symbol. In this embodiment, the CPU 56 of the main board 31 sends a big hit start command to each of the display control board 80, the sound control board 70, and the lamp control board 35 when the big hit game is started. Further, after a predetermined time elapses, a one round (1R) designation command is transmitted. When the CPUs mounted on the display control board 80, the sound control board 70, and the lamp control board 35 receive the jackpot start command, they perform display control, sound generation control, and lamp lighting control at the start of the jackpot. When a one-round designation command is received, display control, sound generation control, and lamp lighting control during a big hit are performed. However, the CPU of the display control board 80 performs the first round display.

  Thereafter, the CPU 56 of the main board 31 sequentially sends commands indicating each round to the display control board 80. The CPU of the display control board 80 performs corresponding display control according to these commands.

  At the end of the big hit game, the CPU 56 of the main board 31 sends a big hit end command to each of the display control board 80, the sound control board 70, and the lamp control board 35. Then, after a predetermined time has elapsed, a normal screen display command is sent out. Each game device control means, when receiving the normal screen display command, sets the control state to a game waiting state.

  FIG. 15 is a flowchart illustrating an example of the gaming state recovery process performed in the power failure recovery process illustrated in FIG. In this example, if it is necessary to restore the register contents, the CPU 56 restores the value stored in the backup RAM to the register (step S61). Then, the gaming state at the time of a power failure is confirmed based on the data stored in the backup RAM. For example, the gaming state can be confirmed by the value of the special symbol process flag corresponding to the progress of the special symbol process.

  If the gaming state is changing in the design (step S62), control is performed to send a change start command to the display control board 80, the sound control board 70, and the lamp control board 35 (step S63). If the gaming state is a big hit game (step S64), control is performed to send the last sent control command to the display control board 80, the sound control board 70, and the lamp control board 35 before the power failure. (Step S65). If the game state is other than that, for example, control is performed to send a normal screen display command to the display control board 80, the sound control board 70, and the lamp control board 35 (step S66). Further, for example, the return of the state of the variable winning ball device 15 in the case of a big hit is automatically performed in the later game control process because the data in the RAM is stored.

  FIG. 16 is an explanatory diagram illustrating an example of a control state when the power is restored after a power failure. In FIG. 16, the variable display state is realized by the CPU (display control means) of the display control board 80, the sound state is realized by the CPU (sound control means) of the sound control board 70, and the lamp state is the lamp control board. This is realized by 35 CPUs (lamp control means).

  FIG. 16A shows an example in the case where the power is restored after a power failure occurs during symbol variation. In this case, when the power is restored, a change start command is sent from the main board 31 (step S63 in FIG. 15). Since the variation start command is a command sent at the start of symbol variation, the states of variable display control, sound control, and lamp control are returned to the state at the beginning of variation. In this embodiment, the change start command includes information for specifying the change time, and after sending the change start command, the CPU 56 of the main board 31 does not send anything until the confirmation command at the end of change (change stop command) ( Except for the designating command). Therefore, if a power failure occurs during symbol fluctuation, fluctuation cannot be resumed from the middle of fluctuation, but display control, sound control, and lamp control are synchronized by retransmitting the fluctuation start command. Return to.

  In the main board 31, various parameters used at the start of the change are stored in the backup RAM. Accordingly, the display result (determined symbol) or the like in the fluctuation after power restoration is the same as the display result or the like that should have been in the fluctuation interrupted by the power failure. Therefore, there is no disadvantage to the player.

  FIG. 16B shows an example in the case of recovery after a power failure occurs during a big hit game. In this case, when power is restored, the command sent from the main board 31 to the display control board 80, the sound control board 70, and the lamp control board 35 at the end before the power failure is re-sent (step S65 in FIG. 15). Therefore, the sound control and the lamp control are returned to the control state during the big hit game. In addition, the display control returns to the state performed at the time of power failure.

  In the main board 31, various parameters during the big hit game (number of times of opening of the big winning opening, number of winning balls of the big winning opening, etc.) are stored in the backup RAM. Therefore, the gaming state for the player also returns to the state before the power failure, so there is no disadvantage to the player.

  In the above embodiment, the case where the power supply monitoring process, the data storage process, and the restoration process are performed in the game control unit has been described. However, a part of the RAM in the voice control unit, the lamp control unit, and the display control unit is also powered The display control means, the sound control means, and the lamp control means that are backed up may also perform the processing as described above. However, the display control means, the sound control means, and the lamp control means do not need to perform command transmission processing at the time of recovery.

  Further, in this embodiment, as shown in FIG. 5, the first power supply monitoring unit is mounted on the power supply board 910, and the second power supply monitoring unit is mounted on the main board 31. When the power supply voltage decreases, the second power supply monitoring means (power supply monitoring IC 904 in this example) generates a voltage drop signal when the first power supply monitoring means (power supply monitoring IC in this example) is generated. IC 902) is set to be later than the time when the voltage drop signal is generated. Further, the voltage drop signal from the second power supply monitoring means is input to the reset terminal of the CPU 56.

  Then, as shown in FIG. 17, the CPU 56 performs a power failure generation process (power shutdown process) based on the voltage drop signal from the first power monitoring means (power monitoring IC 902) and then waits for a power shutdown. However, in the power-off waiting state, the reset state is entered. That is, the operation of the CPU 56 is stopped. In the power supply waiting state, the + 5V power supply voltage value gradually decreases and the input / output state becomes indefinite. However, since the CPU 56 is in the reset state, the abnormal operation based on the indefinite data is prevented.

  As described above, in this embodiment, the CPU 56 executes the power-off process in response to the detection output input from the first power supply monitoring means, and receives the detection output from the second power supply monitoring means. Since the system is reset accordingly, it is possible to reliably store data when the power is turned off, and to prevent a disadvantage from being brought to the player.

  In this embodiment, the power supply monitoring ICs 902 and 904 monitor the same power supply voltage, but may monitor different power supply voltages. For example, as shown in FIG. 18, the first power supply monitoring circuit on the power supply board 910 may monitor the + 30V power supply voltage, and the second power supply monitoring circuit on the main board 31 may monitor the + 5V power supply voltage. Then, the power supply monitoring IC 904 of the main board 31 is delayed so that the timing at which the second power supply monitoring circuit generates the low-level voltage drop signal is later than the timing at which the first power supply monitor circuit generates the voltage drop signal. Threshold level (voltage level for generating a voltage drop signal) is set. For example, the threshold is 4.25V. 4.25 V is lower than the normal voltage, but is a voltage that allows the CPU 56 to operate for a while.

  In the above embodiment, the CPU 56 detects the first voltage drop signal from the power supply board (the voltage drop signal from the first power supply monitoring unit) via the input port 570, but the first voltage The lowered signal may be introduced to a non-maskable interrupt interrupt terminal (NMI terminal) or a maskable external interrupt terminal (IRQ terminal). FIG. 19 shows an example in which the first voltage drop signal is input to the IRQ terminal of the CPU 56. In this case, when the first voltage drop signal indicates a voltage drop, a power failure generation process (see FIG. 11) is executed by an interrupt process (IRQ process). Therefore, steps S7 and S8 (see FIG. 7) are unnecessary in the main process executed by the CPU 56. In this case, the IRQ interrupt mask may be set at the start of the game control process in step S10, and the IRQ interrupt mask may be canceled at the end of the game control process. By doing so, an interrupt is applied before and after the start of the game control process.

  When a power failure generation process is executed in the IRQ process, an interrupt mask is set at the start of a routine for sending out a prize ball control command in the game control program, and the interrupt mask is released when the prize ball control command is sent out. . Therefore, the interrupt process is not started while the prize ball control command sending process is being performed, and the power failure occurrence process is not started even if the first voltage drop signal indicates a voltage drop state. Accordingly, for example, information on the number of winning balls based on a winning that occurred immediately before the occurrence of a power failure is also reliably transferred to the winning ball control board 37.

  FIG. 20 is a block diagram showing a configuration example around the prize ball control CPU 371 for power supply monitoring and power supply backup. As shown in FIG. 20, a voltage drop signal from the first power supply monitoring circuit (first power supply monitoring means) mounted on the power supply board 910 is input to the input port of the prize ball control CPU 371. Therefore, the winning ball control CPU 371 can check the power-off state via the input port.

  While power is not supplied from the + 5V power source that is the driving power source of the prize ball control CPU 371 or the like, at least a part of the built-in RAM of the prize ball control CPU 371 is connected to the backup terminal by the backup power source supplied from the power board The contents are saved even if the power to the gaming machine is cut off. When the +5 V power supply is restored, the reset signal is issued from the initial reset circuit 935, so that the winning ball control CPU 371 returns to the normal operation state. At that time, since necessary data is backed up, it is possible to return to the gaming state at the time of the power failure when recovering from the power failure.

  In the configuration shown in FIG. 20, a second power supply monitoring circuit 933 is mounted on the winning ball control board 37. In this example, in the second power supply monitoring circuit 933, the power supply monitoring IC 934 monitors the + 30V power supply voltage that is equal to the power supply voltage monitored by the first power supply monitoring circuit of the power supply substrate 910, and the voltage value is predetermined. When the value falls below this value, a low level voltage drop signal is generated. In the case where the second power supply monitoring circuit 933 is provided, the detection voltage (voltage that will output a voltage drop signal) of the second power supply monitoring circuit 933 is mounted on the power supply board 910. Lower than the detection voltage of the power monitoring circuit.

  The voltage drop signal from the second power supply monitoring circuit 933 is logically summed with the initial reset signal from the initial reset circuit 935 and then input to the reset terminal of the winning ball control CPU 371. Therefore, the prize ball control CPU 371 has a low level when the initial reset signal from the initial reset circuit 935 is low, or when the voltage drop signal from the second power supply monitoring circuit 933 is low. The reset state (non-operating state) is entered.

  FIG. 21 is an explanatory diagram showing an example of a bit configuration of a prize ball control command transmitted from the main board 31 to the prize ball control board 37. As shown in FIG. 21, the upper 4 bits in one byte are used as a control designating part, and the lower 4 bits are used as an area indicating the number of winning balls.

  As shown in FIG. 22, in the control designation unit, if bits 7, 6, 5, and 4 are “0, 1, 0, 0”, it indicates a payout number designation command, and “0, 1, 0, “1” indicates a payout designation command. The payout number designation command is sent to the winning ball control board 37 as soon as the CPU 56 of the main board 31 detects winning.

  The ball break designation command whose bits 7, 6, 5, and 4 are “1, 0, 0, 0” is transmitted from the main board 31 when it is detected that there is no supply ball. Further, the firing stop designation command in which bits 7, 6, 5, 4 are “1, 0, 0, 1” is issued when the surplus ball receiving tray 4 is full and the full switch 48 is turned on (full state). (When the flag is turned on).

  The prize ball control command is output as data of 1 byte (8 bits: prize ball control commands D7 to D0) from the main board 31 to the prize ball control board 37. The prize ball control commands D7 to D0 are output in positive logic. When prize ball control commands D7 to D0 are output, a negative logic prize ball control INT signal is output.

  In this embodiment, as shown in FIG. 23, when the prize ball control commands D7 to D0 are output from the main board 31, the prize ball control INT signal becomes low level for 5 μs or more. The prize ball control INT signal is connected to the interrupt terminal of the prize ball control CPU 371 on the prize ball control board 37. Therefore, when there is an interruption, the prize ball control CPU 371 can recognize that the prize ball control commands D7 to D0 are sent from the main board 31, and perform a prize ball control command reception process in the interrupt process.

  The command configuration shown in FIG. 21 is an example, and other configurations may be used. For example, the upper and lower order in one byte may be reversed from the configuration shown in FIG.

  FIG. 24 is a flowchart showing main processing of the prize ball control CPU 371. In the main process, the prize ball control CPU 371 first performs an initial value setting process such as clearing the RAM area (step S701). When data is set in the RAM area (backup RAM area) backed up by the power supply of the built-in RAM, the clearing process of those areas is not performed. Thereafter, in this embodiment, the winning ball control CPU 371 proceeds to a loop process for confirming the monitoring of the timer interrupt flag (step S702).

  In the initialization process in step S701, the non-backup RAM area is cleared if the total number storage value to be described later is not zero. Then, settings for restarting the prize ball are made. For example, an in-price ball processing flag is set. Even if it is a backup RAM area, if it is an area not related to the number of winning balls, it may be cleared by designating those addresses. In addition to these processes, the timer register provided in the prize ball control CPU 371 is initialized so that a timer interrupt is periodically generated every 2 ms (the timeout is set to 2 ms and the timer is repeatedly operated). ) Is performed. That is, processing for activating a timer interrupt and processing for setting a timer interrupt interval are executed.

  Therefore, in this embodiment, the internal timer of the winning ball control CPU 371 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. Then, as shown in FIG. 25, when a timer interrupt occurs, the prize ball control CPU 371 sets a timer interrupt flag (step S711).

  When detecting that the timer interrupt flag has been set in step S702, the winning ball control CPU 371 resets the timer interrupt flag (step S703) and monitors the voltage abnormality (step S704). The voltage abnormality is monitored by monitoring a voltage drop signal from the power supply monitoring IC 902 of the power supply board 910 via the input port. When a voltage abnormality, that is, a drop in power supply voltage is detected, the winning ball control CPU 371 executes a power failure generation process (power failure process: step S706), which will be described later.

  If no voltage abnormality is detected, the prize ball control CPU 371 executes prize ball control processing (step S705). With the above control, in this embodiment, the prize ball control process is started every 2 ms.

  FIG. 26 is an explanatory diagram showing a usage example of the RAM built in the prize ball control CPU 371. In this example, the total number storage (for example, 2 bytes) is formed in the backup RAM area. The total number storage stores the total number of payouts instructed from the main board 31 side.

  FIG. 27 is a flowchart showing a prize ball control command reception process by an interrupt process. The prize ball control INT signal from the main board 31 is input to the interrupt terminal of the prize ball control CPU 371. Therefore, when the prize ball control INT signal from the main board 31 is turned on, the prize ball control CPU 371 is interrupted, and the prize ball control command reception process shown in FIG. 27 is started.

  In the prize ball control command reception process, the prize ball control CPU 371 first reads 1-byte data from the input port assigned to the prize ball control command data (step S852). If the read data is a payout number instruction command (step S853), the number specified by the payout number instruction command is added to the total number memory (step S855). Otherwise, a communication end flag is set (step S854). In this example, the communication end flag is a flag indicating that a command other than the payout number instruction command has been received.

  As described above, the prize ball control CPU 371 mounted on the prize ball control board 37 stores the number of prize balls included in the payout number instruction command sent from the CPU 56 of the main board 31 in the backup RAM area (total number memory). Remember.

  FIG. 28 is a flowchart showing a prize ball control process (step S711) activated by a timer interrupt. In the prize ball control process, the prize ball control CPU 371 checks whether the total number memory is not 0 (step S511). If the total number storage is not 0, the prize ball control CPU 371 performs a prize ball payout process (step S512). In the winning ball payout process, if the payout motor 289 is not turned on, it is turned on, and it is confirmed whether or not a game ball has been paid out by the detection output of the winning ball count switch 301A. When it is confirmed that one payout has been made (step S513), the total number storage value is decremented by 1 (step S514). When the total number storage value becomes 0 (step S515), the payout motor 289 is turned off (step S516).

  The contents of the total number storage are saved by the backup power source of the power supply board 910 for a predetermined period even if the gaming machine is turned off. Accordingly, when the power is restored during the predetermined period, the prize ball control CPU 371 can continue the prize ball payout process based on the contents of the total number memory.

  When the power is turned on, the prize ball control CPU 371 can determine whether to perform normal initial setting processing or restore the state in the prize ball simply by checking the data in the backup RAM area. In other words, it is possible to resume the prize ball processing for the unpaid prize balls by simple determination.

  The prize ball control CPU 371 manages the number of prize balls instructed from the main board 31 as a total number in the total number memory, but may manage each prize ball number (for example, 15, 10, or 6). Good. For example, a number counter corresponding to the number of winning balls is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by one. When the prize ball payout for each prize ball number is completed, the corresponding number counter is decremented by one. Also in that case, each number counter is formed in the backup RAM area. Therefore, even if the power of the gaming machine is cut off, if the power is restored during a predetermined period, the prize ball control CPU 371 can continue the prize ball payout process based on the contents of each number counter.

  FIG. 29 is a flowchart showing a power failure generation process executed by the prize ball control CPU 371. When the power monitoring IC 902 on the power supply board 901 detects a drop in the power supply voltage, the voltage drop signal indicates a voltage drop, and a power failure generation process is started. In the power failure generation process, the winning ball control CPU 371 sets the RAM access prohibited state (step S801), and then loops. Therefore, when the voltage drop signal is output from the power monitoring IC 902, the prize ball payout control is not performed.

  FIG. 30 is a flowchart showing a part of the initialization process (step S701) executed by the prize ball control CPU 371 when the power is turned on. When the power is turned on or the power is restored, the prize ball control CPU 371 first checks whether the value of the total number storage formed in the backup RAM area is not 0 (step S901). If it is 0, it means that there was no unpaid prize ball at the time of the previous power-off, so normal initial setting processing is performed. That is, the register and the entire RAM area are cleared (step S903), and the stack pointer is initialized (step S904).

  If the total number storage value is not 0, the address is designated and the register and the non-backup RAM area are cleared (step S905). Then, settings for restarting the prize ball are made. For example, an in-price ball processing flag is set (step S906). Even if it is a backup RAM area, if it is an area not related to the number of winning balls, it may be cleared by designating those addresses.

  Thus, the prize ball control CPU 371 can determine whether to perform normal initial setting processing or restore the state in the prize ball simply by checking the data in the backup RAM area when the power is turned on. In other words, it is possible to resume the prize ball processing for the unpaid prize balls by simple determination.

  In this embodiment, the prize ball control CPU 371 detects the first voltage drop signal from the power supply board (voltage drop signal from the first power supply monitoring means) via the input port. The voltage drop signal may be introduced to a non-maskable interrupt interrupt terminal (NMI terminal) or a maskable external interrupt terminal (IRQ terminal). In that case, the power failure occurrence process shown in FIG. 29 is executed by the NMI process or the IRQ interrupt process. Therefore, in the main process executed by the prize ball control CPU 371, the processes of steps S704 and S706 (see FIG. 24) are unnecessary.

  In the above embodiment, the first voltage drop signal from the power supply board 910 is input to the input ports of the main board 31 and the prize ball control board 37. However, as shown in FIG. A delay circuit 936 may be provided in front of the input port. In such a configuration, the timing at which the CPU 56 of the main board 31 recognizes that the first power supply monitoring unit has detected a voltage drop is the timing at which the prize ball control CPU 371 of the prize ball control board 37 recognizes. Faster than.

  The CPU 56 and the prize ball control CPU 371 perform power-off processing in response to the first voltage drop signal. As illustrated in the timing chart of FIG. 32, the CPU 56 is more than the prize ball control CPU 371. Start the process when the power is turned off as soon as possible. That is, the game control process by the CPU 56 stops earlier than the prize ball control process by the prize ball control CPU 371 stops. Then, the prize ball control command sent during the game control process is surely received by the prize ball control CPU 371 even when the power is cut off. Since the prize ball control CPU 371 stores the number of prize balls based on the received prize ball control command in the backup RAM area, the number of prize balls is retained even during a power failure and processed after the power failure is restored. Therefore, when the delay circuit 936 is provided, the winning ball payout based on the winning detected by the game control means can be more reliably performed. Therefore, it can prevent more effectively that a disadvantage is given to a player.

  Further, the first voltage drop signal may be delayed by software without providing the delay circuit 936. For example, in the main process shown in FIG. 24, when a voltage drop is detected in step S704, a predetermined timer is started. When the timer times out, the power failure generation process in step S706 is started. Until the timer times out, the prize ball control process is executed.

  In the above embodiment, the RAM is used as the volatile storage means. However, as the volatile storage means, a storage means other than the RAM may be used as long as it is an electrically rewritable storage means. Good.

  Further, here, the prize ball control means is exemplified as the game device control means other than the game control means. However, the display control means, the sound control means and the lamp control means are also provided with a second power supply monitoring means. Also good.

  In the pachinko gaming machine 1 according to each of the above-described embodiments, a predetermined game value can be given to a player when a special symbol stop symbol variably displayed on the variable display unit 9 based on the start winning combination is a combination of a predetermined symbol The second type pachinko gaming machine that becomes a predetermined game value can be given to the player when there is a winning in a predetermined area of the electric game that is released based on the start winning Or a third type pachinko gaming machine in which a predetermined right is generated or continued when a winning is given to a predetermined electric accessory that is released when the symbol of the symbol variably displayed based on the start winning is a combination of the predetermined symbols Even so, the present invention can be applied.

It is the front view which looked at the pachinko machine from the front. It is the front view which looked at the game board of the pachinko machine from the front. It is the rear view which looked at the pachinko game machine from the back. It is a block diagram which shows the circuit structural example of a game control board (main board). It is a block diagram which shows one structural example of CPU periphery for a power supply monitoring and a power supply backup. It is a block diagram which shows one structural example of a power supply board. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is a flowchart which shows the initialization process. It is a flowchart which shows a 2 ms timer interruption process. It is a flowchart which shows a game control process. It is a flowchart which shows a power failure generation process. It is a flowchart which shows a power failure recovery process. It is explanatory drawing for demonstrating the backup parity data creation method. It is explanatory drawing which shows the example of transmission timing of each control command from a main board | substrate. It is a flowchart which shows an example of a game state restoration process. It is explanatory drawing which shows an example of the control state at the time of recovering after a power failure generate | occur | produces. It is a timing chart which shows an example of the operation state of CPU based on the output of a voltage monitoring means. It is a block diagram which shows the other structural example of CPU periphery for a power supply monitoring and a power supply backup. It is a block diagram which shows the further another example of a structure around CPU for a power supply monitoring and a power supply backup. It is a block diagram which shows the example of 1 structure around CPU for prize ball control for power supply monitoring and power supply backup. It is explanatory drawing which shows the structural example of a prize ball control command. It is explanatory drawing which shows the bit structure of a prize ball control command. FIG. 10 is a timing chart showing a state of outputting prize ball control command data. It is a flowchart which shows the main process which CPU for prize ball control performs. It is a flowchart which shows the timer interruption process of CPU for prize ball control. It is explanatory drawing which shows the example of 1 structure of RAM in a prize ball control means. It is a flowchart which shows the command reception process of CPU for prize ball control. It is a flowchart which shows a prize ball control process. It is a flowchart which shows the power failure generation process which CPU for prize ball control performs. It is a flowchart which shows an example of the initialization process of CPU for prize ball control. It is a block diagram which shows the other structural example surrounding CPU for prize ball control for power supply monitoring and power supply backup. It is a timing chart showing an example of the relationship between the time when the game control means starts the power failure occurrence process and the time when the prize ball control means starts the power failure occurrence process.

Explanation of symbols

1 Pachinko machine 31 Main board 37 Prize ball control board 53 Basic circuit 56 CPU
371 CPU for prize ball control
570 Input port 902, 904 Power supply monitoring IC
903, 933 Second power supply monitoring circuit 910 Power supply board

Claims (1)

A game is performed using a game ball, and a variable display unit capable of changing a display state is provided, and a display result of the variable display unit becomes a specific display mode determined in advance, and a predetermined game value is played. A gaming machine to give
A prize winning opening that is opened when the display result of the variable display unit is the specific display mode;
A start winning opening for starting symbol variation in the variable display portion by winning a game ball;
A winning opening for paying out award balls by winning game balls,
A count switch for detecting a winning of a game ball to the big winning opening;
A start port switch for detecting a winning of a game ball to the start winning port;
A winning opening switch for detecting winning of a game ball in the winning opening;
A game control board equipped with a game control microcomputer for outputting a payout number instruction command for instructing a payout number of winning balls when the count switch, the start port switch and the winning port switch detect winning;
A ball dispensing device for dispensing a prize ball;
A prize ball control board equipped with a prize ball control microcomputer that drives the ball dispensing device in response to the number-of-payout instruction command;
A display control board equipped with a display control microcomputer that performs display control of the variable display unit based on a command from the game control microcomputer;
A power monitoring circuit that monitors a predetermined potential power source that is higher than a voltage supplied to the count switch, the start port switch, and the winning port switch , and detects a voltage drop of the predetermined potential power source,
The detection output of the power supply monitoring circuit is input to the prize ball controlling microcomputer,
The prize ball controlling microcomputer is:
A total number of payouts instructed by the payout number instruction command is stored, and includes a backup RAM area in which contents are saved even if the power to the gaming machine is cut off,
The backup RAM area is added to the total number of payouts stored in the backup RAM area by adding the payout number instructed by the payout number instruction command and driving the ball payout device to complete one payout. Subtract 1 from the total number of payouts stored by
When the detection output from the power supply monitoring circuit is input, the RAM access prohibited state is set,
The game control microcomputer mounted on the game control board is:
When starting the symbol variation in the variable display unit, a variation start command including information indicating the variation time of the symbol is output, a display result designation command indicating the display result is further output, and the symbol variation in the variable display unit is output. A gaming machine that outputs a variable stop command when it is confirmed.

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