JP2001046595A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to save necessary data when unexpected power interruption like power stoppage and to reopen the game from the state of power interruption when power is restored, and together not to give rise to deviation in the control timing with control means in each control substrate when the game is reopened. SOLUTION: When power supply to a game machine is reopened, a CPU mounted on a game control substrate sends the initial-state recovery request command set at a state table for recovery to each substrate. After a prescribed time elapsed, values of a special pattern process flags are read out by referring to the data (address of the special pattern process flags) stored in set region of the special pattern process flags that has been set, on the state table for recovery, and the game state is made to return to the state shown by the value. And the game-state recovery request command that has been set in the state table for recovery is sent to each substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine such as a pachinko gaming machine, and more particularly to a game machine in which a game medium is shot by a player's operation and the game medium wins a prize area provided in the game area. A predetermined value is given to the player, and a special game is performed by the entry of the game medium into the specific winning section, and the predetermined game value is given to the player based on the result of the special game being in a predetermined mode. The present invention relates to a gaming machine that can be provided.

[0002]

2. Description of the Related Art As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of prize balls are obtained. Are paid out to players.
Furthermore, a variable display unit capable of changing the display state is provided,
There is a configuration in which a predetermined game value is provided to a player when a display result of the variable display unit has a predetermined specific display mode.

[0003] When the display result of the variable display section for displaying a special symbol is a combination of a predetermined specific display mode, it is usually called a "big hit". In addition, the game value is a right to make the state of the variable prize ball device provided in the game area of the gaming machine advantageous for a player who is easy to win a hit ball, or a right for the player to be in an advantageous state. Or to generate.

[0004] When a big hit occurs, for example, a big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state in which a hit ball is easy to win. Then, in each open period, when a predetermined number (for example, 10) of winning prizes is won, the winning prize opening is closed. The number of opening of the special winning opening is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. If the predetermined condition (for example, winning in the V zone provided in the special winning opening) is not satisfied at the time when the special winning opening is closed, the big hit gaming state ends.

[0005] In addition, among the combinations of display modes other than the "big hit" combination, at a stage where some of the display results of the plurality of variable display portions have not been derived and displayed yet, the display results have already been derived and displayed. The state in which the display mode of the variable display unit that satisfies the display condition that is a combination of the specific display modes is called “reach”. If the display result of the identification information variably displayed on the variable display unit does not satisfy the condition of “reach”, the result is “out” and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

The progress of the game in the gaming machine is controlled by game control means such as a microcomputer. The identification information, the character image, and the background image displayed on the variable display device are controlled by display control means operating according to display control command data from the game control means.
The identification information, the character image, and the background image displayed on the variable display device generally include a display control microcomputer and a video display processor (FIG. 1) that generates image data in accordance with instructions from the microcomputer and transfers the image data to the variable display device side. VDP), and the display control microcomputer has a large program capacity.

Therefore, the microcomputer of the game control means, which has a limited program capacity, cannot control the identification information and the like displayed on the variable display device, and is different from the microcomputer of the game control means for display control. A microcomputer (display control means) is used. Therefore, the game control means for controlling the progress of the game needs to transmit a command for display control to the display control means.

In such a gaming machine, a speaker is provided on the game board, and various sound effects are emitted from the speaker as the game progresses in order to enhance the game effect. Further, a light emitting body such as a lamp or an LED is provided on the game board, and these light emitting bodies are turned on or off as the game progresses in order to enhance the game effect. Generally, sound control for generating sound effects is performed by game control means for controlling the progress of a game. In addition, the lighting / extinguishing control of the luminous body is performed by a game control means for controlling the progress of the game. Then, different types of gaming machines have different ways of generating sound effects, and the patterns of turning on / off the lamps and LEDs are different, so the configuration of the game control means must be changed accordingly. Therefore, if the model is different, it is necessary to redesign the game control means, and there is a problem that the design cost increases.

In order to avoid such a problem, a voice control board equipped with voice control means is provided separately from the game control means, or a luminous body control board mounted with luminous body control means is provided separately from the game control means. Or a control command may be sent from the game control means to the voice control means or the illuminant control means in accordance with the progress of the game. According to such a configuration, different models can be supported by changing the interpretation of the control command by the voice control unit or the illuminant control unit. A similar configuration can be adopted when a control command is transmitted to each control board other than the voice control board and the illuminant control board and on which a control microprocessor (control means) is mounted. A change in the interpretation of the control command in each control means can be easily handled by a software change.

[0010] In addition, a player generally borrows a game medium through a game machine. In that case, a gaming medium lending mechanism is provided in the gaming machine. The game media lending mechanism is often shared with a payout mechanism for paying out prize balls. Since the game media lending mechanism and the prize ball payout mechanism are both common or separately provided, they both perform an operation of paying out game media. It is controlled by prize ball control means mounted on the substrate.

Since the progress of the game is controlled by the game control means mounted on the main board, the number of prize balls based on the winning is determined by the game control means and transmitted to the prize ball control board. On the other hand, since the lending of the game medium is not related to the progress of the game, it is generally controlled by the prize ball control means without passing through the game control means.

[0012]

As described above, the gaming machine is equipped with various control means in addition to the game control means. Generally, each control means is constituted by a microcomputer. That is, a program is stored in a ROM or the like, and data that temporarily occurs in control or data that changes as the control progresses is stored in the RAM. Then, when a power-off state occurs due to a power failure or the like in the gaming machine, data in the RAM is lost. Therefore, at the time of recovery from a power failure or the like, the player must return to the initial state (for example, a state in which the power of the gaming machine is first turned on at the game store for the first time), which may cause disadvantage to the player. There is.
For example, if a power failure occurs during a jackpot game and the gaming machine returns to the initial state, the player will not be able to enjoy the benefits based on the occurrence of the jackpot.

To avoid such a situation, necessary data is stored in a power supply backup RAM when an unexpected power failure such as a power failure occurs, and data stored when the power is restored is restored. And then resume the game. However, as described above, the game control is executed by the game control means mounted on the main board, but various game control devices provided on the gaming machine are provided on other control boards different from the main board. It is controlled by each mounted control means. Since the rise of each control means at the time of power restoration generally varies, there is a possibility that the control by the control means on each control board may be inconsistent at the time of power restoration.

Therefore, according to the present invention, when an unexpected power failure such as a power failure occurs, necessary data can be saved and the game can be resumed from the state at the time of the power failure when the power is restored. It is an object of the present invention to provide a gaming machine in which the control timing of the control means does not shift.

[0015]

A gaming machine according to the present invention comprises:
Perform special games by winning game media in the special prize section,
A gaming machine which can be controlled to a gaming state advantageous to a player based on a result of a special game being in a predetermined mode,
A game control board equipped with game control means for controlling the progress of the game, a game machine control board equipped with a game machine control means for controlling a game machine provided for the game, and Power supply monitoring means for monitoring a power supply voltage drop and outputting a signal to at least one of the game control means and the game device control means when a predetermined amount of voltage drop is detected; The received game control means and game device control means execute power-off processing including processing for storing data in a backup RAM capable of retaining data even when power is turned off, in accordance with the signal,
The game control means has a return data table in which data for returning the game state to the state before power-off is set, and the game state is returned to the state before the power-off using the return data table when the power is restored. It is characterized by returning.

The gaming machine includes a plurality of variable display portions whose display states can be changed, and starts changing the identification information displayed on each of the variable display portions in response to satisfaction of a condition for starting the change. Can be controlled to a game state advantageous to the player on condition that the display result of the predetermined display mode becomes a predetermined display mode, and the game control means determines that the game state at the time of power-off is changing identification information. In such a case, the game state may be returned to the state at the start of the change of the identification information when the power is restored.

Here, it is preferable that the return data table stores data that can be converted from a game state in which the identification information is changing to a game state at the start of the change of the identification information.

The gaming machine control means for controlling the display of the variable display section, if the display state of the variable display section when the power is turned off is changing the identification information, resets the display state to the initial state when the power is restored. Back, and then may be configured to start changing the identification information.

The game control means returns the game state to the state when the power is turned off when the power is restored, and controls the display of the variable display section when the game state when the power is turned off is changing identification information. An error command is sent to the device control means using the data in the return data table, and the game device control means displays an error during the variable display period when the error command is received. It may be.

When the game state at the time of power-off is fluctuating identification information, the game control means sends the return data to the game-apparatus control means for controlling the display of the variable display unit when the power is restored. A command indicating the display result of the identification information is transmitted using the data in the table, and the gaming machine control means does not resume the change in the variable display unit in response to the reception of the command indicating the display result of the identification information, and transmits the identification information. The display result may be configured to be displayed.

The restoration data table is stored when power is restored.
The command sent to each of the plurality of gaming machine control means may be stored in a recognizable manner.

The game control means is configured to return to the state when the power is restored, when the gaming state at the time of power-off is a big hit game and the special winning opening is being opened. Is also good.

[0023]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of the pachinko gaming machine 1 as viewed from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the pachinko gaming machine 1 as viewed from the back. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine.

As shown in FIG. 1, the pachinko gaming machine 1
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing prize balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, a variable display section 9 for variably displaying a plurality of types of symbols and a 7-segment L
A variable display device 8 including a variable display 10 using an ED is provided. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In a passage between the passage gate 11 and the ball outlet 13, there is a gate switch 12 for detecting a hit ball that has passed through the passage gate 11. In addition, the winning ball that entered the starting winning port 14 is
It is guided to the back of the game board 6 and is detected by the starting port switch 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16.

An opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state) is provided below the variable winning ball device 15. In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. The winning ball that enters one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V count switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. Variable display device 8
A start winning prize storage display 18 having four display sections for displaying the number of winning balls entering the starting winning prize port 14 is provided below. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The game board 6 is provided with a plurality of winning ports 19 and 24. Decorative lamps 25 are provided around the left and right sides of the game area 7 so as to blink during the game.
There is an out port 26 for absorbing a hit ball that does not win. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. A game effect LED 28a and a game effect lamp 2
8b and 28c are provided.

In this example, one of the speakers 27
Is provided with a prize ball lamp 51 which is lit when a prize ball is paid out, and a ball out lamp 52 which is lit when a supply ball is out is provided near the other speaker 27. Further, FIG. 1 also shows a card unit 50 which is installed adjacent to the pachinko gaming table 1 and enables lending of a ball by inserting a prepaid card.

On the front of the game board 6, a notification LED is provided.
41 are provided. The notification LED 41 is used for the gaming machine 1
This is for notifying a player or the like that the one-chip microcomputer or the like mounted on the game control board is backed up by the backup power supply.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card is ready for use. If there is a fraction (less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter, the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passage gate 11, the display number of the variable display 10 is changed continuously. Further, when a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17, the symbol in the variable display section 9 starts rotating if the symbol can be changed. If it is not possible to start changing the symbol, the start winning memory is increased by one.

The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the specific winning area while the opening and closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols with probability fluctuation, the probability of the next big hit becomes high. That is, a high probability state, which is more advantageous for the player, is obtained. Also, when the stop symbol on the variable display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the variable display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. On the back of the variable display device 8, as shown in FIG. 2, a prize ball tank 38 is provided above the mechanism plate 36, and when the pachinko gaming machine 1 is installed on the gaming machine installation island, a prize ball is provided from above. Premium ball tank 3
8 is supplied. The prize ball in the prize ball tank 38 reaches the ball payout device through the guide gutter 39.

On the mechanism plate 36, a variable display control unit 29 for controlling the variable display section 9 via the relay board 30, and a game control board (main board) covered with a board case 32 and mounted with a game control microcomputer and the like. ) 31, a relay board 33 for relaying a signal between the variable display control unit 29 and the game control board 31, and a prize ball control board on which a prize ball control microcomputer for controlling the payout of prize balls is mounted. 37 are installed. Further, a ball is hit on the lower part of the mechanism plate 36 by using the rotating force of the motor in the game area 7.
Ball launching device 34 that launches on a game effect lamp / LE
D28a, 28b, 28c, a prize ball lamp 51 and a lamp control board 35 for sending signals to the ball out lamp 52 are provided.

FIG. 3 is a rear view of the gaming board of the pachinko gaming machine 1 as viewed from the rear. The ball that passed through the induction gutter 39
As shown in FIG. 3, the ball cut detectors 187a, 187
b, and reaches the ball dispensing device 97 via the ball supply gutters 186a and 186b. The prize ball paid out from the ball payout device 97 is supplied to the hit ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the communication port 45. On the side of the communication port 45, an excess ball passage 46 communicating with the excess ball tray 4 provided on the front of the pachinko gaming machine 1 is formed. A large number of prize balls based on the prize are paid out, and the ball supply tray 3 becomes full. Finally, after the prize balls reach the communication port 45, further prize balls are paid out. It is led to the ball tray 4. When the prize ball is further paid out, the sensing lever 47 is set to the full switch 4.
By pressing 8, the full tank switch 48 is turned on. In this state, the rotation of the stepping motor in the ball discharging device 97 stops, the operation of the ball discharging device 97 stops, and the driving of the hitting ball firing device 34 also stops as necessary.

Signals from a winning ball detection switch (not shown), a starting port switch 17 and a V count switch 22 are sent to the main board 31 in order to control the winning ball payout. The winning is detected by the winning ball detection switch. When the ON signal of the winning ball detection switch is sent to the main board 31, a winning ball control command is sent from the main board 31 to the winning ball control board 37. For example, when the winning ball detection switch is turned on in response to the turning on of the starting port switch 17, a winning ball control command indicating the number of winning balls “6” is output, and in response to the turning on of the count switch 23 or the V count switch 22, When the winning ball detection switch is turned on, the number of winning balls is “1”.
A prize ball control command indicating "5" is output. When the winning ball detection switch is turned on when these switches are not turned on, a winning ball control command indicating the number of winning balls "10" is output.

FIG. 4 is a block diagram showing an example of a circuit configuration of the main board 31. As shown in FIG. FIG. 4 also shows the prize ball control board 37, the lamp control board 35, the sound control board 70, the emission control board 91, and the display control board 80. On the main board 31, a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 12,
A switch circuit 58 that supplies signals from the starting port switch 17, the V count switch 22, the count switch 23, and the winning ball detection switch 99 to the basic circuit 53, a solenoid 16 that opens and closes the variable winning ball device 15, and the opening and closing plate 2.
A solenoid circuit 59 for driving the solenoid 21 for opening and closing the 0 according to a command from the basic circuit 53;
It includes a lamp / LED circuit 60 for driving the variable display 10 by ED and the decorative lamp 25.

Further, a notification LED 41 is connected via a buffer circuit 42. The notification LED 41 is C
It is connected to an output port built in PU56. The notification LED 41 is supplied with power from a backup power supply.

Also, according to the data supplied from the basic circuit 53, jackpot information indicating occurrence of a jackpot, effective start information indicating the number of start winning balls used to start image display of the variable display section 9, and probability fluctuation have occurred. And an information output circuit 64 that outputs probability change information or the like indicating the fact to a host computer such as a hall management computer.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 used as a work memory, a CPU 56 for performing a control operation according to the control program, and an I / O port unit 57. In this embodiment, the ROM 54 and the RAM 55 are
6 is built in. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to include at least the RAM 55, and the ROM 54 and the I / O port unit 57 may be externally provided.

Further, the main board 31 has an initial reset circuit 65 for resetting the basic circuit 53 when the power is turned on.
A periodic reset circuit 66 for periodically (eg, every 2 ms) giving a reset pulse to the basic circuit 53 to re-execute the game control program from the beginning, and decode an address signal given from the basic circuit 53. I
Address decode circuit 67 for outputting a signal for selecting any I / O port in I / O port unit 57
Are provided. In addition, there is also switch information input to the main board 31 from the ball dispensing device 97, but these are omitted in FIG.

A hit ball firing device that hits and fires a game ball is driven by a drive motor 94 controlled by a circuit on a firing control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

FIG. 5 shows the circuit configuration in the display control board 80 by using the CRT 82 as an example of the variable display section 9 and the output ports (ports A and B) 571 and 572 of the main board 31.
FIG. 9 is a block diagram shown together with an output buffer circuit 63. The output port 571 outputs 8-bit data, and the output port 572 outputs a 1-bit strobe signal (INT signal).

The display control CPU 101 controls the control data R
It operates according to the program stored in the OM 102, and receives a display control command via the input buffer circuit 105 when a strobe signal is input from the main board 31 via the noise filter 107 and the input buffer circuit 105. As the input buffer circuit 105, for example, a general-purpose IC
74HC244 can be used. In addition,
When the display control CPU 101 does not include an I / O port, the input buffer circuit 105 and the display control CP
An I / O port is provided between U101.

Then, the display control CPU 101 controls display of a screen displayed on the CRT 82 in accordance with the received display control command. Specifically, a command corresponding to the display control command is given to the VDP 103. VDP103
Reads necessary data from the character ROM 86. The VDP 103 generates a CRT 8 according to the input data.
2 is generated, and the image data is stored in the VRAM 87. Then, the image data in the VRAM 87 is converted into R, G, B signals, converted into analog signals by the DA converter 104, and output to the CRT 82.

FIG. 5 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, an animal, or an image composed of characters, graphics, or symbols displayed on the CRT 82. In this embodiment, the display control C
PU 101 is a one-chip microcomputer,
At least a RAM is built-in.

The input buffer circuit 105 can pass a signal only in the direction from the main board 31 to the display control board 80. Therefore, there is no room for a signal to be transmitted from the display control board 80 side to the main board 31 side. Display control board 80
Even if the internal circuits are modified illegally, the signal output by the illegal modification is not transmitted to the main board 31 side. The outputs of the output ports 571 and 572 may be output to the display control board 80 as they are. However, by providing the output buffer circuit 63 capable of transmitting a signal in only one direction, the output from the main board 31 to the display control board 80 is provided. One-way signal transmission can be further ensured. Further, for example, a three-terminal capacitor or a ferrite bead is used as the noise filter 107 that cuts off a high-frequency signal. However, even if noise is present between display control commands between substrates due to the presence of the noise filter 107, the effect is eliminated. Is done.

FIG. 6 is a block diagram showing an example of the configuration of the voice control command signal transmitting portion of the main board 31 and the voice control board 70. In this embodiment, according to the progress of the game, the voice control command for instructing the voice output of the speaker 27 provided outside the game area 7 is:
It is output from the main board 31 to the voice control board 70.

As shown in FIG. 6, the voice control command is
The data is output from output ports (output ports C and D) 573 and 574 of the I / O port unit 57 in the basic circuit 53.
8-bit data is output from the output port 573,
A 1-bit strobe signal (I
NT signal) is output. In the voice control board 70,
Each signal from the main board 31 is input to the audio control CPU 701 via the input buffer circuit 705. When the audio control CPU 701 does not include an I / O port, the input buffer circuit 705 and the audio control CPU 7
01, an I / O port is provided. In this embodiment, the voice control CPU 701 is a one-chip microcomputer and has at least a RAM.

The voice synthesizing circuit 702 using, for example, a digital signal processor is
The sound and the sound effect corresponding to the instruction 01 are generated and output to the volume switching circuit 703. The volume switching circuit 703 sets the output level of the voice control CPU 701 to a level corresponding to the set volume and outputs the output level to the volume amplification circuit 704. The volume amplification circuit 704 outputs the amplified audio signal to the speaker 27.

As the input buffer circuit 705, for example,
74HC244 which is a general-purpose CMOS-IC is used. A low level (GND level) is always applied to the enable terminal of the 74HC244. Therefore, the output level of each buffer is the input level, that is, the main board 31.
Signal level has been determined. Therefore, there is no room for a signal to be transmitted from the voice control board 70 side to the main board 31 side.
Therefore, even if the circuit in the voice control board 70 is tampered with, the signal output by the tampering is transmitted to the main board 31.
It does not reach the side. Note that the input buffer circuit 705
, A noise filter may be provided on the input side.

In the main board 31, the output port 5
A buffer circuit 67 is provided outside of 74 and 575. As the buffer circuit 67, for example, a general-purpose CMOS
-74HC244 which is IC is used. The enable terminal is always given a low level (GND level). According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be supplied from the voice control board 70 to the main board 31 is more reliably eliminated. be able to.

FIG. 7 is a block diagram showing a signal transmitting / receiving portion in the main board 31 and the lamp control board 35.
In this embodiment, a game effect LED 28a and a game effect lamp 28b provided outside the game area 7 are provided.
A lamp control command indicating ON / OFF of 28c and ON / OFF of the award ball lamp 51 and the ball out lamp 52 is output.

As shown in FIG. 7, the lamp control command relating to the lamp control is output from the output ports (output ports E, F) 575, 5 of the I / O port unit 57 in the basic circuit 53.
76. The output port 575 outputs 8-bit data, and the output port 576 outputs a 1-bit strobe signal (INT signal). Lamp control board 35
In, the control command from the main board 31 is input to the lamp control CPU 351 via the input buffer circuit 355. When the lamp control CPU 351 does not include an I / O port, the input buffer circuit 355
An I / O port is provided between the CPU and the lamp control CPU 351. In this embodiment, the lamp control CPU 351 is a one-chip microcomputer and has at least a RAM.

In the lamp control board 35, the CPU 351 for lamp control includes a game effect LED 28a and a game effect lamp 28 defined in accordance with each control command.
b, 28c, the game effect L
A light-on / light-off signal is output to the ED 28a and the game effect lamps 28b and 28c. The light-on / light-off signal is output from the game effect LED 28a and the game effect lamps 28b and 28c.
Is output to The light-on / light-off pattern is stored in a built-in ROM or an external ROM of the lamp control CPU 351.

On the main board 31, the CPU 56 outputs a control command for instructing lighting of a prize ball lamp at the time of a prize ball,
When a ball-out detection sensor installed on the game ball supply path on the back of the game board is turned on, a control command for instructing the ball-out lamp to be turned on is output. In the lamp control board 35, each control command is input to the lamp control CPU 351 via the input buffer circuit 355. Lamp control CPU3
51 is a prize ball lamp 5 according to those control commands.
1 and the ball out lamp 52 are turned on / off.

As the input buffer circuit 355, for example,
74HC244 which is a general-purpose CMOS-IC is used. A low level (GND level) is always applied to the enable terminal of the 74HC244. Therefore, the output level of each buffer is the input level, that is, the main board 31.
Signal level has been determined. Therefore, there is no room for a signal to be transmitted from the lamp control board 35 side to the main board 31 side. For example, even if a circuit in the lamp control board 35 is tampered with, a signal output by the tampering is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuit 355.

In the configuration shown in FIG. 7, a signal line to which a signal may be given from the lamp control board 35 to the main board 31 can be eliminated. That is, the unidirectionality of the signal from the main board 31 to the lamp control board 35 is ensured, and the possibility that the lamp control board 35 influences the game control on the main board 31 is eliminated. As a result, even if, for example, the lamp control board 35 is modified so as to give an illegal signal for causing a big hit to the basic circuit 53 of the main board 31, the illegal signal cannot be transmitted to the main board 31.

Further, on the main board 31, a buffer circuit 62 is provided outside the output ports 575, 576. As the buffer circuit 62, for example, a general-purpose CMO
74HC244 which is S-IC is used. The enable terminal is always given a low level (GND level). According to such a configuration, the main substrate 31 is externally provided.
Is prevented from being input to the main board 31, so that a signal line to which a signal may be given from the lamp control board 35 to the main board 31 can be more reliably eliminated.

In FIG. 7, the CPU 35 for lamp control is used.
Signals for instructing the game effect LED 28a, the game effect lamps 28b and 28c, the prize ball lamp 51 and the ball out lamp 52 to be turned on or off are output from the internal output port 1 in practice. -A driver circuit is inserted between the LED and the LED.

FIG. 8 is a block diagram showing components related to the prize ball, such as the components of the prize ball control board 37 and the ball payout device 97. As shown in FIG. 8, the detection signals from the winning ball detection switch 99 and the full tank switch 48 are:
The signal is input to the I / O port 57 of the main board 31 via the relay board 71. The prize ball discharge solenoid 127 drives a ball stop member provided in the middle of the prize ball flow path on the back of the game board. The prize ball detection switch is provided when the prize ball is stopped on the ball stop member. A winning ball is detected by 99. In addition, the full tank switch 48 is used to
Is a switch that detects when the tank is full.

The detection signals from the cut-out ball detection switch 167 and the cut-out switch 187 (187a, 187b) are transmitted to the main board 3 via the relay board 72 and the relay board 71.
1 is input to the I / O port 57. The out-of-ball detection switch 167 is a switch for detecting a shortage of replenishment balls in the prize ball tank 38, and the out-of-ball switch 187 is a switch for detecting the presence or absence of a prize ball in the prize ball passage.

The CPU 56 of the main board 31 indicates that the detection signal from the ball out detection switch 167 or the ball out switch 187 indicates that the ball is out, or that the detection signal from the full switch 48 indicates the full state. , A prize ball control command instructing ball lending is sent. When receiving the award ball control command instructing the ball lending prohibition, the award ball control CPU 371 of the award ball control board 37 stops the ball lending process.

Further, a detection signal from the award ball count switch 301A is also input to the I / O port 57 of the main board 31 via the relay board 72 and the relay board 71. A drive signal from the I / O port 57 of the main board 31 to the winning ball discharging solenoid 127 is supplied to the winning ball discharging solenoid 127 via the relay board 71. The prize ball count switch 301A is provided in the prize ball mechanism portion of the ball payout device 97, and detects an actually paid prize ball.

When there is a prize, the output ports (ports G, H) 577, 578 of the main board 31 are provided on the prize ball control board 37.
, A prize ball control command indicating the number of prize balls is input. The output port 577 outputs 8-bit data, and the output port 578 outputs a 1-bit strobe signal (INT signal). The award ball control command indicating the number of award balls is input to the I / O port 372a via the input buffer circuit 373. The CPU 371 for controlling the prize ball includes an I / O port 37.
A prize ball control command is input via 2a, and the ball payout device 97 is driven according to the prize ball control command to perform a prize ball payout. In this embodiment, the CPU 37 for controlling the prize ball
Reference numeral 1 denotes a one-chip microcomputer having at least a RAM.

Each buffer in the input buffer circuit 373 can pass a signal only in a direction from the main board 31 to the prize ball control board 37. Therefore, there is no room for a signal to be transmitted from the award ball control board 37 side to the main board 31 side. Even if the circuit in the prize ball control board 37 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuit 373.

On the main board 31, a buffer circuit 68 is provided outside the output ports 577 and 578 for outputting award ball control commands. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be given from the prize ball control board 37 to the main board 31 is more reliably formed. Can be eliminated.

The prize ball controlling CPU 371 outputs a ball lending number signal indicating the number of lending balls to the terminal board 160 and a buzzer driving signal to the buzzer board 75 via the output port 372g. A buzzer is mounted on the buzzer board 75. Further, an error signal is output to the error display LED 374 via the output port 372e.

Further, the input port 3 of the prize ball control board 37
The detection signal of the prize ball count switch 301A and the detection signal of the ball lending count switch 301B are input to 72b via the relay board 72. The ball lending count switch 301B detects a game ball actually lent. The drive signal from the prize ball control board 37 to the payout motor 289 is output from the payout motor 2 in the prize ball mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72.
It is told to 89.

The card unit 50 is provided with a microcomputer for controlling the card unit. Also,
The card unit 50 is provided with a fraction display switch 152, a connection board direction indicator 153, a card insertion indicator lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected to a frequency display LED, a ball lending switch, and a return switch provided near the hit ball supply tray 3.

From the balance display board 74 to the card unit 50
In response to the player's operation, a ball lending switch signal and a return switch signal are provided via the prize ball control board 37. In addition, the balance display board 74 is provided from the card unit 50.
, A card balance display signal indicating the balance of the prepaid card and a ball lending possible display signal are given via the prize ball control board 37. Between the card unit 50 and the prize ball control board 37, a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal)
A pachinko machine operation signal (PRDY signal) is exchanged via the I / O port 372f.

When the power of the pachinko gaming machine 1 is turned on,
The prize ball control CPU 371 of the prize ball control board 37 outputs a PRDY signal to the card unit 50. When a card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the microcomputer for controlling the card unit outputs a BRDY signal to the prize ball control board 37. When a predetermined delay time elapses from this point, the microcomputer for controlling the card unit outputs a BRQ signal to the prize ball control board 37. The CPU 37 for controlling the prize ball on the prize ball control board 37
1 drives the payout motor 289 and pays out a predetermined number of lending balls to the player. Then, when the payout is completed, the prize ball controlling CPU 371 outputs an EXS signal to the card unit 50.

As described above, all the signals from the card unit 50 are input to the prize ball control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input from 0 to the main board 31, and there is no room for a signal to be incorrectly input from the card unit 50 side to the basic circuit 53 of the main board 31. Although the main board 31 and the prize ball control board 37 are provided with a solenoid and a driver circuit for driving a motor or a lamp, these circuits are omitted in FIG.

In this embodiment, the main substrate 31
CPU 56, display control CPU 101, audio control C
The PU 701, the lamp control CPU 351 and the award ball control CPU 371 are backed up by a backup power supply. That is, even if power supply to the gaming machine is stopped, those CPUs are operable for a predetermined period. Further, as described above, the CPU 5 of the main board 31
6. CPU 101 for display control, CPU 70 for audio control
1. CPU 351 for lamp control and CPU for award ball control
Since the 371 has at least a built-in RAM in addition to the CPU unit, the built-in RAM can retain the stored contents by the backup power supply even when the power supply to the gaming machine is stopped. When detecting a drop in the power supply voltage, each CPU performs a predetermined process, and then enters a power recovery wait state.

FIG. 9 is a block diagram showing an example of a configuration around a CPU for monitoring and backing up a power supply. As shown in FIG. 9, the power supply monitoring IC 902
The occurrence of power interruption is detected by introducing the V voltage and monitoring the 12 V voltage. Specifically, when the 12V voltage becomes equal to or less than a predetermined value (for example, 80% of 12V), it is determined that a power supply interruption occurs, and an interrupt signal is given to the CPU 901.
In the CPU 901, this interrupt is caused by an external interrupt (I
NT) terminal. The signal input to the INT terminal is also input to an input port built in the CPU 901. Therefore, the CPU 901 can detect the occurrence of power interruption by confirming the level of the input port in the interrupt processing. Note that a configuration may be employed in which a signal from the power supply monitoring IC 902 is connected only to the interrupt terminal without supplying an interrupt signal to the input port.

Further, as shown in FIG.
1 is supplied with power from a backup power supply.

The predetermined value for the power-supply monitoring IC 902 to detect the power-off is lower than the normal voltage, but is a voltage at which the prize-ball controlling CPU 371 can operate for a while.
In addition, since the power supply monitoring IC 902 is configured to monitor a voltage higher than the voltage required by the CPU 901 (+5 V in this example), the monitoring range can be expanded with respect to the voltage required by the CPU 901. it can. Therefore, more precise monitoring can be performed. Further, when +12 V is used as the monitoring voltage, since the voltage supplied to the various switches of the gaming machine is +12 V, erroneous switch-on detection during a momentary power interruption can be expected. That is, when the voltage of the +12 V power supply decreases, the switch output becomes ON. However, if the same +12 V power supply voltage is monitored and the power cutoff is recognized, the state of waiting for the power recovery before the switch output becomes ON state. To enter a state where the switch output is not detected.

While power is not being supplied from the + 5V power supply, CPU 901 operates with the backup power supply supplied from the power supply board. Then, when the + 5V power supply is restored, a reset signal is issued from the initial reset circuit 905, so that the CPU 901 returns to a normal operation state. Note that the initial reset circuit 905 has the same configuration as the initial reset circuit 65 shown in FIG. That is, when the power supply potential rises from 0 V and reaches a predetermined level, the initial reset signal applied to the CPU 901 is changed to, for example, a high level.

Here, it is assumed that the normal operation state is restored by the reset signal from the initial reset circuit 905. However, the power monitoring IC 902 is connected to the input port of the CPU 901.
If an interrupt signal from the power supply is introduced, detect that the signal level no longer indicates the level at the time of power failure, detect that the power supply has been restored, and return to the normal operation state. You may.

The configuration as shown in FIG. 9 is provided on each game device control board (the main board 31, the display control board 80, the voice control board 70, the lamp control board 35, and the prize ball control board 37 in this embodiment). Applied. That is, the power supply monitoring IC 902 is mounted on each board. Also, the CPU 901
The configuration around the CPU 56 of the main board 31 and the display control C
PU101, CPU 701 for voice control, C for lamp control
This is applied to the PU 351 and the CPU 371 for controlling the prize ball.

FIG. 10 is a block diagram showing an example of the configuration of the power supply board 910. The power supply board 910 includes a main board 31,
The display control board 80, the voice control board 70, the lamp control board 35, and the control board such as the prize ball control board 37 are installed independently of each other, and generate voltages used by each control board and mechanical components in the gaming machine. In this example, AC24V, DC + 3
Generates 0V, + 21V DC, + 12V DC and + 5V DC. A capacitor 9 serving as a backup power supply
16 is charged from DC + 5V, that is, a power supply line for driving an IC or the like on each substrate.

The transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A predetermined DC voltage is generated from V and supplied to the DC-DC converter 913. DC-DC converter 913
Generates +30 V, +21 V, +12 V, and +5 V and outputs them to the connector 915. The connector 915 is connected to, for example, a relay board, and power of a voltage necessary for each control board and mechanical components is supplied from the relay board.

+5 V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 serves as a backup power supply for each CPU when power supply to the gaming machine is cut off.

Note that a battery that can be charged from a +5 V power supply may be used as a backup power supply. In the case of using a battery, a rechargeable battery is used which runs out of capacity when power is not supplied from a + 5V power supply for a predetermined time.

FIG. 11 is a block diagram showing a power supply board 910 having another configuration together with a control board 920. The control board 920 corresponds to the main board 31, the display control board 80, the audio control board 70, the lamp control board 35, the prize ball control board 37, and the like. In this example, on the power supply board 910, AC 24V, DC + 30V, DC + 21V, DC +
12V and DC + 8V are generated.

The control board 920 includes the power supply board 9
8V-5 which converts + 8V supplied from 10 into + 5V
A V conversion circuit 921 is provided. A voltage is supplied from an 8V to 5V conversion circuit 921 to a control circuit 922 operating on + 5V on the control board 920. 8V-5V conversion circuit 9
21 is a DC including a switching regulator, for example.
-DC converter. The control circuit 922
Are the circuits on the control board 920. In FIG.
What corresponds to a CPU is illustrated.

In a power supply circuit 910 shown in FIG. 11, a capacitor 916 for a backup power supply is provided. In this example, the capacitor 916 is connected to the control board 920
It is charged by the + 5V voltage generated by the above 8V-5V conversion circuit 921. When the power supply to the gaming machine is cut off, power is supplied from the capacitor 916 to each CPU as in the case of the configuration shown in FIG. Also, a battery may be used instead of the capacitor 916.

When the +5 V voltage used in each control board is generated by the power supply board 910 collectively, noise may be applied to the power supply line from the power supply board 910 to each control board. As shown in FIG.
If a voltage higher than 5 V is supplied to each control board and each control board is configured to generate +5 V from the voltage, noise on a power supply line between the boards can be canceled.

Next, the operation of the gaming machine will be described. FIG.
2 is a flowchart showing the operation of the CPU 56 on the main board 31. As described above, this process is started, for example, every 2 ms by the reset pulse generated by the periodic reset circuit 66. When the CPU 56 is started, the CPU 56 first sets a built-in clock monitor register to a clock monitor enable state in order to enable the clock monitor control (step S1). Note that the clock monitor control means that when a fall or stop of the input clock signal is detected,
This is a control for automatically generating a reset inside the U56.

Next, the CPU 56 performs a stack setting process for setting the designated address of the stack pointer (step S2). In this example, 00FFH is set in the stack pointer. Then, a system check process is performed (step S3). In the system check process, the CPU 56 determines whether or not the RAM 55 contains an error.
Processing such as initializing 5 is performed. Further, when the power is turned on, control is performed to restore the register contents saved in the backup RAM area.

Next, after performing processing for setting a display control command sent to the display control board 80 to a predetermined area of the RAM 55 (display control data setting processing: step S
4) A process for outputting a display control command is performed (display control data output process: step S5).

Next, processing for outputting the contents of the storage area for various output data to each output port is performed (data output processing: step S6). Further, an output data setting process for setting output data such as jackpot information, start information, and probability variation information output to the hall management computer in the storage area is performed (step S8). Further, various abnormality diagnosis processes are performed by a self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S9).

Next, a process of updating each counter indicating each random number for determination such as a random number for big hit determination used in game control is performed (step S10).

Next, the CPU 56 performs a special symbol process (step S11). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Further, a normal symbol process is performed (step S12). In normal symbol processing, 7 segments L
A corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 by the ED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

Further, the CPU 56 includes a switch circuit 58
, The state of the gate sensor 12, the starting port sensor 17, and the count sensor 23 are input, and it is determined whether or not there is a prize for each prize port or prize device (switch processing: step S13).

The CPU 56 further performs a process of updating a display random number such as a random number for determining the type of stop symbol (step S15).

Further, the CPU 56 performs signal processing with the award ball control board 37 (step S16). That is,
When a predetermined condition is satisfied, a prize ball control command is output to the prize ball control board 37. The prize ball control CPU mounted on the prize ball control board 37 drives the ball payout device 97 according to the prize ball control command. Thereafter, the CPU 56 repeats the display random number updating process in step S17 until the next reset pulse is given from the periodic reset circuit 66.

FIG. 13 is a flowchart showing the interrupt processing of the CPU 56. As described above, the power supply monitoring IC
When the 902 detects a drop in the power supply voltage, the CPU 56 is interrupted. In the case where another interrupt factor is also input to the interrupt terminal or when it is necessary to more reliably detect the power supply voltage drop, as shown in FIG. The output of the IC 902 may be introduced, and the level of the input port may be confirmed in the interrupt processing to detect the occurrence of an interrupt due to a drop in the power supply voltage.

In the interrupt processing based on the power supply voltage drop,
First, the CPU 56 sets an interrupt prohibition state (step S20). Therefore, there is no interruption thereafter.
Therefore, the CPU 56 is not interrupted a plurality of times during the power supply voltage drop.

Then, the CPU 56 stores the contents of each register in the backup RAM area as a process at the time of power interruption (step S21). Further, an appropriate initial value is set in the backup check data area of the backup RAM area (step S22), and exclusive OR is sequentially performed on the initial value and all data saved in the backup RAM area (step S23). A typical operation value is set in the backup parity data area (step S
24).

Further, the CPU 56 sets the notification LED 41
Is turned on to notify a player or a game clerk that the power supply is being backed up (step S25). When the power supply to the gaming machine is stopped, the game control is interrupted. However, by providing the notification means, the player or the game clerk can easily recognize that. Further, it can be easily recognized that the game state is stored. Here, a dedicated notification LED 41 is used as the notification means.
However, a buzzer or another illuminant may be used.

Then, the CPU 56 disables the RAM access (step S26), and thereafter stops the game control. The stop state continues until power supply to the gaming machine is restarted.

FIG. 14 is a flowchart showing an example of the system check process (step S3) in the main process shown in FIG. When the power supply to the gaming machine is resumed, the initial reset circuit 65
Is supplied with an initial reset signal. The CPU 56 starts the main process in response to the initial reset signal. In the system check process, first, it is checked whether or not the power is turned on (step S41). Note that the CPU 56
When power is turned on, the power supply to the gaming machine is resumed after an unexpected power-off.

If the power is turned on, the RAM access is permitted (step S42). Then, a data check (parity check in this example) of the backup RAM area is performed (step S43). If the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, and the check result becomes normal. In general, the result of the check does not become normal when the power is turned on at the time of starting business at the game store. Therefore, if the check result is not normal (step S4
4), the register and the RAM area are cleared (step S45). In addition, necessary initial settings are made.

If the check result is normal (step S
44), only register clear is performed (step S4)
6). Also, if necessary, a clearing process is performed on an area other than the backup RAM area (an area that is not required to be saved when the power is turned off and restored). The reason why the register is cleared is to return to the initial state (the state when the power is turned on at the time of starting business at the game store). As described later, the register state is changed to an unexpected power supply after a certain period of time. It is returned to the state at the time of disconnection.

Then, the CPU 56 controls the display control board 8
0, control to send an initial state return request command to the voice control board 70 and the lamp control board 35 is performed (step S47), and a game state return timer is started (step S48). In step S47, the CPU 5
6 sets a command in a predetermined RAM area and sets a command transmission request flag. The command transmission request for the display control command on the display control board 80 is accepted in the display control data setting processing (step S4) in the main processing, and the command transmission request for the other control boards is, for example, the data output processing (step S4) in the main processing. Accepted in S6).

When it is confirmed in step S41 that the power is not turned on, the CPU 56 confirms whether or not the game state return timer is operating (step S5).
0). If it is operating, it is checked whether or not a timeout has occurred (step S51). If the time-out has occurred, control is performed to send a game state return request command to the display control board 80, the voice control board 70, and the lamp control board 35 (step S53), and the contents of the register stored in the backup RAM area are deleted. The process returns to the original register (step S54).

FIG. 15 is an explanatory diagram for explaining a backup parity data creating method. However, FIG.
In the example shown in FIG.
The size of the data saved in the M area is 3 bytes.
In the interrupt process due to the power supply voltage drop, initial data (00H in this example) is set in the backup check data area as shown on the left side of FIG. Next, "0
An exclusive OR of “0H” and “F0H” is obtained, and an exclusive OR of the result and “16H” is obtained. Further, an exclusive OR of the result and “DFH” is obtained. And
The result (“39H” in this example) is set in the backup parity data area.

When the power is turned on again, the parity diagnosis is performed in step S43 shown in FIG. 14. The right side of FIG. 15 is an explanatory diagram showing an example of the parity diagnosis. If all the data in the backup area is stored as it is, the data as shown on the left side of FIG. 15 is set in the backup area when the power is turned on again.

In the processing of step S813, the CPU
Reference numeral 56 denotes data set in the backup parity data area of the backup RAM area (in this example, “3”
9H ”) as initial data, a process of sequentially performing exclusive OR on each data in the backup data area is performed. If all the data in the backup area is stored as it is, the final calculation result is “00H”, that is, the same as the data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final operation result is “0”.
0H ".

Therefore, the CPU 56 compares the final operation result with the data set in the backup check data area, and if they match, determines that the parity diagnosis is normal. If they do not match, it is determined that the parity diagnosis is abnormal.

As described above, in this embodiment, when the power supply to the gaming machine is stopped, the CPU 56 recognizes this by interrupt processing, and performs processing for storing necessary data in the backup RAM area. At this time, the check data is also set in the backup RAM area. Therefore, the CPU 56 can confirm whether or not the data has been correctly stored at the time of recovery from an unexpected power-off. In addition, in the interrupt processing, the CPU sets the interrupt prohibition state and the RAM access prohibition state. Therefore, a plurality of interrupts do not occur when the power supply is cut off, and when the power supply voltage decreases, the CPU interrupts.
The state of the 56 bus lines is undefined, but does not destroy the RAM contents. Note that a CPU used in a gaming machine generally has a RAM access prohibition function.

As will be described later, the CPU of each control board other than the main board 31 temporarily responds to the initial state return command from the main board 31 (when the power is turned on at the time of starting business at the game store). State), and returns to the state at the time of unexpected power interruption in response to the game state return command. The time during this period is determined by the game state return timer value. In this way, once returning to the initial state,
After that, if the game state is returned to the power-off game state, for example, after the initial state screen is displayed on the variable display section 9, the game state returns to the original game state screen. Therefore, the player can easily recognize that the game has been restarted.

In this embodiment, the operation state of the CPU 56 is restarted by the initial reset signal, and the CPU 56 does not perform the normal game control until then. However, during the power backup, the CPU 56 sets the input port ( The state of the port (the port to which the signal from the power monitoring IC 902 is input) may be monitored to confirm that the power has been restored.

FIG. 16 is an explanatory diagram showing an example of the configuration of a table set in the ROM 55. As shown in FIG. 16, the ROM 55 is provided with, for example, a return data table and an initial state data table. The return data table includes, for example, an initial state return command to be sent to each of the display control board 80, the voice control board 70, and the lamp control board 35, a game state return timer value, and the display control board 80, the voice control board 70. In addition, parameters required at the time of power restoration such as a game state return command sent to each of the lamp control boards 35 are set. Therefore, in the process of setting those parameters in the program (steps S47, S48, S53), the necessary data is read from the return data table and the parameter setting process is performed.

As described above, the command sent to each of the plurality of gaming machine control means (means for controlling the gaming machine) when the power is restored is stored in the return data table in a recognizable manner. The CPU 56 of the main board 31, that is, the game control means, recognizes the command to be sent from the return data table when the power is restored, and sends the recognized command to the board on which each control means is mounted. In the return data table, commands for all game control means may be set, or commands for one or more necessary game control means may be set.

FIG. 17 is an explanatory diagram showing a configuration example of a display control command. As shown in FIG. 17, the display control command includes 8-bit data and a 1-bit strobe signal (INT signal).

FIG. 18 is an explanatory diagram showing an example of the configuration of display control command data based on 8-bit data. FIG.
As shown in (1), for example, the higher 4 bits of the 8 bits indicate the type of control, and the lower 4 bits indicate the specific control content. For example, in this example, if the upper 4 bits are [0, 0, 0, 1], the reach type, stop of all symbols, and the like are indicated by the numerical values of the lower 4 bits. If the upper four bits are [1,0,0,0], [1,0,0,1] or [1,0,1,0], the variable display unit 9 displays the numerical values of the lower four bits. A stop symbol of the left symbol, the middle symbol or the right symbol which is variably displayed is instructed.

The upper 4 bits are [1,1,1,0].
If this is the case, it indicates that the command is an initial state return command. If the upper 4 bits are [1,1,1,1], this indicates a game state return command. In these commands, the lower 4 bits are set to, for example, 0.

FIG. 19 is a flowchart showing an example of a special symbol processing program executed by the CPU 56. The special symbol process process shown in FIG. 19 is a specific process of step S11 in the flowchart of FIG. When performing the special symbol process processing, the CPU 56 performs any one of steps S300 to S309 shown in FIG. 19 according to the value of the special symbol process flag. In each process, the following processes are performed.

Special symbol change waiting processing (step S30)
0): The start winning port 14 (in this embodiment, the winning port of the variable winning ball device 15) is hit and the start port sensor 17 is turned on. When the starting port sensor 17 is turned on, the starting winning memory number is increased by + if the starting winning memory number is not full.
1 and a big hit determination random number is extracted.

Special symbol determination processing (step S301):
When the state in which the variable display of the special symbol can be started, the number of start winning prize stored is confirmed. If the starting prize memory number is not 0,
It is determined whether to be a big hit or an out-of-big hit according to the value of the extracted big hit determination random number. Stop symbol setting process (step S302): A stop symbol for the left and right middle symbols is determined.

Reach operation setting processing (step S30)
3): Whether or not the reach operation is performed is determined according to the value of the reach determination random number, and the variation mode of the reach operation is determined according to the value of the reach random number.

All symbols change start processing (step S30)
4): In the variable display section 9, control is performed so that all symbols start to change. At this time, with respect to the display control board 80,
The left and right middle final stop symbols and information instructing the variation mode are transmitted. When a background or a character is also displayed on the variable display unit 9, control is performed so that display control command data corresponding to the background or character is transmitted to the display control board 80.

All symbols stop wait processing (step S30)
5): Control is performed so that all symbols displayed on the variable display section 9 are stopped after a predetermined time has elapsed. Also, control is performed so that the left and right symbols are stopped at a predetermined timing until the timing of stopping all symbols.

Big hit display processing (step S306): When the stop symbol is a combination of big hit symbols, control is performed so that the display control command data of the big hit display is transmitted to the display control board 80, and the internal state (process flag) ) Is updated so as to shift to step S307. Otherwise, the internal state is changed to step S309.
Update to move to. The combination of the big hit symbols is a combination in which the right and left middle symbols are aligned. Also,
The display control CPU 101 of the game control board 80 displays a big hit on the variable display unit 9 according to the display control command data. The jackpot display is made to notify the player of the occurrence of the jackpot.

Opening process of opening the special winning opening (step S30)
7): Control for opening the special winning opening is started. Specifically, the counter and the flag are initialized, and the solenoid 21 is driven to open the special winning opening.

Processing during opening of the special winning opening (step S30)
8): Control for transmitting display control command data of the special winning opening round display to the display control board 80, processing for confirming establishment of the closing condition of the special winning opening, and the like are performed. If the closing condition of the special winning opening is satisfied, the internal state is updated to shift to step S307 unless the end condition of the big hit gaming state is satisfied. If the jackpot gaming state end condition is satisfied, the internal state is updated to shift to step S309.

[0130] Jackpot end processing (step S309):
A display for notifying the player that the jackpot gaming state has ended is performed. When the display is completed, the internal flags and the like are returned to the initial state, and the internal state is updated so as to shift to step S300.

A module (step S5 in FIG. 12) that performs processing for transmitting a display control command in the game control program in accordance with the processing in each of the above steps outputs the corresponding display control command data to the output port and Turn on the strobe signal.

FIG. 20 is a flowchart showing the display control data output process (step S5) in the main process shown in FIG. In the display control data output process, the CPU 56 determines whether a port A output request has been set (step S581). The port A output request is sent to the display control data setting process (step S
In 4), it is set in response to a command output request from a special symbol process process or the like.

If the port A output request has been set, the port A output request is reset (step S58).
2) Output the contents of the port A storage area to the output port (output port A) 571 (step S583). Also,
The port A output counter is incremented by 1 (step S
584), and sets bit 7 of the output port (port B) 572 to 0 (step S585).

If the port A output request has not been set, it is determined whether the value of the port A output counter is 0 (step S586). If the value of the port A output counter is not 0, the value of the port A output counter is 2
Is determined (step S587). Port A
If the value of the output counter is not 2, that is, it is 1, the value of the port A output counter is increased by 1 (step S588).

If the value of the port A output counter is 2, the value of the port A output counter is cleared (step S589), and the output port (output port B) 5 is cleared.
The bit 7 of 72 is set to 1 (step S590).

Bit 7 of the output port B is a port for outputting a strobe signal (INT signal) applied to the display control board 80. Also, bits 0 to 7 of output port A
Is a port for outputting display control command data.
In this embodiment, the display control data output process shown in FIG. 20 is executed once every 2 ms. Therefore,
By the data output processing shown in FIG. 20, when the display control command data is output as shown in FIG. 21, the INT signal goes low for 4 ms.

Next, the operation of the display control CPU 101 will be described. FIG. 22 is a flowchart showing the operation of the display control CPU 101 in the display control board 80. The display control CPU 101 enters a loop state after initializing output ports and work areas and performing initial processing such as timer setting (step S101). In the initial processing, a timer is set such that a timer interrupt occurs every 500 μs and 2 ms. Therefore, in the loop state, if a timer interruption of 500 μs occurs, a timer interruption processing of 500 μs is performed (step S10).
2) When a 2 ms timer interrupt is applied, a 2 ms timer interrupt process is performed (step S103). In addition, 500μ
The display control command receiving process is performed in the s timer interrupt process, and the display control process is performed in the 2 ms timer interrupt process.

FIG. 23 is a flowchart showing a timer interruption process of 2 ms. When a timer interrupt of 2 ms occurs, the display control CPU 101 performs an initial process such as starting a timer so that the next 2 ms interrupt occurs (step S111), and then performs a display control process process (step S112). Execute.

FIG. 24 is a flowchart showing a display control command reading process executed in the 500 μs timer interrupt process. In the display control command reading process, the display control CPU 101 reads the bit 7 of the input port assigned to the strobe signal (INT signal).
Then, it is determined whether or not the bit 7 is turned on (low level) (step S501). If it is turned on, display control command data is read from the input port assigned to input of the display control command data (step S502). As described above, the INT signal goes low when the CPU 56 of the main board 31 outputs new display control command data.

If the INT signal is off, the display communication counter is cleared (step S506). The display communication counter is used to count the number of times display control command data is received when the INT signal is on.

When the INT signal is ON, the received display control command data is immediately before (500 μs before).
It is determined whether the received command data is the same as the received command data (step S503). If they are not the same, the display communication counter is cleared (step S506). If they are the same, it is checked whether the display communication counter has reached a predetermined maximum value (MAX) (step S504).

If it has not reached the maximum value, the value of the display communication counter is incremented by 1 (step S505). Here, the maximum value is a value larger than a value (3 in this example) for determining that the display control command data has been reliably received, and is used for the purpose of counting the number of receptions in 4 ms, for example. Can be

Next, the display control CPU 101 checks whether or not the value after the display communication counter has become "3" (step S507). If it is "3", the received data is stored in the received command storage area (step S509). Then, the received data is stored in the work area (step S510). The data stored in the work area is used in step S503 in the next interrupt processing.

As described above, the display control CPU 101
For example, when the same display control command data is received three times in succession, for example, it is determined that the display control command has been received, and the communication end flag is set. Then, when the communication end flag is set, processing such as pattern change and display switching of the background / character is performed based on the display control command stored in the received command storage area.

FIG. 25 shows the display control process in the timer interrupt process shown in FIG. 23 (step S112).
It is a flowchart which shows. In the display control process, step S7 is performed according to the value of the display control process flag.
Any one of the processes from 20 to S870 is performed. In each process, the following processes are performed.

Display control command reception waiting processing (step S720): The contents of the work area in which the reception command is set are read according to the ON of the communication end flag, and
It is determined whether a display control command capable of specifying the fluctuation time has been received.

Reach operation setting processing (step S75)
0): Determine which one of a plurality of variation patterns corresponding to the received display control command capable of specifying the variation time is used.

All symbols change start processing (step S78)
0): Control is performed so that the change of the middle left and right symbols is started.

Symbol change processing (step S810): The switching timing of each change state (change speed, background, character) constituting the change pattern is controlled, and the end of the change time is monitored. Also, stop control of the left and right symbols is performed.

All symbols stop wait setting process (step S84)
0): At the end of the fluctuation time, if a display control command instructing to stop all the symbols has been received, the control of stopping the fluctuation of the symbols and displaying the final stopped symbol (fixed symbol) is performed.

Big hit display processing (step S870): After the end of the fluctuation time, control of round display during a big hit game, display of a probability change big hit display or normal big hit display is performed.

FIG. 26 is a flowchart showing the interrupt processing of the display control CPU 101. When the power supply monitoring IC mounted on the display control board 80 detects a drop in the power supply voltage, the display control CPU 101 is interrupted. In the case where another interrupt factor is also input to the interrupt terminal or when it is desired to more surely detect a drop in the power supply voltage, the power supply monitoring IC 902 is connected to the input port as shown in FIG. May be introduced, and the level of the input port may be confirmed in the interrupt processing to detect the occurrence of an interrupt due to a drop in the power supply voltage.

In the interrupt processing based on the power supply voltage drop,
First, the display control CPU 101 sets an interrupt prohibited state (step S330). Therefore, there is no interruption thereafter. Therefore, the display control C
The PU 101 is not interrupted more than once.

Then, the display control CPU 101 stores data necessary for continuation of display control in the backup RAM area as power-off processing (step S33).
1). Also, an appropriate initial value is set in the backup check data area of the backup RAM area (Step S).
332), exclusive OR is sequentially performed on the initial value and all data saved in the backup RAM area (step S333), and the final operation value is set in the backup parity data area (step S334). Note that the specific process of generating the check data may be the same as the process executed by the CPU 56 of the main board 31.

Furthermore, the display control CPU 101
The M access is prohibited (step S335), and thereafter the display control is stopped. The stop state continues until power supply to the gaming machine is restarted.

FIG. 27 is a flowchart showing an example of the initial processing (step S101) in the main processing shown in FIG. When the power supply to the gaming machine is restarted, a reset signal is input to the display control CPU 101 to restart the process. In the initial process, first, it is checked whether or not the power is turned on (step S341). From the point of view of the display control CPU 101, the time when the power supply to the gaming machine is restarted after the unexpected power-off is also the time when the power is turned on.

If the power is turned on, the RAM access is permitted (step S342) and the backup RAM is set.
Data check of area (parity check in this example)
Is performed (step S343). If the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, and the check result becomes normal. The reason why the check result is not normal is when the power is turned on at the time of starting business at the game store. Therefore, if the check result is not normal (step S344), the register and the RAM area are cleared (step S34).
5). In addition, necessary initial settings are made.

If the check result is normal (step S
344), the data other than the backup RAM area is cleared (step S346). Further, an initial state return request waiting flag is set (step S347).

When it is confirmed in step S341 that the power is not turned on, the display control CPU 101 confirms whether or not the initial state return request waiting flag is set (step S350). If it is set, it is confirmed whether or not an initial state return request command has been received from the main board 31 (step S351). If it has been received, the contents of the RAM and the like are set to the initial state (step S
352). Then, an initial state return request waiting flag is reset (step S353), and a game state return request wait flag is set (step S354).

If it is confirmed in step S350 that the initial state return request is not awaited, the display control CPU 1
01 checks whether the game state return request waiting flag is set or not (step S355). If it is set, it is checked whether a game state return request command has been received from the main board 31 (step S356). If the data has been received, the data stored in the backup RAM area is restored to the original area (step S35).
7). Then, the game state return request waiting flag is reset (step S358).

As described above, the CPU 56 of the main board 31
Sends an initial state return request command when power is restored after an unexpected power interruption. Therefore, the display control C
Upon receiving the command, the PU 101 executes step S
At 352, the internal state is set to the initial state (the state when the power is turned on at the time of starting business in the game store). Therefore, in the display control process or the like, a process based on the setting of the initial state is performed. That is, for example, an initial screen is displayed on the variable display unit 9.

Thereafter, the CPU 56 of the main board 31 sends out a game state return request command. Therefore, upon receiving the command, the display control CPU 101 returns the internal state to the state at the time of power-off in step S357. Then, in the display control process or the like, the process can be restarted from the state at the time of power-off.

When the processing is restarted, the processing may be restarted from a well-defined control state. For example, when the power is turned off, the variable display unit 9
In the case where the symbol is changing, the display control may be restarted from the stage of starting the change. If the design is changing when the power is turned off, the display control process flag stored in the backup RAM area is changed to “design changing”.
(See FIG. 25). Therefore, in such a case, if the display control CPU 101 performs control such as returning the value of the timer for measuring the symbol change period to the initial value (the value at the start of the change) in step S357, for example,
The display control can be restarted from the stage of starting the change.

When the symbol is being changed on the variable display section 9 when the power is turned off, the result of the change is displayed on the variable display section 9.
And the processing may be advanced. Display control CPU
101, for example, when the display control process flag stored in the backup RAM area indicates a value of “symbol changing”, the contents of the stopped symbol storage area stored in the backup RAM area are variably displayed. If the display is controlled on the display unit 9 and the value of the display control process flag is set to a value corresponding to “waiting for display control command reception”, the fluctuation result is displayed on the variable display unit 9 and the process proceeds. Can be.

Further, the display control process flag stored in the backup RAM area is changed to "big hit display processing".
(As described above, the big hit display process also includes the display period during the big hit game), and the display control CPU 101 can return to the processing state. At this time, when the special symbol process flag stored in the backup RAM area indicates, for example, “processing for opening a special winning opening”, the CPU 56 of the main board 31
Return to that state. Therefore, when the special winning opening is being opened, the CPU 56 of the main board 31 performs control to open the special winning opening again. In addition, the jackpot game can be restarted from a predetermined round during the jackpot game (a round when the power is turned off). The information indicating the number of rounds and the state of the output port (for example, the output port for the solenoid 21 for opening the special winning opening) are stored in the backup RAM area when the power is turned off.

When the power-off occurs during the opening of the special winning opening during the “winning opening processing”, not only the information indicating the predetermined round but also the opening in that round stored in the RAM. The elapsed time and the number of winning prizes in the special winning opening (count number) are also stored. Therefore, the main substrate 31
When the power is restored, the CPU 56 can restart the elapsed time of opening the special winning opening and the counted number from the state at the time of power-off.

FIG. 28 shows the main board 31 to the voice control board 7.
FIG. 9 is an explanatory diagram showing an example of voice control command data sent to 0. Each voice control command data shown in FIG.
It consists of bits, each of which specifies the type of sound effect. The voice control command data includes an initial state return request command and a game state return request command. These commands are transmitted when the CPU 56 of the main board 31 sends the display control commands of the initial state return request and the game state return request to the display control board 80.
Also sent to 0.

FIG. 29 is an explanatory diagram showing the bit configuration of the voice control command. As shown in FIG. 29, the voice control command is composed of 8-bit data and a 1-bit strobe signal (INT signal).

FIG. 30 is a flowchart showing the output data setting process (step S8) in the main process shown in FIG. However, here, the voice control board 7
Only the output data setting of the control command for 0 and the lamp control board 35 is shown. In the output data setting process, the CPU 56 determines whether or not the audio data has been changed (step S81). Changes to audio data
For example, in the special symbol process of the CPU 56 of the main board 31, ie, the game control means, the sound generation pattern is changed when it is necessary to change the sound generation pattern.

When the audio data is changed, the CP
U56 reads, for example, audio data in the process data used in the special symbol processing, that is, audio control command data (step S82). Then, it is set in the port C data storage area (step S84). Further, a port C output request is set (step S8).
5).

If there is no change in the audio data, C
The PU 56 determines whether there is no change in the lamp data (Step S86). The change of the lamp data is also changed when it is necessary to change the lamp / LED display pattern in the special symbol process of the game control means, for example.

If the lamp data has been changed, C
The PU 56 reads out, for example, lamp data, ie, lamp control command data, in the process data used in the special symbol processing (step S87). And
Set in the port E data storage area (step S8
9). Further, a port E output request is set (step S90).

FIG. 31 is a flowchart showing a voice control command output portion of the data output process (step S6) in the main process shown in FIG. In the data output process related to the voice control command output, the CP
U56 determines whether or not the port C output request is set (step S601). If the port C output request has been set, the port C output request is reset (step S602), and the contents of the port C storage area are output to the output port (output port C) 573 (step S603). Voice control command data is set in bits 0 to 7 of the port C storage area. Then, the port C output counter is incremented by 1 (step S604).
The bit 7 of the output port (port D) 574 is set to 0 (step S605).

If the port C output request has not been set, it is determined whether or not the value of the port C output counter is 0 (step S606). If the value of the port C output counter is not 0, the value of the port C output counter is 2
Is determined (step S607). Port C
If the value of the output counter is not 2, that is, it is 1, the value of the port C output counter is increased by 1 (step S608).

If the value of the port C output counter is 2, the value of the port C output counter is cleared (step S609), and the output port (output port D) 5 is cleared.
The bit 7 of 74 is set to 1 (step S610).

Bit 7 of output port D is a port for outputting an INT signal applied to voice control board 70.
Bits 0 to 7 of the output port C are ports for outputting voice control command data. Then, in this embodiment, the data output processing shown in FIG. 31 is executed once every 2 ms. Therefore, as shown in FIG. 32, when the voice control command data is output by the data output processing shown in FIG. 31, the INT signal goes low for 4 ms.

Next, the operation of the voice control CPU 701 will be described. FIG. 33 is a flowchart showing the operation of the audio control CPU 701 in the audio control board 70. After performing initial processing such as initialization of an output port and a work area and timer setting (step S121), the voice control CPU 701 enters a loop state. In the initial processing, a timer is set such that a timer interrupt occurs every 500 μs and 2 ms. Therefore, in the loop state, if a timer interrupt of 500 μs is applied, a 500 μs timer interrupt process is performed (step S12).
2) When a 2 ms timer interrupt occurs, a 2 ms timer interrupt process is performed (step S123). In addition, 500μ
In the s timer interrupt process, a voice control command receiving process is performed, and in the 2 ms timer interrupt process, a voice control process is executed.

FIG. 34 is a flow chart showing a 2 ms timer interrupt process. When a timer interrupt of 2 ms occurs, the voice control CPU 701 performs an initial process such as activating a timer so as to perform the next 2 ms interrupt (step S125), and then performs a voice IC control process (step S126). Execute. The voice control command receiving process by the 500 μs timer interrupt process is performed by the display control C.
This is performed in the same manner as the display control command receiving process executed by the PU 101 (see FIG. 24).

In the ROM, a voice corresponding to each voice control command data shown in FIG. 28 is stored in a voice synthesizing circuit (voice synthesizing LSI; for example, digital signal processor) 70.
2 stores control data to be generated. The voice control CPU 701 reads control data corresponding to each received voice control command data from the ROM.

In this embodiment, the speech synthesis circuit 702
Are controlled by a transfer request signal (SIRQ), a serial clock signal (SICK), a serial data signal (SI), and a transfer end signal (SRDY). When the SIRQ goes low, the speech synthesis circuit 702
Synchronize with ICK, fetch SI one bit at a time,
When Y becomes low level, the data consisting of each SI received so far is interpreted as one audio reproduction data. Accordingly, the voice control CPU 701 turns on SIRQ (low level) (step S135), outputs the control data read from the ROM as SI in synchronization with SICK (step S136), and when the output is completed, turns the SRDY low. The level is set (step S137). When receiving the control data through the SI, the voice synthesis circuit 702 generates a voice corresponding to the received control data.

A power supply monitoring IC 902 as shown in FIG. 9 is also mounted on the audio control board 70. And
When the power supply monitoring IC 902 detects a drop in the power supply voltage,
An interrupt is issued to the CPU 701 for voice control. When an interrupt occurs, the voice control CPU 701 stores data necessary for continuation of voice control in the backup RAM area as power-off processing. The specific processing at the time of power-off is the same as the control executed by the display control CPU 101 (see FIG. 26).

Thus, in the initial process (step S121), the voice control CPU 701 also performs the process of restoring the data stored in the backup RAM area, the initial state return request command, and the game state return in the same manner as the display control CPU 101. The request command is received (see FIG. 27).

The CPU 56 of the main board 31 also sends an initial state return request command to the voice control board 70 when the power is restored after an unexpected power cut. Upon receiving the command, the voice control CPU 701 sets the internal state to the initial state (the state when the power is turned on at the time of starting business in the game store). Therefore, the processing based on the setting of the initial state is performed.

Thereafter, the CPU 56 of the main board 31 sends out a game state return request command. Voice control CP
Upon receiving the command, U701 returns the internal state to the state when the power was turned off. Therefore, the voice control means can also resume the processing from the state at the time of power-off.

FIG. 36 is an explanatory diagram showing an example of a lamp control command sent from the main board 31 to the lamp control board 35. Each lamp control command data is composed of 7 bits, and a lamp / LED according to the progress of the game, respectively.
Specify the lighting pattern and turn off. However, FIG.
Is an example of a pattern corresponding to a specific gaming machine. In other gaming machines, lamp control command data having different definitions can be used. For example, in the example shown in FIG.
To 08H), but in a gaming machine having more special fluctuation patterns, the special fluctuation patterns may be assigned to more types of lamp control command data. Alternatively, the lamp control data that may be used in all the gaming machines may be defined, and the lamp control data to be used in each model may be selected as needed.

The ramp control command data includes an initial state return request command and a game state return request command. These commands are sent to the CP on the main board 31.
When U56 sends the display control command of the initial state return request and the game state return request to the display control board 80, it is also sent to the lamp control board 35.

FIG. 37 is an explanatory diagram showing the bit configuration of the lamp control command. As shown in FIG. 37, the ramp control command includes 8-bit data and a 1-bit strobe signal (INT signal).

FIG. 38 is a flowchart showing a ramp control command output portion of the data output process (step S6) in the main process shown in FIG. In the data output process related to the lamp control command output,
The CPU 56 determines whether or not the port E output request has been set (step S621). The port E output request is set when the lamp data is changed in the output data setting process shown in FIG.

If the port E output request has been set, the port E output request is reset (step S62).
2) Output the contents of the port E storage area to the output port (output port E) 575 (step S623). Lamp control command data is set in bits 0 to 7 of the port E storage area. Then, the port C output counter is incremented by 1 (step S624), and bit 7 of the output port (port F) 576 is set to 0 (step S624).
625).

If the port E output request has not been set, it is determined whether or not the value of the port E output counter is 0 (step S626). If the value of the port E output counter is not 0, the value of the port E output counter is 2
Is determined (step S627). Port E
If the value of the output counter is not 2, that is, it is 1, the value of the port E output counter is increased by 1 (step S628).

If the value of the port E output counter is 2, the value of the port E output counter is cleared (step S629), and the output port (output port F) 5 is cleared.
The bit 7 of 76 is set to 1 (step S630).

The bit 7 of the output port F is a port for outputting an INT signal applied to the lamp control board 35. Bits 0 to 7 of the output port E are ports for outputting ramp control command data. In this embodiment, the data output process shown in FIG.
Executed once every ms. Therefore, when the lamp control command data is output by the data output process shown in FIG. 38, the INT signal goes low for 4 ms as shown in FIG.

Next, the operation of the lamp control CPU 351 will be described. FIG. 40 is a flowchart showing the operation of the lamp control CPU 351 in the lamp control board 35. The lamp control CPU 351 enters a loop state after initializing an output port and a work area and performing initial processing such as timer setting (step S151). 500 μs and 2 ms in initial processing
The timer is set such that a timer interrupt occurs every time. Therefore, in the loop state, if a timer interrupt of 500 μs occurs, a timer interrupt process of 500 μs is performed (step S152), and if a timer interrupt of 2 ms occurs, 2 ms
Timer interruption processing is performed (step S153). Note that the lamp control command receiving process is performed in the 500 μs timer interrupt process, and the lamp control process is performed in the 2 ms timer interrupt process.

FIG. 41 is a flowchart showing a timer interruption process of 2 ms. When a timer interrupt of 2 ms occurs, the lamp control CPU 351 performs initial processing such as starting a timer so that the next 2 ms interrupt occurs (step S155), and then turns on / off the lamp / LED (step S155). S156) is executed. In addition, 500
The lamp control command reception processing by the μs timer interruption processing is performed in the same manner as the display control command reception processing executed by the display control CPU 101 (see FIG. 24).

The built-in R of the lamp control CPU 351
OM or external RO mounted on lamp control board 35
In M, each lamp control command data (in this example, 0
The lighting / extinguishing pattern of the game effect LED 28a and the game effect lamps 28b and 28c according to 1H to 0FH) is stored as lighting pattern data. Then, the lamp / LED lighting / light-off processing (step S15)
In 6), the control of turning on / off the lamp / LED is performed based on the contents of the table according to the received lamp control command. In addition, lighting / extinguishing processing of the award ball lamp 51 and the ball out lamp 52 is performed according to the lamp control command.

The power supply monitoring IC 902 as shown in FIG. 9 is also mounted on the lamp control board 35. When the power supply monitoring IC 902 detects a drop in the power supply voltage, it interrupts the lamp control CPU 351. When an interrupt occurs, the lamp control CPU 351 stores data necessary for continuing the lamp / LED lighting / lighting-off control in the backup RAM area as a power-off process. The specific processing at the time of power-off is performed by the display control CPU.
This is the same as the control executed by 101 (see FIG. 26).

Therefore, in the initial process (step S151), the lamp control CPU 351 also performs the process of restoring the data stored in the backup RAM area, the initial state restoration request command, and the game state restoration in the same manner as the display control CPU 101. The request command is received (see FIG. 27).

The CPU 56 of the main board 31 sends an initial state return request command to the lamp control board 37 when the power is restored after an unexpected power cut. Upon receiving the command, the lamp control CPU 371 sets the internal state to the initial state (the state when the power is turned on at the time of starting business in the game store). Therefore, the processing based on the setting of the initial state is performed.

Thereafter, the CPU 56 of the main board 31 sends out a game state return request command. Lamp control C
Upon receiving the command, the PU 351 returns the internal state to the state at the time of power off. Therefore, the lamp control means can also restart the processing from the state at the time of power off.

FIG. 42 shows the main board 31 and the prize ball control board 3
FIG. 7 is an explanatory diagram showing an example of a bit configuration of a prize ball control command transmitted to 7. As shown in FIG. 42, the ramp control command is composed of 8-bit data and a 1-bit strobe signal (INT signal). And 8
The upper four bits of the bit data are used as control designation. That is, bits 7, 6, 5, and 4 are "0,
“0,0,0” indicates the normal payout designation (prize ball number output), and “0,0,0,1” indicates the corrected payout designation, and is “0,0,1,0”. A ball lending prohibition designation is indicated, and a ball lending prohibition designation is released if "0, 1, 1, 1". The ball lending prohibition is designated when the surplus ball tray 4 is full and the full switch 48 is turned on, and when the ball out detection switch 167 or the ball out switch 187 is turned on, the basic circuit of the main board 31 is turned on. Sent from 53. And when those switches are turned off,
The ball lending prohibition release is transmitted. Further, the correction payout designation is sent from the main board 31 when the game control means detects a prize ball payout shortage.

The award ball control command is transmitted from the main board 31 to the award ball control board 37 via the output ports (ports G, H) 577 and 578 as shown in FIG.
In this embodiment, as shown in FIG. 43, when the prize ball control command data is output from the main board 31, the INT signal is at the low level for 4 ms.

FIG. 44 is a flowchart showing the operation of the award ball control CPU 371 in the award ball control board 37. The prize ball controlling CPU 371 enters a loop state after initializing an output port and a work area and performing initial processing such as timer setting (step S171).
In the initial processing, a timer is set such that a timer interrupt occurs every 500 μs and 2 ms. Therefore, in the loop state, if a 500 μs timer interrupt is applied, a 500 μs timer interrupt process is performed (step S172), and if a 2 ms timer interrupt is applied, a 2 ms timer interrupt process is performed (step S173). In addition,
In the 500 μs timer interrupt process, a prize ball control command receiving process is performed, and in the 2 ms timer interrupt process, a prize ball control process is executed.

FIG. 45 is a flowchart showing a timer interruption process of 2 ms. When a 2 ms timer interrupt is applied, the prize ball control CPU 371 performs initial processing such as starting a timer so that the next 2 ms interrupt is applied (step S175), and then performs award ball processing (step S17).
Execute 6). The prize ball control command receiving process by the 500 μs timer interrupt process is executed by the display control CPU 10.
1 is performed in the same manner as the display control command receiving process executed by the device 1 (see FIG. 24). In the prize ball control processing, the prize ball control CPU 371 drives the ball payout device 97 based on the prize ball control command received from the main board 31 to execute the prize ball payout.

The power supply monitoring IC 902 as shown in FIG. 9 is also mounted on the award ball control board 37. And
When the power supply monitoring IC 902 detects a drop in the power supply voltage,
The CPU 371 for the prize ball control is interrupted. When an interrupt occurs, the CPU 371 for controlling the prize ball stores data necessary for continuation of the prize ball control in a backup RAM area as a power-off process. The specific processing at the time of power-off is the same as the control executed by the display control CPU 101 (see FIG. 26).

Therefore, the CPU 371 for controlling the prize ball also performs the process of restoring the data stored in the backup RAM area in the initial process (step S171), similarly to the CPU 101 for display control (see FIG. 27). However, the reception processing of the initial state return request command and the game state return request command is not performed.

As described above, in this embodiment, when the power supply to the gaming machine is stopped, the main board 31, the display control board 80, the audio control board 70, the lamp control board 35, and the prize ball control board 37 are mounted. Each of the CPUs recognizes this by an interrupt process and performs a process of transferring necessary data to the backup RAM area. At this time, the check data is also set in the backup RAM area. Therefore, the CPU can resume the processing from the power-off state by restoring necessary data from the backup RAM area at the time of recovery from an unexpected power-off.

In the above embodiment, the CP of each control board is
U introduces the signal from the power supply monitoring IC 902 to the interrupt terminal or both the interrupt terminal and the input port, but may introduce it to only the input port. FIG. 46 is a block diagram showing such an embodiment. CPU 901 in FIG. 46
Are the main board 31, the display control board 80, the audio control board 7
0 corresponds to each CPU mounted on the lamp control board 35 and the award ball control board 37. In this case, in the main board 31, the CPU 56 monitors whether or not the signal from the power supply monitoring IC is turned on in the main processing, not in the interrupt processing. Then, when it is detected that it has been turned on, processing for storing necessary data as shown in FIG. 13 in the backup RAM is performed.

Further, the display control board 80 and the audio control board 7
0, each of the CPUs mounted on the lamp control board 35 and the award ball control board 37 is not in the interrupt processing but in the loop in the main processing (the processing shown in FIGS. 22, 33, 40 and 44). It monitors whether a signal from the power supply monitoring IC is turned on. Then, when it is detected that the power is turned on, a process of storing necessary data in the backup RAM is performed.

Also in this embodiment, the CPU of each control board may recognize that the power supply has been restored by an initial reset signal, or the power supply monitoring IC 90
Recognition may be made based on the level of an input port for introducing a signal from the second port.

Further, as shown in FIG. 47, a signal from the power supply monitoring IC 902 may be introduced to a non-maskable interrupt terminal (NMI terminal) of the CPU 901. In this case, in each control board, the CPU monitors whether or not the signal from the power supply monitoring IC is turned on in the NMI processing, not in the normal interrupt processing. However, the content of the process is the same as the process shown in FIG. 13 (the process of storing necessary data in the backup RAM) except for the process of disabling the interrupt. Also, as shown in FIG.
The signal from the power supply monitoring IC 902 is also introduced into the input port, and in the NMI processing, necessary data when the level of the input port indicates power off is stored in the backup RAM.
May be performed. Also, CPU
However, if the NMI terminal is at a predetermined level (for example, low level) and the NMI is applied to the NMI terminal, one NMI interrupt occurs between the power monitoring IC 902 and the NMI terminal of the CPU. A one-shot pulse output circuit for generating a one-shot pulse having such a pulse width may be provided.

In this case as well, the CPU of each control board may recognize that the power has been restored by using the initial reset signal, or recognize the level of the input port to which the signal from the power monitoring IC 902 is introduced. You may make it.

In each of the above embodiments, the power supply monitoring IC 902 is used to detect a decrease in the power supply voltage. However, for example, a divided voltage of +12 V is introduced into the one-shot pulse output circuit, The output of the shot pulse output circuit may be input to an interrupt terminal (INT terminal or NMI terminal). The one-shot pulse output circuit outputs a one-shot pulse when the input level falls below a predetermined value. Therefore, even with such a configuration, a drop in the power supply voltage can be detected.

Further, the output of the one-shot pulse output circuit may be introduced into the input port of the CPU to detect a drop in the power supply voltage by detecting the level of the input port. The signal may be input to an interrupt terminal (INT terminal or NMI terminal) and an input port. When an input is made to the interrupt terminal and the input port, the level of the input port is detected in the interrupt processing, and if the level indicates the level at the time of power-off, the power-off processing is executed.

In each of the above embodiments, the power supply monitoring IC 902 is mounted on each control board, and the power cut-off is detected on each control board. However, the power supply monitoring IC is mounted on the power supply board 910. The power supply board 910 may be configured to detect the power-off at once. In that case, a detection signal from the power supply monitoring IC is supplied from the power supply board 910 to each control board.

In the above description, for example, as shown in FIG. 9, the fact that the power has been restored may be detected by the output of the initial reset circuit. It may be detected that the power has been restored when the output of the periodic reset circuit is restarted. Alternatively, when another reset unit is connected to the CPU, the reset unit may be used to detect that the power has been restored.

In each of the above embodiments, as shown in FIG. 9, the return data table of the game control means specifies an initial state return request command, a game state return timer value, and a game state return request command. Possible information was set. However, more information may be set at the time of power restoration so that the player can easily return to the game state at the time of power interruption. For example, as shown in FIG. 48, information indicating a special symbol process flag storage area (special symbol process flag setting area) may be set in the return data table.

When the power is restored, the CPU 56 of the main board 31 inputs the value of the special symbol process flag with reference to the data of the special symbol process flag setting area of the return data table, for example. Then, based on the value, it is possible to confirm the state of the symbol change of the variable display section 9 when the power is turned off.

It has already been mentioned that, when the power is restored, if the symbol is being changed on the variable display section 9 when the power is turned off, the state at the start of the symbol change may be returned, but such a return is facilitated. Therefore, more data may be set in the return data table. For example, if a value corresponding to “all symbol variation start processing” is set in the return data table, the CPU 56 reads the value and sets the value in the special symbol process flag, thereby obtaining the special symbol process flag. The control state can be returned to the state corresponding to the “all symbol variation start processing”. In the “all symbol variation start process” in the special symbol process process illustrated in FIG. 19, for example, a left and right middle stop symbol and information instructing a variation mode are transmitted to the display control board 80.

Here, as the data for facilitating the return to the state at the start of the symbol change, a value corresponding to the special symbol process flag “all symbol change start processing” is exemplified. If it is necessary to change the values of the work data such as other internal flags to return the control state to the state corresponding to "all symbol change start processing", set those values in the return data table as well. May be.

As described above, when the symbol is being changed in the variable display section 9 when the power is unexpectedly turned off, and the state is returned to the state at the time of the start of the symbol change when the power is restored, the return data table is displayed. If more information is set, the game control means and the display control means can easily return to the state and recover.

If the symbols are changing when the power is turned off, the game control means may return to the game state when the power is turned off when the power is restored, and the display control means may perform predetermined display control. To enable such control, FIG.
, An error command is also set. In addition, as described above, when the game control means is configured to return to the state at the time of starting the symbol change when the power is restored when the symbol is changing when the power is turned off, the error command is displayed in the return data table. It does not need to be set.

FIG. 49 is a flowchart showing another example of the system check process (step S3 in the main process) executed by CPU 56 of main board 31. In this example, when the gaming state return timer times out (step S51), the CPU 56 checks whether or not the special symbol is changing (step S55). The confirmation is made from the RAM area having the information of the special symbol process flag setting area in the return data table as an address.
It can be executed by reading the saved special symbol process flag. If the special symbol process flag indicates “all symbol stop wait processing”, the CPU 56
Determines that the special symbol was being changed. If the special symbol is being changed, an error command transmission request is set to the display control board 80 (step S5).
6).

Therefore, if the symbol is being changed on the variable display section 9 when the power is turned off, the display control CPU 101 receives an error command when the game state return timer times out. Display control CPU
When the error command is received, the symbol change is restarted and, for example, an error is displayed on the variable display unit 9 so that the player can identify the error as an error. Then, the display control CPU 101 erases the error display at the end of the symbol change. Note that the display control CPU 101 may display the error screen without changing the symbol. Further, the CPU 56 of the main board 31 does not change the value of the special symbol process flag. That is, when the symbol is changing when the power is turned off, the game control means returns to the game state when the power is turned off when the power is restored.

In such display control, a display control command capable of specifying a fluctuation period is transmitted from the game control means to the display control means at the start of symbol fluctuation, and thereafter, the display control command is not transmitted until the fluctuation is stopped. It is effective in a gaming machine configured as described above. That is, since the display control command is not sent during the symbol change, the game control means cannot give an instruction to the display control means to restart the game from a state in the middle of the symbol change.
If it is desired to configure the display control means to restart the game from a state in which the symbols are being changed based on an instruction from the game control means, the command transmission control method must be changed. However, if the error screen described above is used to display an error screen at the time of the change using the error command, the command transmission control method (when the game control means starts the game change, the game control means On the other hand, it is not necessary to change the display control command that can specify the fluctuation period.

When the game control means returns from the power-off state to the power-off state, a display control command indicating a stop symbol (variable display result) is sent to the display control means. Is also good. FIG. 50 is a flowchart showing such a process. In this example, when the game state return timer times out (step S5).
1), the CPU 56 checks whether or not the special symbol is being changed (step S55). If the special symbol is changing, the display control board 80 is used to set a command transmission request indicating a stopped symbol of the left and right middle symbol (step S57).

When the symbol is being changed when the power is turned off, the display control CPU 101 receives a command indicating a stop symbol of the left and right middle symbol when the gaming state return timer times out. Display control CPU 101
When the command indicating the stop symbol of the left and right middle symbol is received, for example, the variable display of the left and right middle symbol is displayed on the variable display section 9 without restarting the variable display of the symbol. The display control C
When the PU 101 receives a command indicating the stop of symbol fluctuation or a display control command indicating the end of the big hit game sent from the main board 31 thereafter, the PU 101 returns to the normal display control according to these commands.

When the display control CPU 101 receives the command indicating the left and right middle symbols, the symbols may be displayed on the variable display section 9 immediately or at the end of the original symbol variation period ( For example, a stop symbol may be displayed on the variable display unit 9 when a command indicating a symbol confirmation timing is received from the game control means. Further, in the case where the stop symbol is displayed at the end of the original symbol fluctuation period, the game control means may send a command indicating a left and right middle symbol stop symbol at the end of the original symbol fluctuation period. .

If the special symbol process flag stored in the backup RAM area indicates, for example, "all symbol stop waiting processing" at the time of power restoration, the CPU 56 of the main board 31 returns to that state. However, the display control CPU 101 continues to display the variable display result without performing the symbol variation control in the current variation. Therefore, the player can easily recognize that the power failure has been restored by displaying the variable display result. When the variable display result is a big hit (when the lottery result performed before the power failure is a big hit), the variable control result is continuously displayed, and then both the game control unit and the display control unit set the big hit. Since the game state can be restored, no disadvantage is given to the player.

The backup process of the necessary data based on the output signal of the power monitoring means for detecting an unexpected power interruption such as a power failure is performed by the main board 31, the display control board 80, the audio control board 70, the lamp control board 35, and the prize. Ball control board 37
May be performed on all the substrates, or may be performed on some substrates that require such control. For example, the backup may be made only by the main board 31. Further, when there is another control board having a game device control unit for controlling the game device, data backup processing based on the output signal of the power supply monitoring unit may be performed for those other control boards.

In the case where there is a gaming machine control unit that is not backed up, the gaming control unit sends a command necessary for matching the gaming machine control unit with the gaming state after returning to the gaming state. Is also good. For example, if the display control means is not backed up,
When returning to the game state in which the special symbol is changing when the power is restored, the game control means sends again, for example, a command indicating the pattern change mode and a command indicating the stop symbol to the display control means. When it is desired to display the variation display result without restarting the symbol variation, for example, a command indicating a stopped symbol is transmitted again.

[0231]

As described above, according to the present invention, the gaming machine has a return data table in which data for the gaming control means to return the gaming state to the state before power-off is set. When the power is restored, the game state is returned to the state before the power was turned off by using the return data table. Therefore, when an unexpected power loss such as a power failure occurs, the game control means sets the return data table. It is possible to instruct each of the gaming machine control means to restart the game based on the data of the game device, and to prevent a shift in control timing between the game control means and the game device control means when the game is restarted. This has the effect of smoothly restarting the game.

When the game control means is configured to return the game state to the state at the start of the change of the identification information when the power is restored when the game state at the time of power-off is changing the identification information, Is re-executed from the beginning, and a game restart that is easy for the player to understand can be realized.

If the return data table is configured to store data that can be converted from a game state in which the identification information is changing to a game state at the start of the change in the identification information, the game control means can easily identify the game state. Since it is possible to return to the state at the start of the information fluctuation, it is possible to facilitate the realization of the game restart that is easy for the player to understand.

If the display state of the variable display unit when the power is turned off is changing the identification information, the display device is returned to the initial state when the power is restored. If the game is configured to start the change of the identification information after that, the game state such as the display state once returns to the initial state, so that the game does not suddenly resume when the power is restored. Etc. can easily recognize that the game has been resumed.

If the game state at the time of power-off is fluctuating identification information, the game control means returns the game state to the state at the time of power-off when power is restored, and controls the display of the variable display section. An error command is sent to the game device control means, and when the game device control means receives the error command, the error control command is displayed during the variable display period. Without changing the command transmission method from the device to the gaming device control means,
The game state can be returned.

If the game state when the power is turned off is the identification information fluctuating, the game control means controls the display control of the variable display section when the power is restored, and displays the display result of the identification information to the game apparatus control means. Is transmitted, and the gaming machine control means is configured to display the display result of the identification information without restarting the change in the variable display unit in response to receiving the command indicating the display result of the identification information. In such a case, at the time of restoration from a power failure, the game state can be restored only by giving the display result of the already determined and stored identification information to the gaming device control means, and performing complicated return control. The game can be restarted without any action.

When the return data table is restored when the power is restored,
If the command to be sent to each of the plurality of gaming machine control means is stored so as to be recognizable, the gaming control means can easily instruct each gaming machine control means to restart the game. . That is, it is possible to easily prevent the timing deviation of the control restart.

In the case where the game control means is configured to return to the state when the power is restored, when the game state when the power is turned off is a big hit game and the special winning opening is being opened. Does not cause a disadvantage to the player and does not return to the state at the time of opening the first big winning opening, so that there is no disadvantage to the game store.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is a front view of the gaming board of the pachinko gaming machine as viewed from the front.

FIG. 3 is a rear view of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a block diagram showing a circuit configuration example of a game control board (main board).

FIG. 5 is a block diagram illustrating a circuit configuration example of a display control board.

FIG. 6 is a block diagram illustrating a circuit configuration example of an audio control board.

FIG. 7 is a block diagram illustrating a circuit configuration example of a lamp control board.

FIG. 8 is a block diagram showing a circuit configuration example of a winning ball control board.

FIG. 9: C for power supply monitoring and power supply backup
FIG. 3 is a block diagram illustrating a configuration example around a PU.

FIG. 10 is a block diagram illustrating a configuration example of a power supply board.

FIG. 11 is a block diagram showing a power supply board having another configuration together with a control board.

FIG. 12 is a flowchart showing the operation of the basic circuit on the main board.

FIG. 13 is a flowchart showing an interrupt process of the CPU of the main board.

FIG. 14 is a flowchart illustrating a system check process in a main process.

FIG. 15 is an explanatory diagram for describing a backup parity data creation method.

FIG. 16 is an explanatory diagram showing a configuration example of a table set in a ROM of a basic circuit on a main board.

FIG. 17 is an explanatory diagram illustrating a configuration example of a display control command.

FIG. 18 is an explanatory diagram illustrating a configuration example of display control command data.

FIG. 19 is a flowchart showing an example of a special symbol process processing program.

FIG. 20 is a flowchart illustrating display control data output processing.

FIG. 21 is a timing chart showing a state of output of display control command data.

FIG. 22 is a flowchart illustrating a main process executed by a display control CPU.

FIG. 23 is a flowchart showing a 2 ms timer interrupt process of the display control CPU.

FIG. 24 is a flowchart showing a display data reading process of the display control CPU.

FIG. 25 is a flowchart showing a display control process executed by the display control CPU.

FIG. 26 is a flowchart showing an interrupt process of the display control CPU.

FIG. 27 is a flowchart showing initial processing executed by a display control CPU.

FIG. 28 is an explanatory diagram illustrating an example of a voice control command.

FIG. 29 is an explanatory diagram showing a bit configuration of a voice control command.

FIG. 30 is a flowchart showing an output data setting process for a voice control board and a lamp control board.

FIG. 31 is a flowchart showing a voice control command output process part of the data output process.

FIG. 32 is a timing chart showing how the voice control command data is output.

FIG. 33 is a flowchart showing a main process executed by a voice control CPU.

FIG. 34 is a flowchart showing a 2 ms timer interrupt process of the voice control CPU.

FIG. 35 is a flowchart showing a voice IC control process.

FIG. 36 is an explanatory diagram showing an example of a lamp control command.

FIG. 37 is an explanatory diagram showing a bit configuration of a lamp control command.

FIG. 38 is a flowchart showing a ramp control command output processing portion of the data output processing.

FIG. 39 is a timing chart showing how the lamp control command data is output.

FIG. 40 is a flowchart showing a main process executed by a lamp control CPU.

FIG. 41 is a flowchart showing a 2 ms timer interrupt process of the lamp control CPU.

FIG. 42 is an explanatory diagram showing a bit configuration of a winning ball control command.

FIG. 43 is a timing chart showing how the award ball control command data is output.

FIG. 44 is a flowchart showing a main process executed by a winning ball control CPU.

FIG. 45 is a flowchart showing a 2 ms timer interrupt process of the winning ball control CPU.

FIG. 46 is a block diagram showing another configuration example around the CPU for power supply monitoring and power supply backup.

FIG. 47 is a block diagram showing still another configuration example around a CPU for power supply monitoring and power supply backup.

FIG. 48 is an explanatory diagram showing another configuration of the return data table.

FIG. 49 is a flowchart illustrating another example of the system check process.

FIG. 50 is a flowchart illustrating still another example of the system check process.

[Explanation of symbols]

 1 Pachinko gaming machine 31 Main board 35 Lamp control board 37 Prize ball control board 53 Basic circuit 56 CPU 70 Voice control board 80 Display control board 101 Display control CPU 351 Lamp control CPU 371 Prize ball control CPU 701 Voice control CPU 901 CPU 902 Power supply monitoring IC 910 Power supply board 916 Capacitor

Claims (8)

[Claims] 1. A gaming machine capable of performing a special game by winning a game medium in a specific winning section and controlling a game state advantageous to a player based on a result of the special game having a predetermined mode. A game control board equipped with game control means for controlling the progress of the game, a game machine control board equipped with a game machine control means for controlling a game machine provided for the game, Power supply monitoring means for monitoring a power supply voltage drop of the machine and outputting a signal to at least one of the game control means and the game device control means when a predetermined amount of voltage drop is detected; Upon receipt of the output signal, the game control means and the game device control means execute power-off processing including processing for storing data in a backup RAM capable of retaining data even when power is turned off, according to the signal. The game control means has a return data table in which data for returning a game state to a state before power-off is set, and uses the return data table to restore a game state before power-off when power is restored. A gaming machine characterized by returning to a state. 2. A display apparatus comprising: a plurality of variable display units whose display states are changeable; wherein a change of identification information displayed on each of said variable display units is started according to a condition for starting a change, and a display of each identification information is performed. A gaming machine which can be controlled to a gaming state advantageous to a player on condition that the result is a predetermined specific display mode, wherein the gaming control means is configured such that the gaming state when the power is turned off is fluctuating in identification information. 2. The gaming machine according to claim 1, wherein when the power is restored, the gaming state is returned to the state at the start of the change of the identification information. 3. The gaming machine according to claim 2, wherein the return data table stores data that can be converted from a gaming state in which the identification information is changing to a gaming state at the start of the changing of the identification information. 4. The gaming machine control means for controlling the display of the variable display section, wherein if the display state of the variable display section when the power is turned off is changing the identification information, the display state is initialized when the power is restored. The gaming machine according to claim 2, wherein the game machine returns to the state, and thereafter changes the identification information. 5. A display apparatus comprising: a plurality of variable display units whose display states are changeable, wherein a change of identification information displayed on each of said variable display units is started according to a condition for starting a change, and a display of each identification information is performed. A gaming machine which can be controlled to a gaming state advantageous to a player on condition that the result is a predetermined specific display mode, wherein the gaming control means is configured such that the gaming state when the power is turned off is fluctuating in identification information. If there is, when the power is restored, the game state is returned to the state when the power is turned off, and an error command is issued to the game device control means for controlling the display of the variable display unit using the data of the return data table. 2. The game device control means, when receiving an error command, performs an error display during the variable display period.
The gaming machine described. 6. A display device comprising: a plurality of variable display portions whose display states are changeable; wherein a change of identification information displayed on each of said variable display portions is started in accordance with satisfaction of a condition for starting a change; A gaming machine which can be controlled to a gaming state advantageous to a player on condition that the result is a predetermined specific display mode, wherein the gaming control means is configured such that the gaming state when the power is turned off is fluctuating in identification information. If there is, when the power is restored, a command indicating the display result of the identification information is transmitted to the game device control means for controlling the display of the variable display unit using the data of the return data table, The gaming machine according to claim 1, wherein the device control unit displays the display result of the identification information without restarting the change in the variable display unit in response to receiving the command indicating the display result of the identification information. 7. The gaming machine according to claim 5, wherein the return data table stores the types of commands to be sent to each of the plurality of gaming machine control means when the power is restored so as to be recognizable. 8. A game state advantageous to the player is a big hit game in which a large winning port provided on a game board is opened / closed so as to easily generate a prize, and the game control means includes: 8. The gaming machine according to claim 2, wherein if the gaming state at the time of disconnection is a jackpot game and a special winning opening is being opened, the gaming machine returns to the state when power is restored.