JP2007209471A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To appropriately recover the display state of a game machine from the abnormal state while preventing increase of the program capacity and complication of the process. <P>SOLUTION: A CPU installed in a presentation controlling microcomputer prevents the start of execution of a presentation controlling interrupt process corresponding to the occurrence of a timer interrupt by starting a loop process if the value in an event interrupt stand-by timer reaches a limit time determination value without detecting an event interrupt (the step S372: Yes). Then, if a reset signal is in the on-state based on the occurrence of the time-out without clearance of a reset IC with a watchdog, feeding of the power supply voltage to the presentation controlling microcomputer is stopped by a power control circuit, and is restarted after the elapse of prescribed time, so that the presentation controlling microcomputer is rebooted. In this case, the initial setting of a VDP is executed as when the power feeding to the game machine is started. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine or a slot machine that allows a player to play a predetermined game.

  As a gaming machine such as a pachinko machine or a slot machine, a game is performed when predetermined display information (also referred to as a display pattern) is variably displayed and the display result is a predetermined specific display result. Some are configured to be controllable to a game state advantageous to the player (for example, a specific game state such as a big hit game state, a special game state such as a big bonus or a regular bonus).

  In such a gaming machine, a predetermined character appears on a display device such as a liquid crystal display (LCD) according to the progress of the game, the character is changed, a live-action image, etc. In some cases, various game effects are performed by displaying a multicolor image of the above, outputting sound from a speaker, or blinking a light emitter such as a lamp or LED.

Here, in a gaming machine in which a display effect is executed using a drawing device that receives the transfer of image data and draws on the image display device, an arithmetic processing unit for controlling the display effect is provided from the drawing device for a predetermined time. When waiting for an interrupt signal, it has been proposed that the initial data of the drawing apparatus is reset so that the normal operation can be restored (for example, Patent Document 1).
JP-A-10-85406

  In the technique described in Patent Document 1, when the arithmetic processing unit waits for an interrupt signal from the drawing device for a predetermined time, a dedicated process is executed to reset the initial data of the drawing device. For this reason, there is a problem in that the program capacity increases and the processing when an abnormality occurs becomes complicated.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a gaming machine capable of appropriately recovering from an abnormal display state while preventing an increase in program capacity and complication of processing. To do.

  In order to solve the above problems, a gaming machine according to claim 1 of the present application is a gaming machine (for example, a pachinko gaming machine 1 or a slot machine 500) in which a player can perform a predetermined game, Image display means for displaying various images including a plurality of types of effect images (for example, image display devices 5, 510, etc.), game control means for controlling the progress of the game (for example, game control microcomputers 100, 610, etc.), Display control means (for example, an effect control board 12) including an effect control microcomputer (for example, an effect control microcomputer 120, 630) and an image processing processor (for example, VDP 141) to control the display operation of the image display means. 620, etc.), and the display control means controls the control state of the effect control microcomputer. Including data storage means (for example, a backup area of the RAM 133) for storing data necessary for aging (for example, production backup data, etc.), and the image processing processor has a predetermined function related to image display by the image display means. Completion signal output means for outputting a completion signal indicating that the processing is completed to the effect control microcomputer (for example, a portion where the moving picture decoder 158 executes the process of step S466), and the effect control The microcomputer for image processing performs initial setting of the image processing processor in response to the activation of the effect control microcomputer (for example, the part where the CPU 131 executes the effect initial setting process in step S51, etc.) ) And the processing for the image processing processor. Process command means for instructing the start of the process (for example, the part where the CPU 131 executes the process of step S364) and completion signal detection means for detecting the completion signal from the completion signal output means (for example, the CPU 131 executes the process of step S366) And the completion signal from the completion signal output means by the completion signal detection means after the instruction from the processing instruction means is transmitted. In response to the elapse of a predetermined standby period without being detected, effect control restarting means for restarting the effect control microcomputer (for example, the CPU 131 performs loop processing in response to the determination of Yes in step S372). Etc.) and the effect control restart means In response to the operation, the data saving means for storing data in the data storage means (for example, the part where the CPU 131 executes the process of step S77) and the effect control restarting means correspond to the restarting. And a restart control means for resuming the display operation of the image display means from the restored control state after restoring the control state before the restart based on the data stored in the data storage means ( For example, the CPU 131 includes a part for executing the processes of steps S324 and S325). Here, the predetermined process related to image display is, for example, a process of transferring image data used for displaying an image on the image display unit between a plurality of storage units, or reading from a predetermined storage unit. Processing the image data obtained by the above as it is or after performing a predetermined conversion such as compression or expansion, processing to write and store in another storage means, processing to display an image on the image display means based on the image data, It is predetermined as a process including at least one of various processes related to image display, such as a process of creating (drawing) image display data in the image display means using a plurality of types of image data. It only has to be done. Further, for initial setting of the image processing processor, the contents stored in a predetermined storage means included in the image processing processor are initialized, and various processing means (for example, data processing means) incorporated in the image processing processor. Initialize or interrupt the process being executed by setting, assign a storage area corresponding to the display screen of the image display means, set the display area, set the display image update period in the image display means, etc. As long as the operation includes at least one of the various initial settings, it is only necessary to be determined in advance.

  3. The gaming machine according to claim 2, wherein a power supply monitoring that outputs a voltage drop detection signal (for example, a power-off signal) in response to detecting a drop in power supply voltage supplied to the production control microcomputer. Means (for example, a power interruption detection circuit 137), and the data saving means stores data necessary for restoring the control state in response to the output of the voltage drop detection signal from the power supply monitoring means. The data is stored in the data storage means (for example, the part where the CPU 131 executes the process of step S76 in response to the determination of Yes in steps S73 and S74).

  4. The gaming machine according to claim 3, wherein the display control means includes compressed data storage means (for example, a moving image data area 142B of the CGROM 142) for storing moving image data including compressed data obtained by motion compensation predictive coding. The image processing processor includes decoding means for decoding the moving image data read from the compressed data storage means (for example, a portion where the moving image decoder 158 executes the processing of steps S461 and S462), and decoding by the decoding means. Moving image reproduction means (for example, the drawing circuit 154 includes first to X-th picture buffers 155-1 to 155) that reproduces a moving image by sequentially displaying images generated based on the moving image data on the image display means. The frame buffer memory 1 reads image data sequentially from 155-X. 6 and a portion where the display circuit 157 reads out the data stored in the frame buffer memory 156 and outputs it to the image display device 5, etc., and the completion signal output means decodes the moving image data by the decoding means. Is output to the effect control microcomputer, and the process command means instructs the decode start command means (for example, to start the process of decoding moving image data by the decode means (for example, And the effect control restarting means completes the completion signal output means by the completion signal detection means after the instruction from the decode start instruction means is sent. That the waiting period has elapsed without detection of a signal (for example, step S364) In response to the determination that Yes at step S372) after executing the process, to restart the presentation control microcomputer.

  According to a fourth aspect of the present invention, there is provided a gaming component (for example, the special symbol display device 4, the variable display device 501, the decorative members 31, 32, 33, etc.) disposed on the front or back of the image display means. The image display means includes a display area in which various images are displayed (for example, display areas 5A and 510A) and a non-display area in which display of various images is restricted corresponding to the arrangement position of the gaming parts ( The display control means includes display data storage means (for example, a frame buffer memory 156) for storing image display data in the image display means, and a display target display object. Arrangement determining means for determining whether or not an image is arranged in the non-display area (for example, the part where the drawing circuit 154 executes the process of step S444, or the CPU 13 Display data for restricting writing to the display data storage unit with respect to image data indicating an image determined to be arranged in the non-display area by the arrangement determination unit) Write restriction means (for example, a part where the process of step S445 is skipped in response to the determination of Yes in step S444, a part where the process of step S502 is not executed in response to the determination of Yes in step S501, etc.) .

  6. The gaming machine according to claim 5, wherein said display control means stores image element data storage means for storing a plurality of types of image element data including image element data corresponding to the effect image (for example, sprite data area 142A of CGROM 142). The image processing processor includes a data processing means (for example, a transfer control circuit 152 and a drawing circuit 154) that executes processing for creating display data based on image element data, and the display data storage. Display data output means (for example, a display circuit 157) that outputs display data read from the means to the image display means, and the effect control microcomputer determines the reading position and writing position of the image element data. Notifying the image processing processor and instructing to update the display image in the image display means. Display image update command means (for example, the part where the CPU 131 executes the process of step S345), and the arrangement determination means is configured such that the writing position of the image element data notified from the display image update command means is not displayed. A writing position determining means for determining whether or not the writing position corresponds to the area (for example, a portion where the drawing circuit 154 executes the process of step S444); The writing position determining unit restricts writing of image element data by the data processing unit to the writing position determined to correspond to the non-display area (for example, the drawing circuit 154 corresponds to the determination of Yes in step S424). For example, a portion skipping the processing of step S425).

  7. The gaming machine according to claim 6, wherein the display control means stores image element data storage means (for example, a sprite data area 142A of the CGROM 142) that stores a plurality of types of image element data including image element data corresponding to the effect image. The image processing processor includes a data processing means (for example, a transfer control circuit 152 and a drawing circuit 154) that executes processing for creating display data based on image element data, and the display data storage. Display data output means (for example, a display circuit 157) that outputs display data read from the means to the image display means, and the effect control microcomputer determines the reading position and writing position of the image element data. Notifying the image processing processor and instructing to update the display image in the image display means. Display image update command means (for example, a portion where the CPU 131 executes the process of step S385), and the display data writing restriction means determines that the display data write restriction means is arranged in the non-display area by the arrangement determination means The image element data indicating the element is restricted from being instructed to be written into the display data storage unit by the display image update command unit (for example, the CPU 131 performs the process of step S502 in response to the determination of Yes in step S501). Etc.)

  The present invention has the following effects.

According to the gaming machine of the first aspect, when a predetermined waiting period elapses without detection of the completion signal from the completion signal output means by the completion signal detection means after the instruction from the processing instruction means is sent. The effect control microcomputer is restarted by the effect control restarting means. In this restart, data necessary for restoring the control state is stored in the data storage means by the data saving means. As in the case where power supply to the gaming machine is started, the image processing processor is initialized by the image processing initial setting means. Further, in response to being restarted by the production control restarting means, the restart control means recovers the control state before being restarted by the stored data of the data storage means, and then from the recovered control state. The display operation of the image display means is resumed.
As a result, by diverting the process for restoring the control state at the time of restarting, it is not necessary to execute a dedicated process when the waiting period elapses without detecting the completion signal. It is possible to appropriately recover from an abnormal display state while preventing an increase or complication of processing. In addition, the display operation that has been in the middle when the completion period is not detected and the standby period elapses can be resumed after recovery, and more appropriate recovery from an abnormal display state is possible.

In the gaming machine according to claim 2, data necessary for restoring the control state by outputting a voltage drop detection signal in response to the power supply monitoring means detecting a drop in the power supply voltage is stored as data The saving unit stores the data in the data storage unit.
This eliminates the need for special control to restore the control state when the production control microcomputer is restarted, so that it can properly recover from an abnormal display state while preventing complications in processing. Can be made.

In the gaming machine according to claim 3, a completion signal indicating completion of decoding by the decoding means for decoding the moving image data is output from the image processing processor to the effect control microcomputer by the completion signal output means. Is done. Then, the production control restarting means corresponds to the fact that the waiting period has elapsed without the completion signal from the completion signal output means being detected by the completion signal detecting means after the instruction from the decoding start instruction means is sent, Restart the production control microcomputer.
As a result, even when an abnormality occurs in the decoding of the moving image data and the reproduction of the moving image is interrupted, it is possible to appropriately recover from the abnormal display state if a predetermined standby period elapses.

In the gaming machine according to claim 4, the display data writing restricting means restricts writing to the display data storing means for the image data indicating the image determined to be arranged in the non-display area by the arrangement determining means. .
Thereby, compared with the case where the image data of the image arrange | positioned at a non-display area is written in the display data storage means, the control burden in a display effect can be reduced. In addition, it is not necessary to give consideration to prevent an image from being displayed in the non-display area at the stage of designing the gaming machine, and the design burden on the gaming machine can be reduced.

In the gaming machine according to claim 5, the writing position determination determines whether or not the writing position notified from the display image update command means is a writing position corresponding to the non-display area. Then, the display data writing restricting means restricts that the data processing means writes the image element data at the writing position determined to correspond to the non-display area.
Thereby, since it is not necessary to determine whether or not it is a non-display area on the side of the effect control microcomputer, the control burden in the display effect can be reduced by the same configuration as when there is no non-display area. Can do.

In the gaming machine according to claim 6, with respect to the image element data indicating the image element determined to be arranged in the non-display area by the arrangement determination means, the display image update instruction means writes to the display data storage means. This is restricted by the display data writing restriction means.
As a result, since it is not necessary for the image processing processor to determine whether or not it is a non-display area, it is possible to reduce the control burden in the display effect with the same configuration as when there is no non-display area. it can.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a front view of a pachinko gaming machine 1 according to the present embodiment, and shows an arrangement layout of main members. The pachinko gaming machine (gaming machine) 1 is roughly composed of a gaming board (gauge board) 2 constituting a gaming board surface and a gaming machine frame (base frame) 3 for supporting and fixing the gaming board 2. The game board 2 is formed with a substantially circular game area surrounded by guide rails. Above the central position of the game area, there is provided a special symbol display device 4 for displaying (variably displaying) a special symbol as identifiable identification information in a variable manner.

  Below the special symbol display device 4, an ordinary variable winning ball device 6 that forms a start winning opening is arranged. Below the ordinary variable winning ball apparatus 6, a special variable winning ball apparatus 7 that forms a large winning opening and an ordinary symbol display apparatus 20 are provided. The normal symbol display device 20 is configured to include a light emitting diode (LED) or the like, and an execution condition is that a game ball that has passed through a passing gate 41 provided in the gaming area is detected by the gate switch 21 (FIG. 3). In the normal view game, lighting, blinking, coloring, etc. are controlled. When display is performed with a predetermined hit pattern in this normal game, the display result in the normal game is “win” (normal hit), and the movable wing piece of the electric tulip constituting the normal variable winning ball apparatus 6 is set for a predetermined time. Tilt is controlled until elapses.

  The special symbol display device 4 includes, for example, 7-segment or dot matrix LEDs. The special symbol display device 4 is, for example, “0” in a special game as a variable display game that is performed based on the fact that a start condition is established by winning a game ball in a start winning opening formed by the normal variable pay ball device 6. ”To“ 9 ”are variably displayed special symbols composed of numbers and the like. Each special symbol is assigned a symbol number corresponding to each special symbol, for example, the same number as the number indicated by each symbol. The special symbol display device 4 variably displays more types of symbols such as numbers indicating “00” to “99” in order to make it difficult for the player to grasp a specific stop symbol. It may be configured as follows.

  In the special symbol game performed by the special symbol display device 4, when a predetermined time elapses after the variation of the special symbol is started, the fixed special symbol that is a variable symbol display result is stopped (derived display). At this time, if a special symbol (big hit symbol) is stopped and displayed as a confirmed special symbol in the special symbol game on the special symbol display device 4, it becomes a “big hit” as a specific display result, and a special symbol other than the big bonus symbol is displayed. If it is stopped, it will be “lost”. When the variable display result in the special figure game becomes “hit”, the game is controlled to the big win game state as the specific game state by opening and closing the opening / closing plate of the special variable winning ball apparatus 7. In the pachinko gaming machine 1 according to this embodiment, as a specific example, a special symbol indicating “7” is a jackpot symbol, and a special symbol indicating other numerical values is a lost symbol.

  In the jackpot gaming state based on the special symbol indicating “7” which is a jackpot symbol as a confirmed special symbol in the special symbol game by the special symbol display device 4, by the opening / closing plate of the special variable winning ball device 7, A game ball that drops on the surface of the game board 2 during a predetermined opening period (for example, 29 seconds) or a period until a predetermined number (for example, 10) of winning balls are generated and the large winning opening is opened. Is received, and it becomes possible to enter the grand prize opening, and then the round is closed by closing the grand prize opening. The round as the open / close cycle can be repeated up to a predetermined upper limit number (for example, 15 rounds). The game balls that have won the big prize opening are detected by the count switch 24 (FIG. 3), and a predetermined number (for example, “15”) of prize balls are paid out based on the detection result. Thus, the big hit gaming state is a gaming state that is more advantageous for the player than the normal gaming state. The normal gaming state is a gaming state other than the big hit gaming state, such as an initial setting state immediately after power-on of the pachinko gaming machine 1, for example.

  An image display device 5 is disposed on the front surface of the game board 2 so as to cover almost the entire game area. Here, “substantially the entire surface” refers to a region on the inner side of the decorative members 31, 32, 33, etc. provided at least at the peripheral edge of the game region. The image display device 5 may be any device that is configured using, for example, an LCD panel, an organic EL (Electro Luminescence) panel, or the like, and performs screen display by a dot matrix method using a large number of pixels (pixels). For example, on the display screen of the image display device 5, each is identified by a variable display unit as a display area divided into three corresponding to the special symbol variable display in the special symbol game by the special symbol display device 4. A variable display that displays a variety of possible decorative patterns in a variable manner is performed. In this example, variable display portions “left”, “middle”, and “right” are arranged on the image display device 5, and decorative symbols are variably displayed on each variable display portion. Then, when the change of the special symbol in the special symbol display device 4 is started, the change of the decorative symbol (for example, the change of the symbol) is performed on each of the “left”, “middle”, and “right” variable display portions in the image display device 5. When the confirmed special symbol is stopped and displayed as a variable display result of the special symbol on the special symbol display device 4, the “left”, “middle”, and “right” on the image display device 5 are started. By stopping the display of the decorative pattern that becomes the confirmed decorative pattern in each variable display section, the combination of the decorative pattern that is the variable display result is stopped and displayed (derived display).

  In each of the “left”, “middle”, and “right” variable display sections provided on the display screen of the image display device 5, for example, symbols indicating numbers “1” to “8” are displayed variably. . In each of the “left”, “middle”, and “right” variable display portions, the decorative symbols are variably displayed by displaying or deleting the symbols indicating the numbers in a predetermined order. More specifically, the symbols indicating the numbers “1” to “8” may be displayed in order, and the symbols indicating the number “1” may be displayed following the symbols indicating the number “8”.

  When a big hit is generated in which a big hit symbol is derived and displayed as a confirmed special symbol in the special symbol game by the special symbol display device 4, the decorative display variable display result on the image display device 5 is “left”, “middle”, The same decorative design is stopped and displayed on each “right” variable display section. Therefore, as a result of variable display of the decorative symbols in the image display device 5, after the same decorative symbols are stopped and displayed on the “left”, “middle”, and “right” variable display portions, the pachinko gaming machine 1 is a big hit The game state will be controlled.

  The image display device 5 is provided with a special symbol start memory display area for displaying the number of reserved memories (the number of special figure reserved memories) as the number of effective winning balls won in the start winning opening formed by the normally variable winning ball apparatus 6. It may be. In the special symbol start memory display area, a winning display is performed in response to an effective start winning when the special figure reservation storage number is less than a predetermined upper limit value (for example, “4”). As a specific example, when 1 is added to the special figure reservation storage number, one of the display parts that is normally blue (for example, the leftmost display part among the display parts that are blue) is displayed in red. Change. Further, when 1 is subtracted from the special figure reserved storage number, one of the display parts displayed in red (for example, the display part at the right end of the display part in red) is returned to blue display. Alternatively, in the special symbol start storage display area, a number indicating the special figure reserved memory number may be displayed so that the player or the like can recognize the special figure reserved memory number. Further, a display (special symbol start memory display) for displaying the number of special symbol hold memories may be provided separately from the special symbol start memory display area arranged in the display area of the image display device 5.

  On the screen of the image display device 5, for example, as shown in FIG. 2, a display area 5A where various images are displayed and a non-display area 5B where image display is restricted are provided. For example, an arrangement portion on the front surface of the special symbol display device 4, an arrangement portion on the back surface of the decorative members 31, 32, 33 provided on the peripheral portion of the game area, and an arrangement on the back surface of the gaming machine frame 3 outside the game area The part is not provided with a liquid crystal for displaying an image, a member constituting the liquid crystal (for example, a polarizing plate), a circuit for controlling the liquid crystal, etc., and remains transparent without displaying an image physically. The non-display area 5B. On the other hand, on the back surface of the display area 5A, for example, a backlight that irradiates the display area 5A from behind, a concealing member that conceals the interior of the pachinko gaming machine 1, and the like are provided.

  The normal variable winning ball apparatus 6 is an electric tulip-type accessory (ordinary normal) having a pair of movable wing pieces that are controlled by a solenoid 81 (FIG. 3) between a vertical (normally open) position and a tilt (enlarged open) position. It has an electric accessory) and forms a start winning opening. The game ball that has entered the start winning opening formed in the normal variable winning ball apparatus 6 is detected by the start opening switch 22 (FIG. 3), and an execution condition (starting condition) for executing the special game based on the detection. ) Holds. Based on the detection of the game ball by the start port switch 22, a predetermined number (for example, four) of prize balls are paid out.

  The special variable winning ball apparatus 7 includes an opening / closing plate that opens and closes a large winning opening serving as a winning area by a solenoid 82 (FIG. 3). The opening / closing plate is in a state in which the big prize opening is closed at a normal time, for example, before the big hit gaming state occurs after the power of the pachinko gaming machine 1 is turned on. On the other hand, when a big hit gaming state is achieved based on the variable display result in the special symbol game by the special symbol display device 4, the big winning opening is opened by the solenoid 82 for a predetermined period or until a predetermined number of winning balls are generated. After closing. Here, out of the game balls led to the back of the game board 2 after winning the big winning opening and entering one area (V winning area; special area) is detected by the V winning switch 23 (FIG. 3). A game ball that is detected by the count switch 24 and enters the other area may be detected by the count switch 24 as it is. In this case, a solenoid for switching the route in the special winning opening may be provided on the back of the game board 2. Then, in each round other than the final round in the big hit gaming state, the detection of the game ball by the V winning switch 23 may be a condition for shifting to the next round. Alternatively, without providing the V winning area, it is possible to always shift to the next round in each round other than the final round in the big hit gaming state.

  In addition to the above configuration, the surface of the game board 2 is provided with a windmill with a built-in lamp, an outlet, and the like. Speakers 8L and 8R as sound effect generators for reproducing and outputting sound effects and the like are provided at the left and right upper positions of the gaming machine frame 3. Further, a game effect lamp 9 as an electric decoration member is provided in the periphery of the game area. A decorative LED included in the electric decoration member may be installed around each structure (for example, the normal variable winning ball device 6 or the special variable winning ball device 7) in the game area of the pachinko gaming machine 1. A hitting operation handle (operation knob) operated by a player or the like to launch a game ball is provided at a lower right position of the gaming machine frame 3.

  Various control boards such as a power supply board 10, a main board 11, and an effect control board 12 as shown in FIG. 3 are mounted on the pachinko gaming machine 1. Between the main board 11 and the effect control board 12, a signal relay board 13 for relaying various control signals transmitted from the main board 11 to the effect control board 12 is also provided. In addition, the pachinko gaming machine 1 may be provided with various boards such as a payout control board, a launch control board, and an interface board.

  The power supply board 10 is installed independently of each control board such as the main board 11 and the effect control board 12, and generates a voltage used by each control board and mechanism component in the pachinko gaming machine 1. For example, the power supply board 10 generates AC24V, VLP (DC + 24V), VSL (DC + 30V), VDD (DC + 12V), VCC (DC + 5V), and VBB (DC + 5V). The power supply board 10 includes, for example, a transformer circuit, a DC voltage generation circuit, and a power supply monitoring circuit. Further, the power supply substrate 10 may be provided with a clear switch that outputs a clear signal in response to a predetermined operation such as a pressing operation, or a capacitor that serves as a backup power supply. In addition, the power supply board 10 may be provided with a power switch for executing or cutting off the power supply to each control board and the mechanical components in the pachinko gaming machine 1. Alternatively, the power switch may be provided outside the power supply board 10 in the pachinko gaming machine 1.

  The main board 11 shown in FIG. 3 is a main-side control board, and various circuits for controlling the progress of the game in the pachinko gaming machine 1 are mounted. The main board 11 is mainly addressed to a sub-side control board composed of a random number setting function used in a special game, a function of inputting a signal from a switch or the like disposed at a predetermined position, and an effect control board 12. A function of outputting and transmitting a control command as an example of command information as a control signal, a function of outputting various information to a hall management computer, and the like are provided. The main board 11 controls the special symbol display on the special symbol display device 4 by controlling the lighting / extinction of each segment constituting the special symbol display device 4, while the normal symbol display device 20 is turned on. By controlling the blinking / coloring control, the normal symbol display on the normal symbol display device 20 is controlled. The main board 11 includes, for example, a game control microcomputer 100, a switch circuit 101 that receives detection signals from various switches for game ball detection and transmits them to the game control microcomputer 100, and the game control microcomputer 100. A solenoid circuit 102 that outputs a drive signal for each of the solenoids 81 and 82 according to the command is mounted.

  As shown in FIG. 3, wiring for receiving detection signals from the gate switch 21, the start port switch 22, the V winning switch 23, and the count switch 24 is connected to the main board 11. Note that the gate switch 21, the start port switch 22, the V winning switch 23, and the count switch 24 may have any configuration that can detect a game ball as a game medium, such as a sensor. That's fine. In addition, the main board 11 is provided with wiring for transmitting a command signal for performing tilt control of the movable blade piece in the normal variable winning ball apparatus 6 to the solenoid 81 and opening / closing control of the opening / closing plate in the special variable winning ball apparatus 7. A wiring for transmitting a command signal for performing the operation to the solenoid 82 is connected. Furthermore, the main board 11 is connected to a wiring for transmitting a command signal for performing display control of the special symbol display device 4 and the normal symbol display device 20.

  A control signal output from the main board 11 toward the effect control board 12 is relayed by the signal relay board 13. The main board 11 is provided with a main board side connector corresponding to, for example, the signal relay board 13, and an output buffer circuit is connected between the main board side connector and the game control microcomputer 100. The output buffer circuit can pass a signal only in the direction from the main board 11 to the effect control board 12 via the signal relay board 13 and prevents the signal from being input from the signal relay board 13 to the main board 11. Therefore, there is no room for signals to be transmitted from the production control board 12 or the signal relay board 13 side to the main board 11 side.

  The signal relay board 13 may be provided with a transmission direction regulating circuit for each wiring for transmitting a control signal output from the main board 11 to the effect control board 12, for example. Each transmission direction regulating circuit includes a diode having an anode connected to the main board connector corresponding to the main board 11 and a cathode connected to the presentation control board connector corresponding to the presentation control board 12, and one end connected to the cathode of the diode. And a resistor having the other end connected to the ground (GND). With this configuration, each transmission direction regulating circuit can prevent signals from being input from the effect control board 12 to the signal relay board 13 and pass signals only in the direction from the main board 11 to the effect control board 12. . Therefore, there is no room for signals to be transmitted from the production control board 12 side to the main board 11 side. In order to prevent unauthorized input of signals to the main board, a one-way data transfer means that restricts only the signal output from the main board to the sub board between the main board and the sub board has already been proposed. (See, for example, JP-A-8-224339). However, since there is nothing that regulates signal input to the main board between the main board and the one-way data transfer means, it is possible to input illegal signals to the main board by modifying the one-way data transfer means. Was possible. In this embodiment, a transmission direction regulating circuit is provided for each wiring for transmitting a control signal in the signal relay board 13, and an output buffer is provided between the game control microcomputer 100 and the main board side connector on the main board 11. By providing the circuit, it is possible to more reliably prevent an illegal signal input from the outside to the main board 11.

  The control command transmitted from the main board 11 to the effect control board 12 via the signal relay board 13 is an effect control command transmitted as an electric signal, for example. The effect control command includes, for example, a display control command used to control an image display operation in the image display device 5, a voice control command used to control sound output from the speakers 8L and 8R, and a game effect lamp 9 And a lamp control command used for controlling the lighting operation of the decorative LED and the like. FIG. 4 is an explanatory diagram showing an example of the contents of the effect control command used in this embodiment. The effect control command has, for example, a 2-byte structure, and the first byte indicates MODE (command classification), and the second byte indicates EXT (command type). The first bit (bit 7) of the MODE data is always “1”, and the first bit of the EXT data is “0”. The command form shown in FIG. 4 is an example, and other command forms may be used. In this example, the control command is composed of two control signals. However, the number of control signals constituting the control command may be one or a plurality of three or more.

  In the example shown in FIG. 4, the command 80XXh is a variable display start command that is transmitted when the special symbol display device 4 starts the variable symbol special symbol display in the special symbol game. XXh indicates an unspecified hexadecimal number, and may be a value arbitrarily set according to the instruction content by the effect control command. In the variable display start command, for example, different EXT data is set corresponding to a variable display pattern of a special symbol or a decorative symbol. In this embodiment, a plurality of types of normal losing patterns are prepared as variable display patterns for deriving and displaying a definitive decorative symbol of a losing combination without the decorative symbol variable display mode becoming reach. Also, a plurality of reach patterns are prepared as variable display patterns for deriving and displaying a definite decorative combination of a big hit combination or a lost combination after setting the variable display mode of the decorative design as reach.

  Here, the reach means that a decorative display (referred to as a reach variation pattern) that has not yet been derived and displayed when the decorative pattern derived and displayed by the image display device 5 forms a part of the jackpot combination is a variable display. It is a display mode that is being performed, or a display mode in which all or some of the decorative symbols are synchronously displayed while constituting all or part of the jackpot symbol. Specifically, on the combination effective line that has not been stopped yet when the symbols constituting the predetermined jackpot combination are stopped and displayed on some of the variable display portions on the predetermined combination effective line. Display mode in which variable display is performed in the variable display section (for example, “left”, “right” variable display sections among the “left”, “middle”, “right” variable display sections provided in the display area Is a display mode in which a variable display part of “medium” is still in a variable display state while a part of the jackpot symbol (for example, a decorative symbol indicating the number “7”) is stopped and displayed, or A display mode in which all or part of the decorative symbols on the variable display portion on the effective line are synchronously displayed while constituting all or part of the jackpot symbol (for example, “left” provided in the display area) , Fluctuate in all of the “middle” and “right” variable displays It shows a display manner in variable display is being performed manner which state is performed have all the same decoration pattern be displayed). In addition, during the reach, unusual effects may be performed with lamps or sounds. This production is called reach production. Further, during the reach, the image display device 5 displays a character (an effect display imitating a person or the like, which is different from the decorative design), changes the display mode of the background, or changes the decorative design. The display mode may be changed. This change in character display, background display mode, and decorative pattern variation mode is referred to as reach effect display.

  The command 90XXh is a display result notification command indicating the type of variable display result of special symbols and decorative symbols. In the display result notification command, for example, the display result of the decorative symbol that is stopped and displayed as an execution result of the variable display of the decorative symbol, for example, is a normal loss that is lost instead of reaching, or is lost after reaching reach Different EXT data is set in accordance with the type of display result, such as whether it is a reach loss or a big hit after reaching reach.

  The command A000h is a big hit start command indicating that the big hit gaming state is started when a big hit is made in the special symbol game by the special symbol display device 4 or the variable display of the decorative symbols on the image display device 5. The command A1XXh is a jackpot round number notification command indicating the number of rounds started in the jackpot gaming state. Command B000h is a jackpot end command indicating that the jackpot gaming state is ended.

  FIG. 5 is a diagram illustrating a configuration example of the game control microcomputer 100 mounted on the main board 11. A game control microcomputer 100 shown in FIG. 5 is, for example, a one-chip microcomputer, and includes a CPU (Central Processing Unit) 111, a ROM (Read Only Memory) 112, a RAM (Random Access Memory) 113, and a random number circuit 114. And an input / output port 115. The CPU 111 reads the user program and data stored in the ROM 112, and uses the RAM 113 as a work area to perform a control operation according to the program.

  In the main board 11, the random number circuit 114 generates all or a part of various random numbers used on the main board 11 side. For example, on the main board 11 side, a random number value for jackpot determination, a random number value for ordinary hit determination, a random value for reach determination, a random value for variable display pattern determination, or the like is used. In order to enhance the gaming effect, random numbers other than these may be used on the main board 11 side. All or part of the numerical data indicating these random numbers may be counted by the random number circuit 114. Further, numerical data indicating a part of these random number values may be counted by updating by software using a random counter different from the random number circuit 114 by the CPU 111.

  The random number value for jackpot determination is a random value used for determining whether or not the pachinko gaming machine 1 is in the jackpot gaming state due to occurrence of the jackpot. That is, the random number value for determining the big hit is used to determine whether the type of display result in the special display game by the special symbol display device 4 or the variable display of the decorative symbols in the image display device 5 is a big hit or a loss. Used for. The random number value for determining the normal hit is a random value used for determining whether or not the display result of the normal symbol game by the normal symbol display device 20 is “win”. The reach determination random number value is a random value used for determining whether or not the variable display mode of decorative symbols is to be reached. The random number value for variable display pattern determination is a random number value for display that is used to determine a variable display pattern of a special symbol or a decorative symbol as one of a plurality of types prepared in advance.

  In addition to the game control user program, the ROM 112 stores various data tables used for controlling the progress of the game. For example, the ROM 112 stores table data constituting a plurality of determination tables and determination tables prepared for the CPU 111 to make various determinations and determinations. As a determination table, a big hit determination table referred to for determining whether or not a variable display result is a big hit with a confirmed special symbol in a special figure game as a big hit symbol, or a display result in a normal figure game is set to “win”. Ordinary hit determination table referred to determine whether or not the variable symbol display mode of the special symbol or decorative symbol is lost when the variable symbol display result of the special symbol or decorative symbol is lost. The reach determination table to be used is included.

  The big hit determination table is a loss determination value indicating that the random number for determining the big hit matches the big hit determination value data indicating that the display result of the special figure game is a big hit or the display result of the special figure game is lost. What is necessary is just to be comprised from the setting data etc. which can determine whether it corresponds with data. In the normal hit determination table, the random number for determining the normal hit matches the normal hit determination value data indicating that the display result of the normal game is “win”, or the display result of the normal game is “lost”. What is necessary is just to be comprised from the setting data etc. which can determine whether it corresponds with the loss determination value data which show doing. The reach determination table can determine whether the reach determination random number value matches the reach determination value data indicating that the variable display mode of the decorative design is reached, or the normal loss determination value data that is not reached It only has to be configured from setting data to be set.

  In the determination table stored in the ROM 112, a fixed special symbol determination table for determining a fixed special symbol to be derived and displayed as a variable display result in a special symbol game, or a variable display pattern of a special symbol or a decorative symbol is determined. The variable display pattern determination table is included.

  The variable display pattern determination table is, for example, selection data that enables selection of a variable display pattern based on a random display pattern determination random number value by associating each variable display pattern with a random display pattern determination random value. And so on. The data indicating each variable display pattern in the variable display pattern determination table is, for example, in the variable display pattern determination table or in a variable display pattern setting table different from the variable display pattern determination table. It only needs to be associated with data indicating the total variable display time, control data set as EXT data by the variable display start command, and the like.

  The RAM 113 is provided with an area for holding various data used for controlling the gaming state and the like in the pachinko gaming machine 1. For example, in the RAM 113, as a special figure storage unit, a normal diagram storage unit, a confirmed special symbol storage unit, a game control flag setting unit, a game control timer setting unit, a game control counter setting unit, a game control buffer setting unit, etc. It is only necessary to provide an area for holding various data.

  Although the special figure holding storage unit has an execution condition for executing the special figure game by the special symbol display device 4 when the game ball enters (wins) the start winning opening formed by the normally variable winning ball device 6, On-hold information relating to a special figure game in which a start condition for starting variable display is not satisfied due to reasons such as executing a conventional special figure game is stored. For example, the special figure holding storage unit associates with the holding number in the order of winning to the start winning opening, and shows the random value for jackpot determination extracted from the random number circuit 114 or the like by the CPU 111 based on the establishment of the execution condition by the winning. Numerical data is stored as pending data, and stored until the number reaches a predetermined upper limit (eg, “4”).

  The normal diagram holding storage unit stores the previous normal diagram game although the execution condition for the normal symbol display device 20 to execute the normal diagram game is satisfied when the game ball passes through the passing gate 41 provided in the game area. On-hold information relating to a normal game in which a start condition for starting variable display is not satisfied due to reasons such as being executed is stored. For example, the normal diagram hold storage unit associates with the hold numbers in the order in which the game balls have passed through the passing gate 41, and for normal hit determination extracted from the random number circuit 114 or the like by the CPU 111 based on the establishment of the execution condition by the passage. Is stored as pending data, and the number is stored until the number reaches a predetermined upper limit (eg, “4”).

  The confirmed special symbol storage unit stores data indicating a confirmed special symbol derived and displayed as a variable display result in a special symbol game by the special symbol display device 4. The game control flag setting unit stores data for setting a plurality of types of flags that are set or cleared in accordance with the gaming state in the pachinko gaming machine 1, signals transmitted from various switches via the switch circuit 101, and the like. Remember. The game control timer setting unit stores data indicating a plurality of types of timer values used for game control in the pachinko gaming machine 1. The game control counter setting unit stores data indicating a plurality of types of count values used for game control in the pachinko gaming machine 1. The game control buffer setting unit temporarily stores various data used for game control in the pachinko gaming machine 1. The circuit used for flag setting and counter / timer may be constituted by a register circuit provided separately from the RAM 113.

  The input / output port 115 includes an input port for taking in various signals transmitted to the game control microcomputer 100 and an output port for transmitting various signals to the outside of the game control microcomputer 100. Has been.

  The effect control board 12 shown in FIG. 3 is a sub-side control board independent of the main board 11, receives a control command transmitted from the main board 11 via the signal relay board 13, and receives the image display device 5. In addition, various circuits for controlling electric parts for production such as the speakers 8L and 8R and the game effect lamp 9 are mounted. That is, the effect control board 12 has predetermined electrical components for effects such as display operation in the image display device 5, sound output operation from the speakers 8L and 8R, and lamp lighting operation and extinguishing operation in the game effect lamp 9. It has a function of determining the control content for executing the rendering operation.

  The effect control board 12 is connected to wiring for transmitting video signals to the image display device 5 and wiring for transmitting drive signals to the speakers 8L and 8R and the game effect lamp 9. As shown in FIG. 3, the effect control board 12 includes an effect control microcomputer 120, a display control unit 121, a sound control unit 122, a lamp control unit 123, a reset IC 124 with a watchdog, and a power control circuit. 125 is mounted.

  FIG. 6 is a diagram illustrating a configuration example of the effect control microcomputer 120 mounted on the effect control board 12. 6 also shows a reset IC 124 with a watchdog and a power control circuit 125 mounted on the effect control board 12. 6 is configured using, for example, a one-chip microcomputer, and includes a CPU 131, a ROM 132, a RAM 133, a random number circuit 134, an input / output port 135, a reset / interrupt controller 136, and the like. And a power interruption detection circuit 137. The CPU 131 reads the user program and data stored in the ROM 132 and uses the RAM 133 as a work area to perform a control operation according to the program.

  In the effect control board 12, the random number circuit 134 generates all or a part of various random numbers used on the effect control board 12 side. For example, on the side of the effect control board 12, a random value for determining a definite decorative design, a random value for determining a notice, or the like is used. In order to enhance the effect, a random value other than these may be used on the effect control board 12 side. All or part of the numerical data indicating these random numbers may be counted by the random number circuit 134. Further, a part of numerical data indicating these random numbers may be counted by updating by software using a random counter different from the random number circuit 134 by the CPU 131.

  The random number value for determining the fixed decorative design is a random value used for determining the fixed decorative design that is derived and displayed as the display result in the variable display of the decorative design. The random number value for determining the notice determines whether or not to execute a notice effect for notifying that the variable display result of special symbols or decorative symbols will be a big hit, or that the variable display mode of decorative symbols will be reached. It is a random value used to determine the mode of the notice effect when it is determined and executed.

  The ROM 132 stores, for example, data constituting a plurality of types of decorative symbol determination tables, a notice determination table, and an effect control pattern table as data for determining the control operation by the CPU 131. The decorative symbol determination table is a table used to determine a fixed decorative symbol that is derived and displayed as a variable display result of the decorative symbol in the image display device 5 based on a random value for determining the fixed decorative symbol. The notice determination table is a table used for determining whether or not a notice effect is to be executed, a notice pattern indicating a form of the notice effect when it is executed, and the like based on a random number value for determining a notice.

  As a specific example of the effect control pattern table, an effect control pattern table 201 having a configuration as shown in FIG. 7 is used in this embodiment. This effect control pattern table 201 shows the contents of various effect controls such as the contents of the display operation in the image display device 5, the contents of the sound output control of the speakers 8L, 8R, etc., the contents of the effects by the game effect lamp 9, etc. A plurality of types of data are stored as production control patterns. Each of the plurality of types of effect control patterns stored in the effect control pattern table 201 is, for example, as shown in FIG. 8, effect control timer setting values, effect control timer determination values # 1 to #n (n is an arbitrary natural number), The image display device 5 is composed of various data for controlling the production operation, such as display control data # 1 to #n, audio control data # 1 to #n, and lamp control data # 1 to #n. The contents of various effects control, such as the contents displayed on the screen, the contents of audio output from the speakers 8L and 8R, the contents of effects by the game effect lamp 9, and the switching timing of the effects control are set.

  The effect control pattern table 201 stores, for example, a plurality of types of effect control patterns corresponding to the effect operation within a period in which the decorative display variable display is executed on the image display device 5. In addition, the effect control pattern corresponding to the effect operation in the period controlled to the big hit gaming state is also stored in the effect control pattern table 201.

  The RAM 133 provided in the effect control microcomputer 120 shown in FIG. 6 is provided with an area for holding various data used for controlling the effect operation. For example, in the RAM 133, a confirmed decorative symbol storage unit, an effect control flag setting unit, an effect control timer setting unit, an effect control counter setting unit, an effect control buffer setting unit, a variable display pattern storage unit, a display result storage unit, a special figure hold An area for holding various data may be provided as a storage number storage unit, a round number storage unit, a notice pattern storage unit, and the like. At least a part of the RAM 133 is a backup RAM that is backed up by a backup power source created in the power supply substrate 10. That is, even if the power supply to the effect control microcomputer 120 is stopped or the effect control microcomputer 120 is restarted, at least part of the contents of the RAM 133 is saved for a predetermined time.

  The confirmed decorative symbol storage unit stores data indicating a fixed decorative symbol that is derived and displayed as a variable display result in the variable display of decorative symbols on the image display device 5. The effect control flag setting unit sets a plurality of types of flags that are set or cleared according to the effect operation state such as the display state of the image display device 5, the effect control command transmitted from the main board 11, and the like. Store the data. The effect control timer setting unit stores data indicating a plurality of types of timer values used for effect control such as display control on the image display device 5, for example. The effect control counter setting unit stores data indicating a plurality of types of count values used for effect control such as display control on the image display device 5, for example. The circuit used for flag setting and counter / timer may be constituted by a register circuit provided separately from the RAM 133.

  The effect control buffer setting unit is provided with an effect-side reception command buffer for temporarily storing commands from the main board 11 received by the effect control board 12. The variable display pattern storage unit stores data that can specify the variable display pattern notified from the main board 11 by storing, for example, EXT data in the variable display start command. The display result storage unit stores data that can specify the type of the display result notified from the main board 11 by storing, for example, EXT data in the display result notification command. The special figure reserved memory number storage unit stores data that can specify the special figure reserved memory number notified from the main board 11. The round number storage unit stores data that can specify the round number in the big hit gaming state notified from the main board 11 by storing, for example, EXT data in the big hit round number notification command. The notice pattern storage unit stores data that can specify the notice pattern determined to execute the notice effect display.

  The effect control microcomputer 120 has an input / output port 135 for inputting various signals transmitted to the effect control microcomputer 120 and for transmitting various signals to the outside of the effect control microcomputer 120. Output port. For example, from the output port of the input / output port 135, a display control command transmitted to the display control unit 121, a voice control command transmitted to the sound control unit 122, and a lamp control transmitted to the lamp control unit 123. Commands are output. The output port of the input / output port 135 includes an output terminal for outputting a clear signal for initializing the reset IC 124 with watchdog. The input port of the input / output port 135 includes an input terminal for inputting a power supply voltage supplied from the power control circuit 125. Note that the power supply voltage supplied from the power control circuit 125 may be input to a dedicated power supply terminal different from the input / output port 135.

  The reset / interrupt controller 136 is for controlling various reset and interrupt requests generated inside or outside the production control microcomputer 120. Resets controlled by the reset / interrupt controller 136 include system resets and user resets. The system reset is a reset that occurs when a low level signal is input to a predetermined system reset terminal for a certain period. User resets include a low level signal input to a predetermined user reset terminal for a certain period of time, an out-of-designated area prohibition (IAT) signal, or an interval reset signal. The reset is caused by a predetermined factor.

  The interrupts controlled by the reset / interrupt controller 136 include four types of interrupts: X class interrupt (XIRQ), I class interrupt (IRQ), software interrupt (SWI), and illegal opcode trap (ILGOP). . The X class interrupt is an interrupt that occurs when a low level signal is input to a predetermined XIRQ terminal for a certain period. An I class interrupt is an interrupt that can allow / prohibit acceptance of an interrupt request by a user program. A low level signal is input to a predetermined IRQ terminal for a certain period, or an interrupt request signal from a predetermined timer circuit. This is an interrupt generated by various predetermined interrupt factors such as occurrence of an interrupt, an interrupt request signal from a predetermined communication circuit, and the like.

  The power interruption detection circuit 137 monitors the power supply voltage supplied from the power supply substrate 10 via the power control circuit 125, and notifies the CPU 131 and the like of the occurrence of power interruption when a decrease in the power supply voltage is detected. Is. For example, when the power supply voltage drops below a predetermined power interruption determination value, the power interruption detection circuit 137 turns on a power interruption signal indicating the occurrence of power interruption. On the other hand, when the power supply voltage is higher than the power interruption determination value, the power interruption signal is turned off. The power-off signal output from the power-off detection circuit 137 is transmitted to the CPU 131, for example, and used to check whether or not a power-off has occurred.

  The display control unit 121 shown in FIG. 3 controls the display operation in the image display device 5 based on a display control command from the effect control microcomputer 120. For example, the display control unit 121 performs control for executing variable display of decorative symbols and various effect displays by causing the image display device 5 to perform switching display of images.

  FIG. 9 is a block diagram illustrating a hardware configuration example of the display control unit 121. As illustrated in FIG. 9, the display control unit 121 includes a VDP 141 (Video Display Processor) and a CGROM (Character Generator ROM) 142. The VDP 141 has, for example, a high-speed drawing function and a display output function for displaying an image on the image display device 5, and executes image processing in accordance with a display control command from the effect control microcomputer 120. The CGROM 142 stores various image data used for displaying an image on the image display device 5. The image data stored in the CGROM 142 includes a plurality of types of image element data corresponding to a plurality of types of effect images indicating a plurality of types of decorative designs, and a plurality of types of moving images corresponding to a plurality of types of effect images different from the decorative symbols. Image data is included.

  As shown in FIG. 9, the VDP 141 includes a host interface 151, a transfer control circuit 152, a CGROM interface 153, a drawing circuit 154, a temporary storage memory 155, a frame buffer memory 156, a display circuit 157, a moving image Decoder 158.

  The host interface 151 includes an address input terminal and a data input / output terminal for exchanging various data with the production control microcomputer 120. The transfer control circuit 152 controls the transfer of the image element data read from the CGROM 142 to the temporary storage memory 155 based on a display control command from the effect control microcomputer 120. For example, the transfer control circuit 152 includes a DMA device for performing data transfer from the CGROM 142 to the temporary storage memory 155 using DMA (Direct Memory Access) transfer.

  The CGROM interface 153 includes an address output terminal and a data input terminal for reading image element data stored in the CGROM 142. The drawing circuit 154 executes a drawing process for creating image display data in the image display device 5 based on the image element data temporarily stored in the temporary storage memory 155. The drawing circuit 154 sequentially reads out the picture data decoded by the moving picture decoder 158 from the first to Xth picture buffers 155-1 to 155-X (FIG. 10) provided in the temporary storage memory 155. By writing the data in the frame buffer memory 156, it is possible to reproduce a moving image by sequentially displaying images generated based on the moving image data on the image display device 5.

  The temporary storage memory 155 is configured using, for example, a VRAM (Video RAM) or the like, and temporarily stores image element data and moving image data read from the CGROM 142. For example, the temporary storage memory 155 stores the first to Xth pictures in order to temporarily store a plurality of picture data reproduced by the moving picture decoder 158 decoding the moving picture data read from the CGROM 142. Storage areas serving as buffers 155-1 to 155-X (X is an arbitrary natural number) are provided.

  The frame buffer memory 156 is configured using, for example, a VRAM or the like different from the temporary storage memory 155, and stores image display data created by a drawing process or the like by the drawing circuit 154. For example, the frame buffer memory 156 has a storage capacity larger than the capacity of the image data used for displaying an image in the display area for one screen in the image display device 5. In the frame buffer memory 156, in order to facilitate address management, for example, as shown in FIG. 11, in the display data area for storing display data, not only the display area 5A on the screen of the image display device 5 but also the non-display area. An address is also assigned to the display area 5B.

  The display circuit 157 shown in FIG. 9 uses the display data read from the frame buffer memory 156 as gradation data, generates a scanning signal based on a predetermined clock signal, and outputs it to the image display device 5. This is a circuit for displaying an image on the screen of the display device 5.

  The moving image decoder 158 decodes moving image data by reading out moving image data stored in the CGROM 142 in a state where the data is compressed by, for example, motion compensation predictive coding, and executing a predetermined expansion process. .

  FIG. 12 is a diagram illustrating specific examples of various commands serving as display control commands transmitted from the CPU 131 included in the effect control microcomputer 120 to the VDP 141. As shown in FIG. 12, in this embodiment, commands such as a transfer display command, a moving image decoding start command, a moving image decoding NOP command, and the like are transmitted from the CPU 131 to the VDP 141 as display control commands.

  The transfer display command causes the image element data stored in the CGROM 142 or the image element data temporarily stored in the temporary storage memory 155 to be written in the frame buffer memory 156 and the image element indicated by the image element data is displayed. This is a command for instructing display on the screen of the image display device 5. For example, the transfer display command is data for notifying the VDP 141 of the read address of the image element data in the CGROM 142 or the temporary storage memory 155, the write address of the image element data in the frame buffer memory 156, the data amount of the image element data, and the like. Is included.

  In place of the read address of the image element data in the CGROM 142 or the temporary storage memory 155, for example, identification information attached to the effect image indicated by the image element data to be read (for example, the character number of the effect character indicated by the image element data) Any information that makes it possible to specify the reading position of the image element data read from the CGROM 142 or the temporary storage memory 155 may be used. Further, instead of the writing address of the image element data in the frame buffer memory 156, the frame buffer memory 156 such as the display coordinates of the image elements on the screen of the image display device 5 (for example, the display coordinates at the upper left of the image elements), Arbitrary information that makes it possible to specify the writing position of the image element data in may be used.

  The moving image decoding start command is a command for instructing the moving image decoder 158 included in the VDP 141 to start decoding moving image data. The moving picture decoding NOP command is a command for instructing the moving picture data decoder 158 included in the VDP 141 to wait for decoding moving picture data (NOP; No OPeration).

  The CGROM 142 is for storing various image element data and moving image data used for displaying various effect images including decorative designs on the image display device 5. FIG. 13 is a diagram illustrating an example of an address map in the CGROM 142. As shown in FIG. 13, the CGROM 142 has a sprite data area 142A that is an area for storing image element data for sprite drawing and moving image data that is an area for storing encoded moving image data. An area 142B is provided. In this embodiment, the storage area from the address SPSTA to the address SPEND in the CGROM 142 is set in the sprite data area 142A. In addition, a storage area from the address MVSTA to the address MVEND in the CGROM 142 is set in the moving image data area 142B.

  The moving image data stored in the moving image data area 142B is data-compressed by motion compensated prediction encoding, and has a stream configuration as shown in FIG. 14, for example. In the moving image data area 142B, a plurality of types of moving image data are stored, for example, in a state where they are stored in one moving image file for each type of game effect of one unit by moving images. Each moving image file includes a file header, at least one frame header, and compressed data for each frame. For example, compressed data for one frame is classified as either an I picture, a P picture, or a B picture, and information for identifying the type of any picture and the display order of each picture are specified in the frame header. Information to be included. An I picture is a picture that has been encoded by intraframe encoding. The P picture is a picture that performs forward motion compensation prediction using only past frames. A B picture is a picture that performs bi-directional motion compensation prediction using both past and future frames.

  The sound control unit 122 shown in FIG. 3 controls the sound output operation in the speakers 8L and 8R based on the sound control command from the production control microcomputer 120. For example, the sound control unit 122 includes an audio output circuit that generates an audio signal corresponding to an audio control command from the production control microcomputer 120 and outputs the audio signal to the speakers 8L and 8R, and the like.

  The lamp control unit 123 controls the lighting operation, the extinguishing operation, the blinking operation, and the like in the game effect lamp 9 and the like based on a lamp control command from the effect control microcomputer 120. For example, the lamp control unit 123 generates a lamp drive signal corresponding to the lamp control command from the effect control microcomputer 120 and supplies the lamp drive signal to the game effect lamp 9, various decorative lamps, and an electric decoration member such as an LED. Includes a lamp driver circuit that performs lighting operation, extinguishing operation, blinking operation, and the like.

  Note that the sound control unit 122 and the lamp control unit 123 may be mounted on a predetermined control board installed outside the effect control board 12.

  The reset IC 124 with a watchdog is a reset IC with a built-in watchdog circuit. The reset IC with watchdog 124 counts up or down the timer value of the watchdog circuit in response to, for example, a rising edge or a falling edge of a predetermined clock signal. Then, the timer value of the watchdog circuit is initialized in response to the clear signal transmitted from the production control microcomputer 120 being turned on.

  Here, the time that can be measured by the watchdog circuit, that is, the time until the timer value of the watchdog circuit is up-counted or down-counted from the initial value to the final value is determined by the effect control microcomputer 120. It is set to be longer than the cycle in which a timer interrupt for control occurs. When the CPU 131 periodically executes interrupt processing corresponding to the occurrence of the timer interrupt in the effect control microcomputer 120, the clear signal transmitted from the effect control microcomputer 120 is periodically turned on. Therefore, the timer value never reaches the final value. On the other hand, when the interrupt processing corresponding to the occurrence of the timer interrupt is not normally executed by the CPU 131, the clear signal is not turned on, so that the timer value reaches the final value. Thus, when the timer value of the watchdog circuit reaches the final value and times out, a predetermined reset signal is output as an ON state and input to the power control circuit 125.

  The power control circuit 125 is a circuit for delivering the power supply voltage supplied from the power supply board 10 to each part on the effect control board 12. In this embodiment, the reset signal output from the reset IC with watchdog 124 is input to the power control circuit 125. When the reset signal is turned on, the power control circuit 125 stops the supply of the power supply voltage to the effect control microcomputer 120 until a predetermined time has elapsed, and then restarts the supply of the power supply voltage. . The production control microcomputer 120 stops its operation when the supply of the power supply voltage from the power control circuit 125 is stopped, and starts the supply of power to the pachinko gaming machine 1 when the supply of the power supply voltage is resumed. Start again in the same way as The reset IC with watchdog 124 and the power control circuit 125 are provided as circuits for switching whether the power supply voltage supplied from the power supply board 10 is delivered to each part in the production control microcomputer 120 or cut off. It may be built in the control microcomputer 120.

  Next, the operation (action) of the pachinko gaming machine 1 in this embodiment will be described. In the main board 11, when power supply from the power supply board 10 is started, the game control microcomputer 100 is activated, and the CPU 111 executes a game control main process as shown in the flowchart of FIG. When the game control main process shown in FIG. 15 is started, first, interrupt prohibition is set (step S1), and an interrupt mode is set (step S2). For example, in step S2, the value (1 byte) of the specific register (I register) of the gaming control microcomputer 100 and the interrupt vector (1 byte: the least significant bit is “0”) output from the built-in device are synthesized. Sets the interrupt mode for maskable interrupts that generate interrupt addresses. When a maskable interrupt is generated, the game control microcomputer 100 is automatically set to be in an interrupt disabled state, and the contents of the program counter may be saved in the stack.

  Subsequently, settings relating to the stack pointer such as setting of a stack pointer designation address are performed (step S3). The built-in device register in the game control microcomputer 100 is set (initialized) (step S4). Then, CTC (counter / timer) and PIO (parallel input / output port) which are built-in peripheral circuits in the game control microcomputer 100 are set (initialized) (step S5). Thereafter, the RAM 113 is set to be accessible (step S6).

  Following the process of step S6, the CPU 111 determines whether or not a clear switch provided on, for example, the power supply board 10 in the pachinko gaming machine 1 is in an on state (step S7). At this time, the CPU 111 may confirm the state of the clear switch only once, but may confirm it a plurality of times. For example, if it is confirmed once that the clear switch is in the OFF state, the state of the clear switch is confirmed once after a predetermined time (for example, 0.1 second) has elapsed. At this time, if the clear switch is in an off state, it is determined that the clear switch is in an off state. On the other hand, if the clear switch is on at this time, the state of the clear switch may be confirmed again after a predetermined time has elapsed. It should be noted that the number of times of reconfirming the state of the clear switch may be one time or a plurality of times. Further, it is possible to check twice and check again when the check results do not match.

  When the clear switch is OFF in step S7 (step S7; No), it is determined whether or not there is predetermined backup data in the backup area of the RAM 113 (step S8). For example, in the process of step S8, the CPU 111 determines whether or not a backup flag provided in a game control flag setting unit of the RAM 113 is on. At this time, if the backup flag is on, it is determined whether or not the stored data is normal by calculating a checksum of the stored data in a predetermined area of the RAM 113. Determine that there is backup data. On the other hand, if the backup flag is off or the stored data is not normal, it is determined that there is no backup data.

  If it is determined in step S8 that there is backup data (step S8; Yes), the CPU 111 restores the game state for returning the internal state of the game control microcomputer 100 to the state when the power supply is stopped. Is performed (step S9). Then, for example, by setting the saved value of the program counter stored in the backup area of the RAM 113 in the program counter, the process returns to the process corresponding to the address.

  If the clear switch is on in step S7 (step S7; Yes), or if it is determined in step S8 that there is no backup data (step S8; No), the RAM 113 is cleared and initialized. At the same time (step S10), the sub-board such as the effect control board 12 is initialized (step S11). At this time, the internal state of the game control microcomputer 100 is also cleared to the initial state.

  Thereafter, the CPU 111 sets an interrupt (step S12). For example, in the process of step S12, the CPU 111 controls the progress of the game every predetermined time (for example, 2 milliseconds) by setting the CTC register based on the interrupt initial setting data stored in the ROM 112. To generate a timer interrupt. Further, in the process of step S12, priority may be set in a plurality of types of interrupt processing corresponding to a plurality of types of interrupt factors by setting a predetermined register.

  After executing the process of step S12, the interrupt is prohibited (step S13), the main random number value update process is executed (step S14), the interrupt is permitted (step S15), and a series of processes are repeatedly executed. To do. The main random number update process executed in step S14 is a process for updating all or part of the random values used on the main board 11 side by software.

  FIG. 16 is a flowchart showing an example of a game control interrupt process executed by the CPU 111 each time a timer interrupt for controlling the progress of the game is generated in the game control microcomputer 100. When a maskable interrupt such as a timer interrupt occurs, the CPU 111 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack. When the game control interrupt process shown in FIG. 16 is started, the CPU 111 first saves the internal register (step S20), and then executes a predetermined switch process to input from each switch via the switch circuit 101. The state of the detection signal is determined (step S21). Subsequently, a main random number update process similar to step S14 in FIG. 15 is executed (step S22). Next, for example, a start winning process is executed based on the execution result of the switch process in step S21 (step S23). In the start winning process, a big hit determination is made in response to the detection of a game ball winning at the start winning opening formed by the normally variable winning ball apparatus 6 when the start winning signal from the start opening switch 22 is turned on. The numerical data indicating the random number value for use is extracted from the random number circuit 114 or the like and stored in the special figure holding storage unit of the RAM 113.

  Following the start winning process, the CPU 111 executes a special symbol process (step S24). In the special symbol process, the value of the special symbol process flag provided in the game control flag setting unit of the RAM 113 is updated according to the progress of the game in the pachinko gaming machine 1 to control the display operation in the special symbol display device 4. Various processes are selected and executed in order to set the special winning opening / closing operation in the special variable winning ball apparatus 7 in a predetermined procedure. Following the special symbol process, the normal symbol process is executed (step S25). The CPU 111 executes normal symbol process processing to control display operations (for example, lighting and extinguishing of LEDs) in the normal symbol display device 20, and to perform variable display of normal symbols (for example, lighting and blinking) and the like. Setting of tilt control of the movable blade piece in the normal variable winning ball apparatus 6 is enabled.

  Further, the CPU 111 causes the main board 11 to transmit a control command to a sub-board such as the effect control board 12 by executing a command control process (step S26). For example, in the command control process, it is determined whether or not a transmission command is stored in various transmission command buffers provided in the game control buffer setting unit of the RAM 113. Read data. Then, transmission of a control command to the sub-board is controlled by setting read data to a predetermined output port provided in the input / output port 115, for example. After that, by executing a predetermined information output process, for example, data such as jackpot information, starting information, probability variation information supplied to a hall management computer installed outside the pachinko gaming machine 1 is output (step S27). ).

  Subsequently, the CPU 111 executes predetermined solenoid output processing to control the tilting of the movable blade piece in the normal variable winning ball device 6 and open / close the opening / closing plate in the special variable winning ball device 7 when a predetermined condition is satisfied. Control is performed (step S28). Thereafter, by executing predetermined prize ball processing, the number of prize balls is set based on the detection signal input from each switch, and the payout control command can be output to the payout control board (step S29). ). Then, the contents of the register saved in step S20 are restored (step S30), the interrupt is permitted (step S31), and the game control interrupt process is terminated.

  FIG. 17 is a flowchart showing an example of processing executed in step S24 shown in FIG. 16 as special symbol process processing. In the special symbol process shown in FIG. 17, the CPU 111 executes the following steps S100 to S106 according to the value of the special symbol process flag provided in the game control flag setting unit of the RAM 113.

  The special symbol normal process in step S100 is executed when the value of the special symbol process flag is “0”. This special symbol normal process is a process for determining whether or not to start a special symbol game by the special symbol display device 4 based on numerical data indicating a random number value for jackpot determination stored in the special symbol storage unit of the RAM 113. Etc. The variable display start process in step S101 is executed when the value of the special symbol process flag is “1”. In the variable display start process, a process for setting a fixed special symbol that is stopped and displayed as a variable symbol display result of the special symbol in the special symbol game by the special symbol display device 4 and a variable symbol display pattern for the special symbol and the decorative symbol are determined. Includes processing. In the variable display start process, for example, by setting the control data corresponding to the confirmed special symbol in the effect transmission command buffer also received by the game control buffer setting unit of the RAM 113, the effect control board 12 is controlled. Configure settings for sending display result notification commands. In addition, in the variable display start process, for example, a variable display start command is sent to the effect control board 12 by setting control data corresponding to the variable display pattern of special symbols and decorative symbols in the effect transmission command buffer. Configure settings for sending.

  The variable display control process of step S102 is executed when the value of the special symbol process flag is “2”. This variable display control process includes a process of measuring the remaining variable display time in the special figure game by the special symbol display device 4 based on the timer value in the variable display timer provided in the game control timer setting unit of the RAM 113. It is out. The variable display stop process in step S103 is executed when the value of the special symbol process flag is “3”. In the variable display stop process, the special symbol display device 4 derives and displays the confirmed special symbol and ends the variable symbol variable display.

  The pre-opening process for the special winning opening in step S104 is executed when the value of the special symbol process flag is “4”. In the special winning opening opening pre-processing, for example, setting for transmitting a big hit start command to the effect control board 12 is performed by setting predetermined control data in the effect transmission command buffer. Further, the pre-opening process for the big winning opening includes an initialization process in the big hit operation such as opening and closing the big winning opening by the opening / closing plate of the special variable winning ball apparatus 7. The special winning opening opening process in step S105 is executed when the value of the special symbol process flag is “5”. This process during the opening of the special prize winning opening is performed in various processes related to the big hit operation such as opening / closing the big winning prize opening by the opening / closing plate of the special variable winning prize ball apparatus 7 or once in the big prize opening formed by the special variable winning ball apparatus 7. It includes processing to check the opening time. Further, in the special winning opening opening process, it is determined whether or not the big hitting operation by the special variable winning ball device 7 is finished, and if it is finished, the value of the special symbol process flag is updated to “6”. The jackpot end process in step S106 is executed when the value of the special symbol process flag is “6”. The jackpot end process includes a process of setting for transmitting a jackpot end command to the effect control board 12 by setting predetermined control data in the effect transmission command buffer, for example.

  Next, the operation in the effect control board 12 will be described. In the effect control board 12, when the power supply voltage is supplied from the power supply board 10, the effect control microcomputer 120 is activated, and the CPU 131 executes an effect control main process as shown in the flowchart of FIG. When the effect control main process shown in FIG. 18 is started, the CPU 131 first executes a predetermined effect initial setting process (step S51).

  FIG. 19 is a flowchart showing an example of the effect initial setting process executed in step S51 of FIG. In the effect initial setting process, the CPU 131 first sets the interrupt prohibition (step S301) and sets the interrupt mode (step S302). For example, in step S302, the value (1 byte) of the specific register (I register) of the production control microcomputer 120 and the interrupt vector (1 byte: the least significant bit is “0”) output from the built-in device are synthesized. Sets the interrupt mode for maskable interrupts that generate interrupt addresses.

  Subsequently, settings relating to the stack pointer, such as setting of a stack pointer designation address, are performed (step S303). In addition, the built-in device register in the production control microcomputer 120 is set (initialized) (step S304). Then, CTC (counter / timer) and PIO (parallel input / output port), which are built-in peripheral circuits in the production control microcomputer 120, are set (initialized) (step S305). Thereafter, the RAM 133 is set to be accessible (step S306).

  Thereafter, initial setting of the VDP 141 is performed, for example, a predetermined initialization signal is transmitted to the VDP 141 and then initial setting data for setting in the internal register of the VDP 141 is transmitted (step S307). At this time, in the VDP 141, for example, the storage contents of the temporary storage memory 155 and the frame buffer memory 156 are initialized based on the initialization signal and the initial setting data received from the effect control microcomputer 120, the transfer control circuit 152, A display area (for example, an actual area) is initialized or interrupted by the drawing circuit 154 or the moving picture decoder 158 or assigned to a storage area in the frame buffer memory 156 corresponding to the display screen of the image display device 5. A process for performing at least one of various setting operations such as setting a display area, a virtual display area, or the like, or setting a display image update period in the image display device 5 may be executed. Further, for example, by setting the operation of the random number circuit 134 based on the random number initial setting data stored in the ROM 132, the setting for generating the random value used on the side of the effect control board 12 is performed (step S308). . Further, for example, after setting the interrupt by setting the reset / interrupt controller 136 or the CTC register based on the interrupt initial setting data stored in the ROM 132 (step S309), the effect initial setting process is performed. finish.

  In the setting in step S309, for example, by setting the CTC register, the production control microcomputer 120 generates a timer interrupt for controlling the production operation every predetermined time (for example, 2 milliseconds). . In addition, in the setting in step S309, the priority order of interrupt processing to be executed corresponding to various interrupt factors generated in the effect control microcomputer 120 is set. In this embodiment, for example, as shown in FIG. 20, the priority of interrupt processing (command reception interrupt processing) corresponding to a command reception interrupt that occurs when an effect control command transmitted from the main board 11 is received is the highest. Next, an interrupt process corresponding to a power interruption check timer interrupt for monitoring the occurrence of power interruption by the production control microcomputer 120 (production side power interruption check interruption process), an effect for controlling the production operation The priority order of each interrupt process is determined so as to be the order of the interrupt process (effect control interrupt process) corresponding to the control timer interrupt.

  Following the effect initial setting process as described above, the CPU 131 restores the control state in the effect control board 12 such as the internal state of the effect control microcomputer 120 to the state when the power supply is stopped. Is executed (step S52 in FIG. 18).

  FIG. 21 is a flowchart showing an example of the effect control restoration process executed in step S52 of FIG. In this effect control restoration process, the CPU 131 first checks the data in the RAM 133 and determines whether or not the check result is normal (step S321). In the process of step S321, for example, a checksum is calculated using data stored in a predetermined area of the RAM 133, and the checksum calculated and a check stored in the effect checksum buffer provided in the effect control buffer setting unit of the RAM 133 are calculated. Compare with Sam. Here, the effect checksum buffer stores a checksum calculated by the same processing when the power supply was stopped last time. This effect checksum buffer is included in the backup area of the RAM 133 backed up by the backup power source, and the contents of the effect checksum buffer are stored for a predetermined period even when the power supply is stopped. If the comparison result between the calculated checksum and the checksum stored in the effect checksum buffer does not match, the data in the predetermined area of the RAM 133 is different from the data when the power supply is stopped. Is determined to be not normal.

  If the check result in step S321 is normal (step S321; Yes), it is determined whether or not the effect backup flag provided in the effect control flag setting unit of the RAM 133 is on (step S322). The state of the effect backup flag is set in the effect control flag setting unit when the power supply is stopped. And the state of the production backup flag is preserved even when the power supply is stopped by backing up the set location of the production backup flag by the backup power source. In the process of step S322, for example, if “55H” is set as the value of the effect backup flag in the effect control flag setting unit, it is determined that there is a backup (ON state). On the other hand, if a value other than “55H” is set, it is determined that there is no backup (OFF state). Note that the determination as to whether or not the effect backup flag is turned on as in step S322 is performed prior to the determination of the check result as in step S321, and the data check of the RAM 133 is performed when the effect backup flag is turned on. You may make it determine whether a result is normal.

  When the effect backup flag is on in step S322 (step S322; Yes), after clearing the effect backup flag to turn it off (step S323), the CPU 131 changes the internal state of the effect control microcomputer 120, and the like. Setting at the time of recovery for returning to the state when the power supply is stopped is performed (step S324). As a specific example, in the process of step S324, first, the start address of the backup setting table stored in the ROM 132 is set as a pointer, and the contents of the backup setting table are sequentially set in the work area in the RAM 133. To do. Here, when the work area of the RAM 133 is backed up by a backup power source, it is only necessary to set initialization data for an area that may be initialized in the work area in the backup setting table. Subsequently, the production backup data for restoring the control state is read from the backup area of the RAM 133 backed up by the backup power source, and the settings of the internal register of the CPU 131 and the work area of the RAM 133 are set according to the read data. The microcomputer 120 is restored to the state before being restarted.

  Thereafter, based on the setting in step S324, the CPU 131 performs various control resumption settings in the VDP 141 by, for example, sending a command that becomes a display control command corresponding to the state after restoration to the VDP 141 (step S324). S325), the effect control restoration process is terminated. Note that after executing the process of step S325, for example, the process may be returned to the process corresponding to the saved value set in the program counter by the return of the control state in step S324.

  If the check result in step S321 is not normal (step S321; No), or if the effect backup flag is off in step S322 (step S322; No), the RAM 133 is initialized (step S326). ). Subsequent to the process of step S326, after setting for initialization to set the internal state of the effect control microcomputer 120 to the initial state (step S327), the effect control restoration process is terminated.

  After performing the effect control restoration process as described above in step S52 in FIG. 18, after interrupt prohibition (step S53), the effect random number value update process is executed (step S54), and the interrupt is permitted. (Step S55), a series of processing is repeatedly executed. The effect side random number value update process executed in step S54 is a process for updating all or part of the random number values used on the effect control board 12 side by software.

  In the effect control microcomputer 120, for example, the effect control flag setting unit of the RAM 133 is provided with interrupt flags corresponding to various interrupts. Instead of such an interrupt flag, an interrupt register built in the CPU 131 may be used. When various interrupts occur in the production control microcomputer 120, for example, an interrupt flag corresponding to the type of interrupt generated by the reset / interrupt controller 136 is set to an on state. At this time, the reset / interrupt controller 136 sets an interrupt signal for notifying the CPU 131 of the occurrence of an interrupt to an on state. In the CPU 131, when an interrupt that can be masked is generated, if the interrupt is permitted, the CPU 133 produces an effect control flag setting unit of the RAM 133 in response to the interrupt signal from the reset / interrupt controller 136 being turned on. The cause of the interrupt that occurred is specified by checking the respective interrupt flags provided in. When a plurality of types of interrupt factors are generated at the same time, the interrupt processing corresponding to the generated interrupt factors is executed from the one set so as to have a higher priority.

  For example, the effect control microcomputer 120 generates an interrupt for receiving an effect control command from the main board 11 separately from a timer interrupt that occurs every time a predetermined time elapses. This interruption is generated when, for example, an effect control INT signal from the main board 11 is turned on. When an interrupt occurs due to the turn-on of the effect control INT signal, the command reception interrupt flag is turned on, and the CPU 131 automatically sets the interrupt disabled state and saves the contents of the built-in registers such as the program counter in the stack. To do.

  In response to the interrupt generated when the effect control INT signal from the main board 11 is turned on, the CPU 131 executes a predetermined command reception interrupt process, for example. In this command reception interrupt process, after the command reception interrupt flag is cleared and turned off, the input port included in the input / output port 135 included in the effect control microcomputer 120 is mainly connected via the signal relay board 13. A control signal serving as an effect control command is captured from a predetermined input port that receives a control signal transmitted from the substrate 11. The effect control command captured at this time is stored, for example, in an effect side reception command buffer provided in the effect control buffer setting unit of the RAM 133. As an example, when the production control command has a 2-byte configuration, the first byte (MODE) and the second byte (EXT) are sequentially received and stored in the production side reception command buffer. Thereafter, the CPU 131 restores the contents of the internal register saved in the stack and permits an interrupt, and then ends the command reception interrupt process.

  When a power interruption check timer interrupt for monitoring the occurrence of a power interruption occurs, the CPU 131 executes a production side power interruption check interrupt process as shown in the flowchart of FIG. At this time, the CPU 131 automatically sets the interrupt disabled state. In the effect-side power interruption check interrupt process shown in FIG. 22, the CPU 131 clears the power interruption check timer interrupt flag provided in, for example, the effect control flag setting unit of the RAM 133 and turns it off (step S71). At the same time, the contents of the built-in register such as a program counter are saved in the stack and saved (step S72). Thereafter, it is determined whether or not the power-off signal from the power-off detection circuit 137 is on (step S73).

  If the power-off signal is on in step S73 (step S73; Yes), it is determined whether a predetermined power-off determination time has elapsed (step S74). Here, the CPU 131 measures the elapsed time since it was first determined in step S73 that the power-off signal is in the on state. In the process of step S74, the measured elapsed time reaches the power-off determination time. What is necessary is just to determine whether it did. In this case, the measurement of the elapsed time is continued in the period in which it is determined in step S73 that the power-off signal is in the on state. In contrast, when it is determined in step S73 that the power-off signal is once off, the elapsed time measurement operation may be initialized.

  If it is determined in step S73 that the power-off signal is in an off state (step S73; No), or if it is determined in step S74 that the power-off determination time has not elapsed (step S74; No). ) After restoring the contents of the built-in register saved in step S72 (step S75), the production side power interruption check interrupt process is terminated. At this time, the CPU 131 may permit the interruption.

  If it is determined in step S74 that the power interruption determination time has elapsed (step S74; Yes), for example, data for effect backup is set using stored data in a predetermined area of the RAM 133 (step S76). . Here, for example, the control state and display control in the effect control microcomputer 120 based on the values of various flags provided in the effect control flag setting unit of the RAM 133 and the timer values of various timers provided in the effect control timer setting unit of the RAM 133. As long as the progress of various processes in the unit 121 can be specified, the production backup data may be configured by data indicating the values of these flags and timers. Further, for example, if the control state in the production control microcomputer 120 and the progress of various processes in the display control unit 121 can be specified from the stored value of a built-in register (for example, a program counter) of the CPU 131 or the like. The effect backup data may be constituted by data indicating the stored value of the built-in register. Alternatively, the effect backup data may be configured by combining data indicating the value of the flag or timer and data indicating the stored value of the built-in register. In addition, any data that can be recovered after restarting by specifying the control state in the production control microcomputer 120 and the progress of various processes in the display control unit 121 is included in the production backup data. Also good.

  Subsequent to the processing in step S76, the CPU 131 creates check data by calculating a checksum using, for example, data stored in a predetermined area of the RAM 133 (step S77). And after setting the effect backup flag provided in the effect control flag setting part of RAM133 to an ON state (step S78), access to RAM133 is prohibited (step S79). When part of the RAM 133 is backed up by a backup power source created on the power supply board 10, the effect backup data set in step S76, the check data created in step S77, and turned on in step S78. Data indicating the effect backup flag set in the state may be stored in the backup area of the RAM 133 at the end of each process. Thereafter, the CPU 131 enters a predetermined loop process and waits until the operation control microcomputer 120 stops operating.

  When an effect control timer interrupt for controlling the progress of the effect is generated in the effect control microcomputer 120, the CPU 131 executes an effect control interrupt process as shown in the flowchart of FIG. At this time, the CPU 131 automatically masks the interrupt so that the interrupt process corresponding to the interrupt factor having the same priority is not started during the execution of the effect control interrupt process. Note that even when masking is performed at this time, execution of interrupt processing corresponding to an interrupt factor having a higher priority than that of the effect control timer interrupt is permitted. When the effect control interrupt process shown in FIG. 23 is started, the CPU 131 first clears the effect control timer interrupt flag to turn it off (step S91), and saves the contents of an internal register such as a program counter in the stack. And evacuate (step S92).

  Subsequently, the CPU 131 clears the reset IC 124 with a watchdog by setting control data for turning on the watchdog clear signal in a predetermined output port included in the input / output port 135, for example (step S93). ). Next, a command analysis process for analyzing the effect control command transmitted from the main board 11 is executed (step S94). In addition, the CPU 131 executes effect control process processing (step S95). In this effect control process, various effects are produced by the display of the image display device 5, the sound output from the speakers 8L and 8R, the lighting operation of the game effect lamp 9, etc. Settings for execution are made. Then, by executing the effect side random number value update process (step S96), various random number values counted by the random number circuit 134 or the like on the effect control board 12 side are updated. Thereafter, the contents of the register saved in step S92 are restored (step S97), and the effect control interrupt process is terminated. It should be noted that when the effect control interrupt process is ended, the CPU 131 may cancel the mask.

  FIG. 24 is a flowchart showing an example of the effect control process executed in step S95 of FIG. In the effect control process shown in FIG. 24, for example, the following processes of steps S150 to S155 are executed according to the value of the effect control process flag provided in the effect control flag setting unit of the RAM 133.

  The variable display start command reception waiting process in step S150 is a process executed when the value of the effect control process flag is “0”. The variable display start command reception waiting process includes a process of determining whether or not to start variable display of decorative symbols on the image display device 5 based on whether or not a variable display start command is received from the main board 11. Contains.

  The variable display control setting process in step S151 is executed when the value of the effect control process flag is “1”. This variable display control setting process performs various effect operations including variable display of decorative symbols on the image display device 5 in response to the special symbols being variably displayed in the special symbol game by the special symbol display device 4. For example, a process for selecting a variable display pattern or a display result corresponding to the type of display result from a plurality of types of effect control patterns stored in the effect control pattern table 201 as shown in FIG. It is out.

  The variable symbol display process in step S152 is executed when the value of the effect control process flag is “2”. In this process, the CPU 131 generates presentation control data such as display control data, audio control data, and lamp control data from the presentation control pattern corresponding to the timer value in the presentation control timer provided in the presentation control timer setting unit of the RAM 133. read out. Various effects during variable display of decorative symbols, such as display control of the image display device 5, audio output control of the speakers 8L and 8R, lighting control of the game effect lamp 9, etc., according to the effect control data read at this time. Control is performed. Then, when the effect control data corresponding to the end of the variable display of the decorative design is read from the effect control pattern, a timer initial value determined in advance corresponding to the jackpot start command reception waiting time is set in the effect control timer. Thereafter, the countdown operation of the effect control timer is started, and the value of the effect control process flag is updated to “3” which is a value corresponding to the big hit start waiting process.

  The big hit start waiting process in step S153 is executed when the value of the effect control process flag is “3”. In this process, the CPU 131 determines whether or not a jackpot start command transmitted from the main board 11 has been received. Then, when the jackpot start command is received, the value of the effect control process flag is updated to “4”, which is a value corresponding to the jackpot effect process, based on the determination that the decorative symbol variable display result is the jackpot. . On the other hand, when the effect control timer times out without receiving the jackpot start command from the main board 11, the effect control process flag of the effect control process flag is determined based on the determination that the decorative symbol variable display result is lost. The value is updated to “0” which is an initial value.

  The big hit effect process of step S154 is a process executed when the value of the effect control process flag is “4”. In this process, for example, the CPU 131 controls the display operation in the image display device 5 to display an image corresponding to the jackpot gaming state, or controls the sound output operation in the speakers 8L and 8R to play the sound corresponding to the jackpot gaming state. Various effects control in the big hit gaming state is performed such that the lighting / extinguishing operation of the game effect lamp 9 is controlled to turn on / off / blink in accordance with the big hit gaming state. Then, in response to the fact that the round game executed in the big hit game state has reached the end of the final round (for example, the fifteenth round), the big hit end command transmitted from the main board 11 has been received, etc. The value of the process flag is updated to “5” which is a value corresponding to the big hit end effect process. The big hit end effect process in step S155 is executed when the value of the effect control process flag is “5”. In the jackpot end effect process, for example, the end of the jackpot gaming state is notified by displaying an image on the image display device 5, outputting sound from the speakers 8L and 8R, or lighting the game effect lamp 9. The process which controls the production | presentation operation | movement for this is included.

  FIG. 25 is a flowchart showing an example of the variable symbol display process executed in step S152 of FIG. In the symbol variable display process, the CPU 131 first updates the effect control timer value, which is a value in the effect control timer, by subtracting, for example, 1 (step S221). Then, whether or not the effect control timer value updated in step S221 matches any of the effect control timer determination values # 1, # 2,..., #N included in the effect control pattern as shown in FIG. Is determined (step S222). At this time, if it matches any of the timer determination values (step S222; Yes), display control data, sound control data, lamp control data stored in the effect control pattern corresponding to the determination value determined to match. Are read out (step S223). Then, based on the display control data read in step S223, it is determined whether or not it is the display update timing in the image display device 5 (step S224).

  If it is the display update timing in step S224 (step S224; Yes), a predetermined display update command process is executed (step S225). On the other hand, when it is not the display update timing (step S224; No), the process of step S225 is skipped. Subsequently, a voice or lamp control command corresponding to the read data in step S223 is sent (step S226).

  When it is determined in step S222 that the production control timer determination values # 1, # 2,..., #N do not match (step S222; No), after the process of step S226 is executed, for example, It is determined whether or not the read data in step S223 is a predetermined end code, or whether or not the effect control timer value updated in step S221 has reached a predetermined value (eg, “0”). As a result of the determination, it is determined whether or not it is the end timing of variable display of decorative symbols on the image display device 5 (step S227). At this time, if it is not the end timing of variable display (step S227; No), the variable symbol display process is ended.

  If it is determined in step S227 that it is the end timing of variable display (step S227; Yes), a predetermined big hit start command reception standby initial value is set in the effect control timer (step S228), and the effect control process After the flag is updated to “3” which is a value corresponding to the big hit start waiting process (step S229), the variable symbol display process is ended.

  FIG. 26 is a flowchart showing an example of the display update command process executed in step S225 of FIG. In this display update command process, the CPU 131 first specifies an image element whose display is to be updated from, for example, display control data read from the effect control pattern corresponding to the effect control timer value (step S341). Subsequently, the read address of the image element data in the sprite data area 142A of the CGROM 142 or the temporary storage memory 155 is specified from the display control data read from the effect control pattern, for example (step S342). Also, for example, the writing address of the image element data in the frame buffer memory 156 corresponding to the display position (display coordinates) of the image element is specified from the display control data read from the effect control pattern (step S343). Further, the data amount of the image element data indicating the image element to be updated is specified (step S344). Thereafter, based on the read address, write address, and data amount of the image element data specified in steps S342 to S344, a transfer display command is created and transmitted to the VDP 141 (step S345).

  After executing the process of step S345, it is determined whether or not the command for all image elements to be displayed is completed (step S346). If the command is not completed (step S346; No), the process returns to step S341. On the other hand, if the command for all the image elements to be updated is completed (step S346; Yes), the display update command process is terminated.

  FIG. 27 is a flowchart showing an example of the big hit effect process executed in step S154 of FIG. In the jackpot effect process, the CPU 131 first determines whether or not a jackpot round number notification command transmitted from the main board 11 has been received (step S241). At this time, if the big hit round number notification command is received (step S241; Yes), for example, the big hit round number is selected from a plurality of types of production control patterns stored in the production control pattern table 201 as shown in FIG. Settings are made to control the rendering operation corresponding to the number of big hit rounds, such as reading out the corresponding rendering control pattern (step S242). If the big hit round number notification command is not received in step S241 (step S241; No), the process of step S242 is skipped.

  Subsequently, it is determined whether or not a jackpot end command transmitted from the main board 11 has been received (step S243). If a jackpot end command is received (step S243; Yes), the value of the effect control process flag is updated to “5” which is a value corresponding to the jackpot end effect process (step S244), and then the jackpot effect process is performed. Exit. On the other hand, if the big hit end command is not received in step S243 (step S243; No), the effect control timer value is updated by subtracting, for example, 1 (step S245).

  After executing the process of step S245, a moving image that displays a moving image using moving image data based on the display control data read from the effect control pattern, the effect control timer value updated in step S245, or the like. It is determined whether or not it is the display period (step S246). If it is the moving image display period in step S246 (step S246; Yes), a predetermined moving image display process is executed (step S247). On the other hand, when it is not a moving image display period (step S246; No), the process of step S247 is skipped. Thereafter, in response to the various control data read from the effect control pattern, processing for issuing other instructions related to effect control is executed (step S248), and then the big hit effect process is terminated.

  FIG. 28 is a flowchart showing an example of the moving image display process executed in step S247 of FIG. In the moving image display process, the CPU 131 first determines whether or not the image reproduced using the moving image data is the first frame image (step S361). For example, in the process of step S361, the CPU 131 newly reads out the moving image file from the presentation control timer value or the stored value of the moving image reading pointer that specifies the reading position (for example, reading address) of the moving image data in the CGROM 142. Specify whether to continue reading. When a new moving image file is read, it is determined that the image is the first frame, while when it is continuously read, it is determined that the image is not the first frame.

  If it is determined in step S361 that the image is the first frame (step S361; Yes), for example, the value of the moving image read pointer is set to a read address corresponding to the moving image file to be read. The initial setting of the register provided for moving image reproduction is performed (step S362). On the other hand, when it is determined that the image is not the first frame (step S361; No), when the previous moving image display process ends, the register saved in the process of step S369, which will be described later, is saved. The contents are restored (step S363).

  Thereafter, the CPU 131 creates a moving image decoding start command and transmits it to the VDP 141 (step S364). In addition, the CPU 131 initializes an event interruption waiting timer provided in the effect control timer setting unit of the RAM 133 and starts measuring elapsed time (step S365). Subsequently, it is determined whether or not the event interrupt flag provided in the effect control flag setting unit of the RAM 133 has been turned on (step S366). Here, the event interrupt flag is turned on in response to occurrence of an event interrupt in the moving picture decoder 158 included in the VDP 141 when the reproduction of picture data corresponding to an image for one frame is completed in the VDP 141. Set to state.

  If the event interrupt flag is on in step S366 (step S366; Yes), after clearing the event interrupt flag to turn it off (step S367), for example, a moving image stored in one moving image file Corresponding to the data, it is determined whether or not the decoding of the last frame has been completed (step S368). If it is determined in step S368 that the decoding of the final frame has not been completed (step S368; No), the contents of the register are saved (step S369), and the moving image display processing is terminated. On the other hand, when it is determined that the decoding of the final frame is completed (step S368; Yes), the process of step S369 is skipped. Thereafter, the CPU 131 creates a moving image decoding NOP command and transmits it to the VDP 141 (step S370), and then ends the moving image display processing.

  If the event interrupt flag is off in step S366 (step S366; No), the event interrupt wait timer value, which is the timer value in the event interrupt wait timer, is updated, for example, by adding 1 (step S366). S371). Then, it is determined whether or not the updated event interrupt wait timer value in step S371 has reached a predetermined time limit determination value (step S372). At this time, if the time limit determination value has not been reached (step S372; No), the processing returns to step S366. On the other hand, if it is determined in step S372 that the time limit determination value has been reached (step S372; Yes), a predetermined loop process is entered and waits until the effect control microcomputer 120 is restarted. To do.

  FIG. 29 is a flowchart showing an example of a reset / interrupt control process executed by the reset / interrupt controller 136 included in the effect control microcomputer 120. In this reset / interrupt control process, the reset / interrupt controller 136 first determines whether or not a command reception interrupt has occurred due to the reception of the effect control command transmitted from the main board 11 (step S401). At this time, if a command reception interrupt has occurred (step S401; Yes), for example, a command reception interrupt flag provided in the effect control flag setting unit of the RAM 133 is set to an on state (step S402).

  If it is determined in step S401 that a command reception interrupt has not occurred (step S401; No), for example, a power interruption check timer interrupt is generated when a predetermined CTC provided for power interruption check times out. It is determined whether or not it has occurred (step S403). At this time, if a power interruption check timer interrupt has occurred (step S403; Yes), for example, a power interruption check timer interrupt flag provided in the effect control flag setting unit of the RAM 133 is set to an on state (step S404). ).

  If it is determined in step S403 that a power interruption check timer interrupt has not occurred (step S403; No), for example, an effect control timer interrupt due to a time-out of a predetermined CTC provided for effect control Whether or not has occurred is determined (step S405). At this time, if an effect control timer interrupt has occurred (step S405; Yes), for example, an effect control timer interrupt flag provided in the effect control flag setting unit of the RAM 133 is set to the on state (step S406).

  When it is determined in step S405 that the production control timer interrupt has not occurred (step S405; No), the event interrupt is determined by determining whether or not the event interrupt signal from the VDP 141 is turned on. Whether or not has occurred is determined (step S407). At this time, if an event interrupt has occurred (step S407; Yes), for example, an event interrupt flag provided in the effect control flag setting unit of the RAM 133 is set to an on state (step S408).

  If it is determined in step S407 that no event interrupt has occurred (step S407; No), it is determined whether another interrupt has occurred (step S409). At this time, if any interrupt has occurred (step S409; Yes), a predetermined process such as setting a predetermined interrupt flag to an on state is executed in response to the generated interrupt (step S409). S410). If it is determined in step S409 that no interrupt has occurred (step S409; No), or after performing any of the processes in steps S402, S404, S406, S408, and S410, the process returns to step S401. .

  FIG. 30 is a flowchart illustrating an example of a power interruption detection process executed by the power interruption detection circuit 137 provided in the effect control microcomputer 120. In this power failure detection process, the power failure detection circuit 137 first determines whether or not the supply voltage from the power control circuit 125 to the effect control microcomputer 120 is equal to or lower than a predetermined voltage value as a power failure detection determination value. Is determined (step S421). At this time, if the supply voltage is equal to or less than the power interruption detection determination value (step S421; Yes), it is determined whether or not a predetermined power interruption occurrence determination time has elapsed (step S422). Here, the power interruption detection circuit 137 measures the elapsed time since it was first determined in step S421 that the supply voltage is equal to or lower than the power interruption detection determination value. In the process of step S422, the measured elapsed time is measured. It may be determined whether or not the power interruption occurrence determination time has been reached. In this case, the measurement of the elapsed time is continued in the period in which it is determined in step S421 that the supply voltage is equal to or less than the power interruption detection determination value. In contrast, once it is determined in step S421 that the supply voltage has exceeded the power interruption detection determination value, the elapsed time measurement operation may be initialized. If the interruption occurrence determination time is set to a minimum value (for example, “0”), the interruption occurrence determination is immediately performed when it is determined in step S421 that the supply voltage is equal to or less than the interruption detection determination value. It can be determined that time has passed.

  If it is determined in step S422 that the power interruption occurrence determination time has elapsed (step S422; Yes), the power-off signal transmitted to the CPU 131 is set to the on state (step S423). After the power-off signal is set to the on state in step S423, the on-state power-off signal is continuously output until the power-off signal is set to the off state in step S425 described later. Good. After executing the process of step S423, the process returns to the process of step S421.

  If it is determined in step S421 that the supply voltage exceeds the voltage value that is the power interruption detection determination value (step S421; No), whether or not a predetermined power interruption end determination time has elapsed is determined. Determination is made (step S424). Here, the power failure detection circuit 137 measures the elapsed time since it was first determined in step S421 that the supply voltage exceeds the power failure detection determination value. In the process of step S424, the measured progress is measured. It may be determined whether or not the time has reached the power interruption end determination time. In this case, the measurement of the elapsed time is continued in the period in which it is determined in step S421 that the supply voltage exceeds the power interruption detection determination value. In contrast, once it is determined in step S421 that the supply voltage has become equal to or less than the power interruption detection determination value, the elapsed time measurement operation may be initialized. If the power interruption end determination time is set to the minimum value (eg, “0”), the power interruption end determination time is immediately determined when it is determined in step S421 that the supply voltage has exceeded the power interruption detection determination value. It can be determined that has passed.

  If it is determined in step S424 that the power interruption end determination time has elapsed (step S424; Yes), the power-off signal transmitted to the CPU 131 is set to an off state (step S425). After the power-off signal is set to the off state in step S425, the power-off signal in the off state is continuously output until the power-off signal is set to the on state in step S423 described above. Good. When it is determined in step S424 that the power interruption end determination time has not elapsed (step S424; No), after the process of step S425 is executed, the process returns to step S421.

  FIG. 31 is a flowchart illustrating an example of sprite drawing processing executed by the transfer control circuit 152 and the drawing circuit 154 included in the VDP 141. In this sprite drawing process, first, it is determined whether or not a transfer display command transmitted from the effect control microcomputer 120 has been received (step S441). If there is no command received from the effect control microcomputer 120 (step S441; No), the process of step S441 is repeatedly executed and the system waits.

  When the transfer display command is received in step S441 (step S441; Yes), the read address of the image element data in the sprite data area 142A of the CGROM 142 or the temporary storage memory 155 is specified from the data included in the transfer display command. (Step S442). Subsequently, the writing address of the image element data in the frame buffer memory 156 is specified from the data included in the transfer display command (step S443). Then, for example, based on the write address specified in step S443, it is determined whether or not the image element data write destination in the frame buffer memory 156 is a non-display area (step S444). For example, in the process of step S444, the drawing circuit 154 matches the address assigned to the non-display area 5B on the screen of the image display device 5 in the frame buffer memory 156 by the writing address specified in step S443. If it matches, it is determined that the writing destination is a non-display area.

  If it is determined in step S444 that the writing destination is not a non-display area (step S444; No), image element data reading and writing operations are performed (step S445). For example, when the read display command of the image element data in the sprite data area 142 A of the CGROM 142 is notified by the transfer display command, the transfer control circuit 152 reads the image element data from the read address of the CGROM 142 and writes it to the temporary storage memory 155. To remember. At this time, the transfer control circuit 152 may notify the drawing circuit 154 of the storage address of the image element data in the temporary storage memory 155. Then, the drawing circuit 154 reads the image element data from the storage address of the temporary storage memory 155 notified from the transfer control circuit 152, and writes the image element data to the write address of the frame buffer memory 156 notified by the transfer display command. Create data for use. Further, for example, when the read address of the image element data in the temporary storage memory 155 is notified by the transfer display command, the drawing circuit 154 reads the image element data from the read address of the temporary storage memory 155 and notifies by the transfer display command. Display data is created by writing to the write address of the frame buffer memory 156.

  If it is determined in step S444 that the writing destination is a non-display area (step S444; Yes), the process of step S445 is skipped. Therefore, even if the transfer display command is received from the effect control microcomputer 120, the writing destination of the image element data in the frame buffer memory 156 is the writing corresponding to the non-display area 5B on the screen of the image display device 5. In the case of the position, the image element data is read from the CGROM 142 by the transfer control circuit 152 and written to the temporary storage memory 155, or the image element data is read from the temporary storage memory 155 by the drawing circuit 154. Writing to the buffer memory 156 is restricted.

  Thereafter, it is determined whether or not drawing (creation of display data) by writing image element data to the frame buffer memory 156 is completed (step S446). If not completed (step S446; No), reading is performed. After updating the address and the write address (step S447), the process returns to step S444. On the other hand, if the drawing is completed in step S446 (step S446; Yes), the process returns to step S441, and further waits until a transfer display command is received from the effect control microcomputer 120.

  In addition to the sprite drawing process as shown in the flowchart of FIG. 31, the drawing circuit 154 executes, for example, a predetermined moving image drawing process. In this moving image drawing process, the first to Xth picture buffers 155-1 to 155 provided in the temporary storage memory 155 in response to receiving the moving image decoding start command from the effect control microcomputer 120. From -X, the picture data decoded by the moving picture decoder 158 is sequentially read out and written in the frame buffer memory 156 to update the display data.

  FIG. 32 is a flowchart illustrating an example of a moving image decoding process executed by the moving image decoder 158 included in the VDP 141. In response to receiving the moving picture decoding start command from the effect control microcomputer 120, the moving picture decoder 158 starts execution of the moving picture decoding process as shown in FIG. In this moving image decoding process, first, picture data indicating a picture for one frame is read out from moving image data used for presentation stored in the CGROM 142 (step S461). The picture data is read out in an order that can be reproduced according to the order in which the picture data is arranged. Note that the playback order and the decoding order do not necessarily match. For example, a B picture is decoded after an I picture or a P picture arranged thereafter is decoded. In the process of step S461, the moving picture decoder 158 designates the reading position (for example, reading address) of the moving picture data in the CGROM 142 based on the moving picture data information used for the presentation notified from the presentation control microcomputer 120. A picture designating the value of the read pointer to be read (read pointer value) or the first to Xth picture buffers 155-1 to 155-X provided in the temporary storage memory 155 for storing the decoded picture data The buffer pointer value (picture buffer pointer value) may be set.

  After reading the picture data in step S461, the moving picture decoder 158 decodes the read data (step S462), and the decoded picture data corresponds to the first to Xth picture buffers 155 corresponding to the picture buffer pointer values. -1 to 155-X are written and stored (step S463). Subsequently, the reading pointer value is updated (step S464), the picture buffer pointer value is updated (step S465), and an event interrupt signal is output to the effect control microcomputer 120 via the host interface 151 (step S465). S466). At this time, for example, a timer for measuring the output period of the event interrupt signal is started and the signal output period is ended by determining whether or not the timer value has reached a predetermined signal output period determination value. It is determined whether or not (step S467). Alternatively, it may be determined whether or not the signal output period has ended by determining whether or not a response signal for receiving the event interrupt signal from the effect control microcomputer 120 has been received.

  When the signal output period does not end in step S467 (step S467; No), the process of step S467 is repeatedly executed and waits. On the other hand, when the signal output period has ended (step S467; Yes), the output of the event interrupt signal is stopped (step S468), and then the moving image decoding process ends.

  As described above, in the moving image decoding process, every time the decoding of the picture data indicating the picture for one frame is completed by executing the process of step S462, the process of step S466 is executed to output the event interrupt signal. I am doing so. Therefore, for example, when a failure occurs in the picture data decoding process in step S462, when the picture data decoding is not completed, the event interrupt signal is not output. In the effect control microcomputer 120, the reset / interrupt controller 136 executes the process of step S407 shown in FIG. 29, and the CPU 131 executes the process of step S366 shown in FIG. 28, whereby an event interrupt signal is output from the VDP 141. It can be determined whether or not it has been done. If it is determined in step S372 that the event interrupt signal has not been output and the event interrupt wait timer value has reached the time limit determination value (step S372; Yes), a predetermined loop process is entered.

  In the effect control microcomputer 120, when the effect control timer interrupt occurs, the CPU 131 automatically masks the interrupt, and executes the interrupt process corresponding to the interrupt factor of the same priority during the effect control interrupt process. Do not let it start. For this reason, when the CPU 131 enters the loop process based on the determination of Yes in step S372, the execution of the effect control interrupt process cannot be started thereafter.

  In the effect control interrupt process shown in the flowchart of FIG. 23, the reset IC with watchdog 124 is cleared by the process of step S93. Therefore, when the execution of the effect control interrupt process is not started and a predetermined time elapses, a timeout occurs in the reset IC with watchdog 124, and the reset signal transmitted to the power control circuit 125 is turned on. In the power control circuit 125, when the reset signal transmitted from the watchdog reset IC 124 is turned on, the supply of the power supply voltage to the effect control microcomputer 120 is stopped until a predetermined time has elapsed, Restart the voltage supply. Here, when the power control circuit 125 stops the supply of the power supply voltage, the voltage value may be lowered relatively slowly. In this way, the power control circuit 125 stops the supply of the power supply voltage to the effect control microcomputer 120, and then restarts the supply after a predetermined time has elapsed, thereby causing the effect control microcomputer 120 to operate. Reboot. As a result, for example, when a failure occurs in the decoding process of picture data by the moving picture decoder 158 of the VDP 141, an event interrupt signal is not output from the VDP 141, and a predetermined standby time elapses. The control microcomputer 120 can be restarted.

  The CPU 131 included in the effect control microcomputer 120 executes an effect initial setting process in step S51 shown in FIG. 18 in response to the activation of the effect control microcomputer 120. Then, in step S307 of the effect initial setting process shown in the flowchart of FIG. 19, by performing the initial setting of the VDP 141, for example, even if a failure occurs in the moving picture decoder 158 of the VDP 141, this is canceled and the initial setting is made It can be returned to the state.

  Thereafter, in response to the activation of the effect control microcomputer 120, the CPU 131 executes effect control recovery processing in step S52 shown in FIG. Here, in the production control microcomputer 120, the power interruption detection circuit 137 executes the power interruption detection process as shown in the flowchart of FIG. 30, and the supply voltage from the power control circuit 125 is interrupted in step S421. After the detection determination value or less (step S421; Yes), if the power interruption occurrence determination time elapses in step S422 (step S422; Yes), the power interruption signal transmitted to the CPU 131 is set to the on state. (Step S423). In the CPU 131, a production side power interruption check interrupt process as shown in the flowchart of FIG. 22 is executed. This stage-side power interruption check interrupt process has a higher priority than the production control interrupt process, so even if an interruption is masked due to the production control timer interrupt, the interruption check timer interrupt is generated. Correspondingly, its execution can be started.

  In such effect side power interruption check interrupt processing, the CPU 131 determines in step S73 that the power interruption signal transmitted from the electric interruption detection circuit 137 is on (step S73; Yes), and then proceeds to step S74. If the power interruption determination time has elapsed (step S74; Yes), a process for backing up the control state of the effect operation in the effect control microcomputer 120 is executed. That is, the CPU 131 executes the process of step S76 to restore the control state before the voltage supply to the effect control microcomputer 120 is stopped in the backup area of the RAM 133 backed up by the backup power source. Set and store the production backup data.

  In step S324 of the effect control restoration process shown in the flowchart of FIG. 21, the CPU 131 reads the effect backup data stored in the backup area of the RAM 133, whereby the effect control microcomputer 120 is restarted. Can be restored to its previous state.

  As described above, in the pachinko gaming machine 1 in the above embodiment, the event interrupt signal from the VDP 141 is turned on in step S407 of FIG. 29 by the reset / interrupt controller 136 provided in the production control microcomputer 120. The occurrence of an event interrupt is detected. In step S372 in FIG. 28, the CPU 131 provided in the effect control microcomputer 120 determines that the event interrupt wait timer value reaches the time limit determination value when the occurrence of the event interrupt is not detected by the reset / interrupt controller 136. A loop process is entered so that the execution of the effect control interrupt process corresponding to the occurrence of the effect control timer interrupt is not started. Then, because the process of step S93 shown in FIG. 23 is not executed, a timeout occurs in the reset IC with watchdog 124, and when an on-state reset signal is input to the power control circuit 125, an effect control microcomputer After the supply of the power supply voltage to 120 is stopped, the production control microcomputer 120 is restarted by restarting the supply after a predetermined time has elapsed. In this case, as in the case where power supply to the pachinko gaming machine 1 is started, the CPU 131 executes the effect initial setting process in step S51 shown in FIG. 18, and the initial VDP 141 is set in step S307 in FIG. Set up. As a result, when the occurrence of an event interrupt in the VDP 141 is not detected on the side of the effect control microcomputer 120 and a predetermined standby period has elapsed, the initial setting of the VDP 141 is performed without executing a dedicated process. It is possible to recover from an abnormal display state while preventing an increase in program capacity and complication of processing.

  Further, in the production control microcomputer 120, if the power interruption occurrence determination time elapses after the supply voltage from the power control circuit 125 becomes equal to or less than the power interruption detection determination value, the power interruption detection circuit 137 is shown in FIG. By executing the process of step S423, the power-off signal is set to the on state. The CPU 131 executes a production side power interruption check interrupt process as shown in the flowchart of FIG. 22 as an interrupt process corresponding to the power interruption check timer interrupt having a higher priority than the production control timer interrupt. If the power interruption determination time has elapsed after the power interruption signal transmitted from the electric interruption detection circuit 137 is turned on, the effect backup data is set and stored in the backup area of the RAM 133 in step S76. . When the CPU 131 executes the effect control restoration process in step S52 shown in FIG. 18 in response to the restart of the effect control microcomputer 120, it is stored in the backup area of the RAM 133 in step S324 in FIG. The control state of the production control microcomputer 120 is restored to the state before it is restarted by the production backup data. As a result, the event control occurrence in the VDP 141 is not detected on the side of the effect control microcomputer 120, and when the predetermined standby period has elapsed, the display operation that has been in progress is continued after the restart. It is possible to recover more appropriately from an abnormal display state. In addition, when the production control microcomputer 120 is restarted, it is not necessary to perform special control for restoring the control state, so that it is appropriately recovered from the abnormal display state while preventing the processing from becoming complicated. Can be made.

  In the VDP 141, after the moving picture decoder 158 performs the decoding in step S462 shown in FIG. 32, the event control signal is output to the effect control microcomputer 120 by the process in step S466. In the production control microcomputer 120, after the CPU 131 transmits a moving image decoding start command to the VDP 141 in step S364 of FIG. 28, the reset / interrupt controller 136 detects the occurrence of an event interrupt in step S407 of FIG. If the CPU 131 determines that the time limit determination value has been reached in step S372, a predetermined loop process is entered. Thereafter, based on the occurrence of a timeout in the reset IC 124 with watchdog, the power control circuit 125 stops and restarts the supply of the power supply voltage to the effect control microcomputer 120 until a predetermined time elapses, thereby producing the effect control microcomputer. 120 is restarted. As a result, even when an abnormality occurs in the decoding of the moving image data and the reproduction of the moving image is interrupted, it is possible to appropriately recover from the abnormal display state if a predetermined standby period elapses.

  On the screen of the image display device 5, for example, a non-display area 5 </ b> B in which image display is restricted is provided in the arrangement portion on the front surface of the special symbol display device 4, the arrangement portion on the back surface of the decorative members 31, 32, and 33. ing. Further, the transfer control circuit 152 and the drawing circuit 154 included in the VDP 141 execute a sprite drawing process as shown in the flowchart of FIG. 31 in response to the reception of the transfer display command from the effect control microcomputer 120. In S444, it is determined whether or not the image element data write destination is a non-display area. When the writing destination is a non-display area, the image element data for the frame buffer memory 156 is skipped by skipping the process of step S445 even if the transfer display command is received from the effect control microcomputer 120. Restrict writing. Thereby, the control in the display effect is performed as compared with the case where the display element is created by writing the image element data to the address of the frame buffer memory 156 allocated corresponding to the non-display area 5B on the screen of the image display device 5. The burden can be reduced.

  In addition, in the VDP 141, the transfer control circuit 152 and the drawing circuit 154 automatically limit writing when the writing destination is a non-display area, so at the stage of designing a gaming machine such as the pachinko gaming machine 1 It is not necessary to take care to prevent an image from being displayed in the non-display area 5B, and the design burden of a gaming machine such as the pachinko gaming machine 1 can be reduced. In addition, by executing processing such as step S444 shown in FIG. 31 by the transfer control circuit 152 and the drawing circuit 154 included in the VDP 141, the display position of the image element is set to the image display device on the side of the effect control microcomputer 120. Therefore, it is not necessary to determine whether or not the image is included in the non-display area 5B on the screen 5, and an increase in the control burden in the display effect can be prevented by the same processing as when the non-display area 5B does not exist.

  The present invention is not limited to the above embodiment, and various modifications and applications are possible. For example, in the above embodiment, the transfer control circuit 152 or the drawing circuit 154 included in the VDP 141 executes processing such as step S444 shown in FIG. In the above description, the writing to the frame buffer memory 156 is limited. However, the present invention is not limited to this. For example, on the side of the production control microcomputer 120, a process for restricting writing to the frame buffer memory 156 when the writing destination is a non-display area is executed. It may be.

  In this case, the CPU 131 provided in the effect control microcomputer 120 replaces the process shown in the flowchart of FIG. 26 as the display update command process executed in step S225 of FIG. 25, as shown in the flowchart of FIG. Execute the process. In the display update command processing shown in FIG. 33, first, in the same manner as steps S341 and S342 in FIG. 26, the image element whose display is to be updated is specified (step S381), and the read address of the image element data is specified. (Step S382). Thereafter, in the display update command process shown in FIG. 33, the write address setting process shown in the flowchart of FIG. 34 is executed (step S383).

  In the write address setting process shown in FIG. 34, first, the arrangement of the image elements to be updated in the display specified in step S381 in FIG. 33 corresponds to the non-display area 5B on the screen of the image display device 5. It is determined whether or not the arrangement is included (step S501). For example, the CPU 131 specifies the display position (for example, display coordinates) of the image element on the screen of the image display device 5 from the display control data read from the effect control pattern, and the size (for example, width or height) of the image element to be displayed. From this, it is determined whether or not at least a part of the image element is arranged in the non-display area 5B. When at least a part of the image element is arranged in the non-display area 5B, it is determined that the image element includes an arrangement corresponding to the non-display area 5B.

  If it is determined in step S501 that the arrangement corresponding to the non-display area 5B is not included (step S501; No), the image element data write address in the frame buffer memory 156 is used as the image element data to be displayed. After setting the address for displaying the entire image on the screen of the image display device 5 (step S502), the write address setting process is terminated, and the process proceeds to the process of step S384 shown in FIG. For example, the CPU 131 displays the entire image element on the screen of the image display device 5 by designating the write address in the frame buffer memory 156 for all the pixels constituting the image element to be displayed in step S502. Like that.

  On the other hand, when it is determined in step S501 that the arrangement corresponding to the non-display area 5B is included (step S501; Yes), the entire image element is arranged in the non-display area 5B. Or whether a part is arranged in the non-display area 5B (step S503). At this time, when it is determined that a part is arranged in the non-display area 5B and the whole is not arranged in the non-display area 5B (step S503; No), the image element in the frame buffer memory 156 After setting an address excluding the write destination corresponding to the non-display area 5B as the data write address (step S504), the write address setting process is terminated, and the process of step S384 shown in FIG. move on. For example, the CPU 131 specifies the write address in the frame buffer memory 156 for each pixel constituting the image element to be displayed in step S503, and excludes the address assigned to the non-display area 5B among the write addresses. As a result, only the address assigned to the display area 5A is set to be notified to the VDP 141.

  If it is determined in step S503 that the entire image element is arranged in the non-display area 5B (step S503; Yes), the process proceeds to step S386 shown in FIG. Thereby, when the entire image element is arranged in the non-display area 5B, the writing address of the image element data in the frame buffer memory 156 is not set, and the transfer display command is not transmitted to the VDP 141. become.

  When the process proceeds to the process of step S384 shown in FIG. 33 after executing the write address setting process as described above, the write data amount that is the data amount of the image element data written to the frame buffer memory 156 is specified. (Step S384). Thereafter, a transfer display command is created and transmitted to the VDP 141 based on the read address, write address, and write data amount of the image element data specified in steps S382 to S384 (step S385).

  After executing the process of step S345 or when it is determined in step S503 of FIG. 34 that the entire image element is arranged in the non-display area 5B, the command for all image elements to be displayed is completed. It is determined whether or not (step S386). If the command is not completed (step S386; No), the process returns to step S381. On the other hand, if the command for all the image elements to be updated is completed (step S386; Yes), the display update command process is terminated.

  In this way, the CPU 131 determines whether or not the image element arrangement includes an arrangement corresponding to the non-display area 5B in step S501 of FIG. If the layout corresponding to the non-display area 5B is included, the write address excluding the write destination corresponding to the non-display area 5B is set, or the write address is not set. This restricts the writing of image element data to the frame buffer memory 156. Thereby, the control in the display effect is performed as compared with the case where the display element is created by writing the image element data to the address of the frame buffer memory 156 allocated corresponding to the non-display area 5B on the screen of the image display device 5. The burden can be reduced.

  In addition, since the CPU 131 automatically restricts writing when the writing destination is a non-display area, an image is not displayed in the non-display area at the stage of designing a gaming machine such as the pachinko gaming machine 1. This eliminates the need for consideration of the game machine and can reduce the design burden of the gaming machine. In addition, the CPU 131 provided in the effect control microcomputer 120 executes the write address setting process as shown in the flowchart of FIG. 34, so that the display position of the image element is on the screen of the image display device 5 on the VDP 141 side. It is not necessary to determine whether or not it is included in the non-display area 5B, and an increase in the control burden in the display effect can be prevented by the same processing as when the non-display area 5B does not exist.

  In the above embodiment, as an example of the gaming machine, the description has been given using the pachinko gaming machine 1 having a function of variably displaying special symbols and decorative symbols and a function of displaying various effect images. However, the present invention is not limited to the pachinko gaming machine 1 in the above embodiment, but can be applied to other gaming machines such as a slot machine. Hereinafter, a case where the present invention is applied to a slot machine which is an example of another gaming machine will be described.

  FIG. 35 is a front view of a slot machine 500 as an example of a slot machine to which the present invention is applied, and shows a layout of main members. The slot machine 500 is roughly composed of a housing whose front surface is open and a front door pivotally supported at a side end of the housing.

  Inside the casing of the slot machine 500, there is installed a variable display device 501 in which reels DL, DC, DR having a plurality of kinds of symbols arranged on the outer periphery are arranged in parallel in the horizontal direction. An image display device 510 having a display function is provided on the front door of the slot machine 500. The image display device 510 is provided with one transparent see-through window. For example, three consecutive symbols arranged on the reels DL, DC, and DR are arranged so that they can be seen from the see-through window. Yes. On the screen of the image display device 510, for example, as shown in FIG. 36, a display area 510A where various images are displayed and a non-display area 510B where image display is restricted are provided. In the image display device 510, the portion of the see-through window arranged in front of the variable display device 501 is limited in image display, like the non-display area 5B on the screen of the image display device 5 in the above embodiment. It is a non-display area 510B. That is, the non-display area 510 is not provided with a liquid crystal for displaying an image, a member constituting the liquid crystal (for example, a polarizing plate), a circuit for controlling the liquid crystal, and the like, and does not physically display an image. It remains transparent. On the other hand, on the back surface of the display area 510A, for example, a backlight that irradiates the display area 510A from behind, a concealing member that conceals the inside of the slot machine 500, and the like are provided.

  On the outer periphery of the reels DL, DC, DR, for example, “Red 7”, “White 7”, “BAR”, “JAC”, “Watermelon”, “Cherry”, “Bell”, which can be distinguished from each other Are drawn in a predetermined order. The symbols drawn on the outer peripheries of the reels DL, DC, and DR are displayed on the upper, middle, and lower three stages through the perspective windows of the image display device 510.

  The reels DL, DC, and DR are rotated by reel motors 651L, 651C, and 651R (FIG. 37) provided in correspondence with each other, so that the symbols of the reels DL, DC, and DR are displayed in the see-through window of the image display device 510. Display continuously changing, and by stopping the rotation of each of the reels DL, DC, and DR, three consecutive symbols are displayed as a display result so as to be visible through the viewing window of the image display device 510. It has come to be.

  Below the image display device 510 at the front door of the slot machine 500 is provided an operation table 520 on which various input switches and the like for the player to perform various operations are arranged. On the far side of the operation table 520, there are a medal insertion slot 502 into which medals can be inserted, a BET switch 503 for setting (BET) the number of bets for one medal, and the maximum number of bets that can be bet in one game ( MAXBET switch 504 for setting the number of bets (three in this example), used for setting the medal and bet number stored as credit (the number of medals stored as a player's own game value) A checkout switch 508 for paying out medals is provided. The medal inserted into the medal insertion slot 502 is detected by a predetermined insertion medal sensor.

  On the front side of the operation table 520, a start lever 505 operated when starting the game in the slot machine 500, stop switches 506L, 506C operated when stopping the rotation of the reels DL, DC, DR, respectively. 506R is provided. A medal payout exit 507 through which medals are paid out is provided at the bottom of the operation table 520.

  In the upper part of the image display device 510 in the front door of the slot machine 500, a game information display unit for displaying various information related to games in the slot machine 500 is provided. For example, the game information display unit displays a credit indicator that displays the number of medals stored as credits, an auxiliary display that displays the number of medals acquired in the big bonus, an error code indicating the contents when an error occurs, and the like And a payout display for displaying the number of medals paid out when a prize is generated. Two speakers 511L and 511R that emit sound effects are provided on the left and right sides of the game information display section. In addition, game effect lamps 512 are provided on the upper part of the image display device 510, and game effect lamps 513 and 514 are provided on the left and right sides of the operation table 520, respectively.

  When a game is played in the slot machine 500, first, medals are inserted from the medal insertion slot 502, or credits are used to set the number of bets. To use the credit, the BET switch 503 or the MAXBET switch 504 is operated. When the number of bets is set in this way, the pay lines L1 to L5 are valid, and the operation of the start lever 505 is valid, that is, the game can be started.

  When the start lever 505 is operated in a state where the game can be started, the reels DL, DC, DR rotate based on the detection of the operation by the start lever switch 505A (FIG. 37), and the reels DL, The DC and DR symbols vary continuously. If any one of the stop switches 506L, 506C, and 506R is operated in this state, the rotation of the corresponding reels DL, DC, and DR is stopped, and the display result is derived and displayed so as to be visible through the see-through window of the image display device 510. The

  Then, when the rotation of all the reels DL, DC, and DR is stopped, one game is finished, and each combination of symbols called predetermined roles on each of the activated pay lines L1 to L5 is displayed. When the display results of the reels DL, DC, DR are stopped, a winning is generated. The types of winning combinations are roughly divided into small roles with medals, re-players that can start the next game without the need to set the number of bets, and special cases that have a transition in gaming state. There is a role, and the winning combination is determined according to the gaming state. In the slot machine 500, an internal lottery is performed to determine whether or not the winning of each combination determined according to the gaming state is allowed based on the random number value extracted at the timing when the start lever 505 is operated. The fact that winning in this internal lottery and winning is permitted is also referred to as “internal winning”. Of the winning of each role, the winning of the small role and the replaying role is valid only in the game for which the winning is determined, but the winning of the special role has the roles allowed to be generated by the internal lottery. It is effective until. In other words, once the occurrence of a special winning combination is allowed, even if the special winning combination cannot be generated in each game, the winning is carried over to the next game.

  The gaming state in the slot machine 500 includes, for example, a regular bonus, a big bonus, and a normal gaming state. In the regular bonus game state, for example, small roles such as JAC, cherry, watermelon, and bell are defined as winning combinations and are subject to lottery in the internal lottery. In the big bonus, small roles such as cherries, watermelons and bells, and special roles such as regular bonus and JACIN are defined as winning roles in a given small role game. It is a lottery target. In the normal gaming state, for example, small roles such as cherry, watermelon and bell, replay roles such as replay, special roles such as big bonus, regular bonus, etc. are predetermined as winning roles, It is a lottery target in the lottery.

  When a special role winning that becomes a big bonus occurs in the normal gaming state, the gaming state shifts to the big bonus. With the big bonus, a predetermined game called a small role game can be played. The big bonus is ended when the total number of medals given to the player in the big bonus becomes equal to or more than a prescribed number (eg, 466). When a special role winning that becomes a regular bonus occurs in a small role game in a normal gaming state or a big bonus, the gaming state shifts to a regular bonus. In addition, when a special role winning that becomes JACIN occurs in the small role game in the big bonus, the gaming state shifts to the regular bonus. The regular bonus ends when 12 games have been consumed or when 8 games have been won (any kind of combination can be used), whichever comes first. If the total number of medals awarded to the player during the big bonus exceeds the specified number with the regular bonus in the big bonus, the regular bonus is terminated together with the big bonus.

  In the slot machine 500, when the gaming state is shifted to a special gaming state such as a regular bonus or a big bonus, the player can acquire more medals than the normal gaming state, which is more advantageous to the player than the normal gaming state. It becomes a game state. Note that the special gaming state is not limited to a regular bonus or a big bonus, and it can be expected that the player will win more medals than the normal gaming state, and the gaming state may be more advantageous to the player than the normal gaming state. That's fine. As such a gaming state that is more advantageous to the player than the normal gaming state, for example, an operation that satisfies the conditions for deriving notification target winnings that occur on condition that reel deriving conditions (for example, stop order and stop timing) are satisfied By restricting the gaming state (so-called assist time) in which the procedure is notified and the pull-in range of at least one of the reels, the symbols displayed when the stop switches 506L, 506C, 506R are operated are stopped. Challenge time (CT) that allows control to be easily controlled and allows players to derive a combination of winning symbols, and allow for specific winnings (such as replay winnings and single bonus winnings) Game state (so-called replay time or concentration state) that increases the probability of being played, and further combining these It may be any such tricks state.

  In the slot machine 500, for example, a main board 600, an effect control board 620, a reel unit 650 and the like as shown in FIG. 37 are mounted. In addition, other boards such as a power supply board and a relay board connected to the main board 600 are also mounted on the slot machine 500. The main board 600 is provided with a game control microcomputer 610. Similar to the game control microcomputer 100 in the above embodiment, the game control microcomputer 610 is a CPU that performs control according to a program, a ROM that stores user programs and data, and a RAM that is used by the CPU as a work area. And so on.

  The reel unit 650 includes reel motors 651L, 651C, 651R, a reel lamp 652, a reel sensor 653, and the like. The reel motors 651L, 651C, and 651R are motors for rotating the reels DL, DC, and DR. The reel lamp 652 is provided inside each reel DL, DC, DR, and irradiates a symbol that can be visually recognized by the variable display device 501 among the symbols drawn on each reel DL, DC, DR from the inside of the reel. It is a lamp to do. The reel sensor 653 is a sensor for detecting the rotation state and the rotation speed of each reel DL, DC, DR.

  On the effect control board 620, an effect control microcomputer 630, a display control unit 631, a sound control unit 632, a lamp control unit 633, and the like are mounted. The effect control board 620 is also equipped with a circuit similar to the reset IC with watchdog 124 in the above embodiment and a circuit similar to the power control circuit 125. Note that circuits such as a reset IC with a watchdog and a power control circuit are circuits for switching whether the power supply voltage supplied from the power supply board is delivered to or shut off from each part in the production control microcomputer 630. It may be incorporated in the production control microcomputer 630. The effect control microcomputer 630 is similar to the effect control microcomputer 120 in the above embodiment, a CPU that performs control according to a program, a ROM that stores user programs and data, and a RAM that is used by the CPU as a work area. , A reset / interrupt controller, a power interruption detection circuit, and the like. The display control unit 631 controls the display operation in the image display device 510. Similarly to the display control unit 121 in the above embodiment, the image processing according to the display control command from the effect control microcomputer 630 is performed. And a CGROM that stores various image data used for displaying an image on the image display device 510.

  The VDP provided in the display control unit 631 is provided with a host interface, a transfer control circuit, a CGROM interface, a drawing circuit, a temporary storage memory, a frame buffer memory, a display circuit, a moving image decoder, and the like, as in the above embodiment. ing. In the frame buffer memory provided in the VDP provided in the display control unit 631, in order to facilitate address management, in the display data area for storing display data, as in the frame buffer memory 156 in the above embodiment, Addresses are assigned not only to the display area 510A on the screen of the image display device 510 but also to the non-display area 510B.

  In the effect control microcomputer 630, processing for controlling the effect operation by the image display device 510, the speakers 511L and 511R, the game effect lamps 512 to 514, and the like according to the effect control pattern based on the effect control command received from the main board 600 is performed. Executed by the CPU.

  The reset / interrupt controller provided in the production control microcomputer 630 is configured to perform an event interrupt when the event interrupt signal from the VDP provided in the display control unit 631 is turned on, as in step S407 of FIG. 29 in the above embodiment. Completion signal detection means is configured by detecting occurrence. The CPU included in the effect control microcomputer 630 is similar to step S372 in FIG. 28 in the above embodiment, and the event interrupt wait timer value is not detected by the reset / interrupt controller, and the event interrupt wait timer value is the time limit determination value. Is reached, a predetermined loop process is started, and execution of the interrupt process corresponding to the generation of the production control timer interrupt is not started. In the interruption process corresponding to the generation of the production control timer interruption, the same process as step S93 shown in FIG. 23 in the above embodiment is executed to clear the reset IC with a watchdog mounted on the production control board 620. To do. When such an interruption process is not executed, a time-out occurs in the reset IC with watchdog mounted on the effect control board 620, and an on-state reset signal is input to the power control circuit mounted on the effect control board 620. The effect control restarting means for restarting the effect control microcomputer 630 by restarting the supply after a predetermined time has elapsed after the supply of power supply voltage to the effect control microcomputer 630 is stopped. Configure. Further, the CPU included in the effect control microcomputer 630 executes the same process as the effect initial setting process in step S51 shown in FIG. 18 in the above-described embodiment, and similarly to step S307 in FIG. 19 in the above-described embodiment. Thus, by performing the initial setting of the VDP provided in the display control unit 631, an image processing initial setting unit is configured. At this time, in the VDP provided in the display control unit 631, for example, the storage contents of the temporary storage memory or the frame buffer memory are initialized based on the initialization signal or the initial setting data received from the effect control microcomputer 630. The display area is set by initializing or interrupting the processing being executed by the transfer control circuit, the drawing circuit, or the moving image decoder, and by allocating a storage area in the frame buffer memory corresponding to the display screen of the image display device 510. It is only necessary to execute a process for performing at least one of various setting operations such as setting the display image update period in the image display device 510.

  With such a configuration, when the production control microcomputer 630 is restarted, the VDP included in the display control unit 631 is initialized as in the case where power supply to the slot machine 500 is started. be able to. Then, when the occurrence of an event interruption in the VDP provided in the display control unit 631 is not detected on the side of the effect control microcomputer 630 and a predetermined standby period has elapsed, without performing dedicated processing, Initial setting of VDP can be performed, and it is possible to appropriately recover from an abnormal display state while preventing an increase in program capacity and complication of processing.

  Further, in the effect control microcomputer 630, if the power interruption occurrence determination time elapses after the supply voltage from the power control circuit mounted on the effect control board 620 becomes equal to or less than the power interruption detection determination value, the power interruption detection is performed. The circuit performs the same process as step S423 of FIG. 30 in the above embodiment, thereby setting the power-off signal to the on state, thereby configuring the power monitoring means. In the CPU included in the effect control microcomputer 630, as the interrupt processing corresponding to the power interruption check timer interrupt having a higher priority than the effect control timer interrupt, the effect side power interruption shown in the flowchart of FIG. The same processing as the check interrupt processing is executed. Then, if the power interruption determination time elapses after the power interruption signal transmitted from the electric interruption detection circuit is turned on, the effect backup data is stored in the same manner as step S76 in FIG. 22 in the above embodiment. A data saving unit is configured by setting and storing the data in a backup area of a RAM serving as a storage unit. Then, the CPU included in the effect control microcomputer 630 executes the effect control restoration process in the same manner as step S52 shown in FIG. 18 in the above embodiment, in response to the restart of the effect control microcomputer 630. Thus, similar to step S324 of FIG. 21 in the above embodiment, the control state of the effect control microcomputer 630 is restored to the state before the restart by the effect backup data stored in the RAM backup area. By doing so, state recovery means is configured. Further, similarly to step S325 of FIG. 21 in the above embodiment, the restart control unit is configured by performing restart setting of various controls in the VDP provided in the display control unit 631.

  With such a configuration, the occurrence of an event interrupt in the VDP provided in the display control unit 631 is not detected on the side of the effect control microcomputer 630, and the process is halfway when a predetermined standby period has elapsed. The display operation can be continued after the restart, and a more appropriate recovery from the abnormal display state is possible. In addition, when the production control microcomputer 630 is restarted, it is not necessary to perform special control for restoring the control state, so that it is properly recovered from the abnormal display state while preventing the processing from becoming complicated. Can be made.

  In the VDP provided in the display control unit 631, after the moving image decoder decodes moving image data in the same manner as in step S462 shown in FIG. 32 in the above embodiment, the same processing as in step S466 in the above embodiment. Then, an event interrupt signal is output to the production control microcomputer 630. Then, in the effect control microcomputer 630, after the CPU transmits a moving image decoding start command to the VDP provided in the display control unit 631 in the same manner as in step S364 in FIG. 28 in the above embodiment, the reset / interrupt controller performs the above-described operation. It is determined that the CPU has reached the time limit determination value in the same manner as in step S372 shown in FIG. 28 in the above embodiment without detecting the occurrence of an event interrupt by the same processing as in step S407 in FIG. 29 in the embodiment. Thus, a predetermined loop process is entered. Thereafter, based on the occurrence of timeout in the reset IC with watchdog mounted on the effect control board 620, the power control circuit mounted on the effect control board 620 passes the supply of the power supply voltage to the effect control microcomputer 630 for a predetermined time. The production control microcomputer 630 is restarted by restarting the system until it is stopped. As a result, even when an abnormality occurs in the decoding of the moving image data and the reproduction of the moving image is interrupted, it is possible to appropriately recover from the abnormal display state if a predetermined standby period elapses.

  On the screen of the image display device 510, a non-display area 510B in which image display is restricted is provided, for example, at an arrangement portion on the front surface of the variable display device 501. Further, the transfer control circuit and the drawing circuit provided in the VDP provided in the display control unit 631 respond to the reception of the transfer display command from the effect control microcomputer 630, and the flowchart of FIG. 31 in the above embodiment. A process similar to the sprite drawing process as shown in FIG. Then, similarly to step S444 in FIG. 31 in the above embodiment, it is determined whether or not the image element data writing destination is a non-display area, thereby arranging the position determining means including the writing position determining means. Configure. In this determination process, when the writing destination is a non-display area, even if a transfer display command is received from the effect control microcomputer 630, the same process as step S445 in the above embodiment is skipped. As a result, a display data write restriction unit for restricting the writing of image element data to the frame buffer memory provided in the VDP provided in the display control unit 631 is configured.

  With such a configuration, a display effect is produced as compared with the case where image element data is written to the address of the frame buffer memory allocated corresponding to the non-display area 510B on the screen of the image display device 510 to create display data. Can reduce the control burden. In the VDP provided in the display control unit 631, the transfer control circuit and the drawing circuit automatically limit the writing when the writing destination is a non-display area, thereby designing a gaming machine such as the slot machine 500. Therefore, it is not necessary to take care to prevent the image from being displayed in the non-display area, and the design burden of the gaming machine can be reduced. In addition, the processing similar to that in step S444 shown in FIG. 31 in the above embodiment is performed by the transfer control circuit and the drawing circuit provided in the VDP included in the display control unit 631, so that the effect control microcomputer 630 side Then, it is not necessary to determine whether or not the display position of the image element is included in the non-display area 510B on the screen of the image display device 510, and the control in the display effect is performed by the same processing as when the non-display area 510B does not exist. Increase in burden can be prevented.

  The CPU included in the effect control microcomputer 630 may execute processing similar to the display update command processing shown in FIG. 33 and the write address setting processing shown in FIG. In this case, the arrangement determination unit is configured by determining whether or not the arrangement of the image elements includes an arrangement corresponding to the non-display area 510B in the same manner as in step S501 of FIG. 34 in the above embodiment. To do. If the layout corresponding to the non-display area 510B is included, the write address excluding the write destination corresponding to the non-display area 510B is set in the same manner as in step S504 of FIG. 34 in the above embodiment. Or the frame buffer provided in the VDP provided in the display control unit 631 by not setting the write address in the same manner as in the case where the determination in step S503 in FIG. Display data writing restriction means for restricting writing of image element data to the memory is configured.

  With such a configuration, a display effect is produced as compared with the case where image element data is written to the address of the frame buffer memory allocated corresponding to the non-display area 510B on the screen of the image display device 510 to create display data. Can reduce the control burden. In addition, by restricting writing when the writing destination is a non-display area by the CPU included in the effect control microcomputer 630, an image is displayed in the non-display area at the stage of designing a gaming machine such as the slot machine 500. This eliminates the need to take care to prevent the display of the game machine, thereby reducing the design burden of the gaming machine. In addition, in the VDP provided in the display control unit 631, the CPU provided in the effect control microcomputer 630 performs the same process as the write address setting process as illustrated in the flowchart of FIG. It is not necessary to determine whether or not the display position of the image element is included in the non-display area 510B on the screen of the image display device 510, and the control burden on the display effect is similar to the case where the non-display area 510B does not exist. Increase can be prevented.

  Note that the CPU included in the effect control microcomputer 630 is based on display control data read from the effect control pattern, for example, during a normal game period in which no winning is made, or in a regular bonus or big bonus game state due to the occurrence of a win. During the transition period, the same processing as the moving image display processing executed in step S247 shown in FIG. 27 in the above embodiment is executed, and the moving image is displayed on the screen of the image display device 510. You may make it perform the effect by the moving image using image data.

  As described above, the present invention can be applied to a slot machine, and even when applied to a slot machine, the same effects as those applied to a pachinko gaming machine can be obtained.

  In the above embodiment, when the power-off signal from the power-off detection circuit 137 is turned on, the CPU 131 executes the processing of steps S76 to S79 in FIG. It has been described that the effect backup data for restoring the control state is set and stored in the backup area of the RAM 133 before starting. However, the present invention is not limited to this, and any data can be used as long as it can store data for restoring the control state at an arbitrary timing when the production control microcomputer 120 is restarted. For example, when the occurrence of an event interrupt is not detected by the reset / interrupt controller 136 in step S372 in FIG. 28 and the event interrupt wait timer value reaches the time limit determination value, the CPU 131 proceeds to steps S76 to S79 in FIG. Data for restoring the control state by executing the same process as described above may be set and stored in the backup area of the RAM 133, and then a predetermined loop process may be entered. In this case, the reset signal from the reset IC 124 with a watchdog is input to the effect control microcomputer 120, and the reset / interrupt controller 136 detects that the on-state reset signal has been detected. The computer 120 may be reset and restarted.

  In the above embodiment, the event interrupt signal indicating that the decoding of the picture data is completed by the moving picture decoder 158 included in the VDP 141 is output from the VDP 141 to the effect control microcomputer 120, and this event interrupt signal is output. It has been described that the production control microcomputer 120 is restarted when it is determined that the event interrupt wait timer value has reached the time limit determination value without being output. However, the present invention is not limited to this. For example, the VDP 141 outputs an arbitrary completion signal indicating that a predetermined process related to image display in the image display device 5 has been completed to the effect control microcomputer 120. As long as a predetermined waiting time elapses without outputting this completion signal, the effect control microcomputer 120 may be restarted. As processing to be completed in the VDP 141 in order to output a completion signal, for example, processing for transferring image element data or moving image data read from the CGROM 142 by the transfer control circuit 152 to the temporary storage memory 155, drawing, Processing for writing image element data and moving image data read from the temporary storage memory 155 by the circuit 154 to the frame buffer memory 156 and storing them, and for moving image decoders read from the CGROM 142 or the temporary storage memory 155 by the moving image decoder 158 Display data for one screen in the image display device 5 is created using a process for performing predetermined conversion and a plurality of types of image element data and moving image data read out from the temporary storage memory 155 by the drawing circuit 154 ( Drawing) processing etc. Of the processing relating to various image display, as a process that includes at least one type, it is sufficient predetermined.

  In addition, if the gaming machine of the present invention has an image display device in a ball game machine such as a pachinko game machine, for example, a general electric machine or a ball game machine with a probability setting function called a Pachi-Con It does not matter. In addition, the present invention is not limited to a payout type gaming machine that pays out a predetermined number of prize balls in response to detection of winning balls, and encloses game balls and gives points in response to detection of winning balls. It can also be applied to an enclosed game machine.

  Furthermore, the gaming machine of the present invention is not limited to a slot machine that can play a game using medals and credits, for example, a slot machine that plays a game using pachinko balls, or credits without medals being discharged to the outside. The present invention can also be applied to a complete credit type slot machine that can be played using the game, an image type slot machine in which a variable display device is displayed as an image, and the like.

  The present invention can also be applied to a game machine that simulates the operation of the pachinko gaming machine 1 or the slot machine 500. The program and data for realizing the present invention are not limited to a form distributed and provided to a computer device or the like by a detachable recording medium, but preinstalled in a storage device such as a computer device or the like in advance. You may take the form distributed by keeping it. Further, the program and data for realizing the present invention are distributed by downloading from other devices on a network connected via a communication line or the like by providing a communication processing unit. It doesn't matter.

  The game execution mode is not only executed by attaching a detachable recording medium, but can also be executed by temporarily storing a program and data downloaded via a communication line or the like in an internal memory or the like. It is also possible to execute directly using hardware resources on the other device side on a network connected via a communication line or the like. Furthermore, the game can be executed by exchanging data with other computer devices or the like via a network.

It is a front view of the pachinko gaming machine in this embodiment. It is a figure which shows an example of the display area and non-display area on the screen of an image display apparatus. It is a block diagram which shows the various control boards etc. which were mounted in the pachinko game machine. It is explanatory drawing which shows an example of the content of an effect control command. It is a block diagram which shows the structural example of the microcomputer for game control. It is a block diagram which shows the structural example of the microcomputer for production control. It is a figure which shows the structural example of an effect control pattern table. It is a figure which shows the structural example of an effect control pattern. It is a block diagram which shows the structural example of a display control part. It is a figure which shows the structural example of the picture buffer provided in the temporary memory. It is a figure which shows an example of the data area for a display in a frame buffer memory. It is a figure which shows an example of the display control command transmitted to VDP from the microcomputer for production control. It is a figure which shows an example of the address map in CGROM. It is a figure which shows the structural example of moving image data. It is a flowchart which shows an example of a game control main process. It is a flowchart which shows an example of a game control interruption process. It is a flowchart which shows an example of a special symbol process process. It is a flowchart which shows an example of production control main processing. It is a flowchart which shows an example of an effect initial setting process. It is explanatory drawing which shows the example of a setting of interruption. It is a flowchart which shows an example of an effect control recovery process. It is a flowchart which shows an example of a production side power interruption check interruption process. It is a flowchart which shows an example of an effect control interruption process. It is a flowchart which shows an example of production control process processing. It is a flowchart which shows an example of a process during symbol variable display. It is a flowchart which shows an example of a display update command process. It is a flowchart which shows an example of a big hit effect process. It is a flowchart which shows an example of a process during moving image display. It is a flowchart which shows an example of a reset / interrupt control process. It is a flowchart which shows an example of a power interruption detection process. It is a flowchart which shows an example of a sprite drawing process. It is a flowchart which shows an example of a moving image decoding process. It is a flowchart which shows the modification of a display update command process. It is a flowchart which shows an example of a write address setting process. It is a front view of the slot machine to which this invention is applied. It is a figure which shows an example of the display area and non-display area on the screen of the image display apparatus with which a slot machine is provided. It is a block diagram which shows the various control boards etc. which were mounted in the slot machine.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pachinko machine 2 ... Game board 3 ... Gaming machine frame 4 ... Special symbol display device 5, 510 ... Image display device 6 ... Normal variable winning ball device 7 ... Special variable winning ball device 8L, 8R, 511L, 511R ... Speakers 9, 512, 513, 514 ... Game effect lamps 10 ... Power supply board 11, 600 ... Main board 12, 620 ... Production control board 13 ... Signal relay board 20 ... Normal symbol display device 21 ... Gate switch 22 ... Start-up switch 23 … V winning switch 24… Count switch 41… Passing gate 81, 82… Solenoid 100, 610… Game control microcomputer 111, 131… CPU
112, 132 ... ROM
113, 133 ... RAM
114, 134 ... Random number circuits 115, 135 ... I / O ports 120, 630 ... Production control microcomputers 121, 631 ... Display control units 122, 632 ... Sound control units 123, 633 ... Lamp control unit 124 ... Reset IC with watchdog
125 ... Power control circuit 136 ... Reset / interrupt controller 137 ... Power failure detection circuit 141 ... VDP
142 ... CGROM
142A ... Sprite data area 142B ... Moving image data area 151 ... Host interface 152 ... Transfer control circuit 153 ... CGROM interface 154 ... Drawing circuit 155 ... Temporary storage memory 155-1 to 155-X ... Picture buffer 156 ... Frame buffer memory 157 ... Display circuit 158... Moving picture decoder 201... Production control pattern table

Claims (6)

A gaming machine in which a player can play a predetermined game,
Image display means for displaying various images including a plurality of types of effect images;
Game control means for controlling the progress of the game;
A display control means for controlling the display operation of the image display means, including an effect control microcomputer and an image processing processor;
The display control means includes data storage means for storing data necessary for restoring the control state of the production control microcomputer,
The image processing processor includes a completion signal output means for outputting a completion signal indicating completion of a predetermined process related to image display by the image display means to the effect control microcomputer,
The production control microcomputer is:
Image processing initial setting means for performing initial setting of the image processing processor in response to activation of the effect control microcomputer;
Processing command means for commanding the image processing processor to start the processing;
A completion signal detection means for detecting a completion signal from the completion signal output means;
In response to a predetermined waiting period elapses without detection of the completion signal from the completion signal output means by the completion signal detection means after the instruction from the processing instruction means is sent, the effect control Effect control restarting means for restarting the microcomputer,
In performing the restart by the effect control restarting means, a data saving means for storing data in the data storage means,
In response to being restarted by the effect control restarting means, after the control state before the restarting is restored based on the data stored in the data storage means, the restored control Restart control means for restarting the display operation of the image display means from the state,
A gaming machine characterized by that. In response to detecting a drop in the power supply voltage supplied to the effect control microcomputer, the power supply monitoring means for outputting a voltage drop detection signal,
The data saving means stores data necessary for restoring the control state in the data storage means in response to the output of the voltage drop detection signal from the power supply monitoring means.
The gaming machine according to claim 1. The display control means includes compressed data storage means for storing moving image data including compressed data by motion compensation predictive coding,
The image processing processor includes:
Decoding means for decoding moving image data read from the compressed data storage means;
Moving image reproduction means for reproducing a moving image by sequentially displaying images generated based on the moving image data decoded by the decoding means on the image display means,
The completion signal output means outputs a completion signal indicating that the decoding of the moving image data by the decoding means is completed to the microcomputer for effect control,
The processing command means includes a decode start command means for commanding start of processing for decoding moving image data by the decoding means,
The effect control restarting means responds to the fact that the waiting period has passed without the completion signal from the completion signal output means being detected by the completion signal detecting means after the instruction from the decoding start instruction means has been sent. And restarting the production control microcomputer,
The gaming machine according to claim 1 or 2, characterized in that. A game component disposed on the front or back of the image display means,
The image display means includes
A display area where various images are displayed;
A non-display area in which display of various images is restricted corresponding to the arrangement position of the gaming parts,
The display control means includes
Display data storage means for storing image display data in the image display means;
Arrangement determining means for determining whether an image to be displayed is arranged in the non-display area;
Display data writing restriction means for restricting writing to the display data storage means for image data indicating an image determined to be arranged in the non-display area by the arrangement determination means,
The gaming machine according to claim 1, 2, or 3. The display control means includes image element data storage means for storing a plurality of types of image element data including image element data corresponding to the effect image,
The image processing processor includes:
Data processing means for executing processing for creating display data based on image element data;
Display data output means for outputting the display data read from the display data storage means to the image display means,
The production control microcomputer includes a display image update command means for notifying the image processing processor of a reading position and a writing position of image element data and instructing an update of a display image in the image display means,
The arrangement determining means includes writing position determining means for determining whether or not the writing position of the image element data notified from the display image update command means is a writing position corresponding to the non-display area,
The display data writing restricting means restricts writing of image element data by the data processing means to a writing position determined by the writing position determining means to correspond to the non-display area;
The gaming machine according to claim 4, wherein: The display control means includes image element data storage means for storing a plurality of types of image element data including image element data corresponding to the effect image,
The image processing processor includes:
Data processing means for executing processing for creating display data based on image element data;
Display data output means for outputting the display data read from the display data storage means to the image display means,
The production control microcomputer includes a display image update command means for notifying the image processing processor of a reading position and a writing position of image element data and instructing an update of a display image in the image display means,
The display data writing restricting unit is configured to store the image element data indicating the image element determined to be arranged in the non-display area by the arrangement determining unit to the display data storage unit by the display image update command unit. Restrict writing to be commanded,
The gaming machine according to claim 4, wherein:

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