JP2003190561A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine capable of preventing the increase of the manufacturing cost of the game machine and increase of the area of parts mounted on a control circuit board in preventing the uncontrollability and runaway operation by an electric control part. <P>SOLUTION: A display control microcomputer outputs display control data to a VDP as the electric control part, and after that, if the microcomputer doesn't receive a feedback signal indicating the completion of signal receiving from the VDP within a prescribed period of time (when a reset flag is ON), it transmits a reset signal for resetting the system to the VDP (S74). <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a pachinko gaming machine,
The present invention relates to a gaming machine represented by a coin gaming machine and a slot machine. More specifically, the present invention relates to a gaming machine having a predetermined electric component and capable of producing a game by controlling the operation of the electric component.

[0002]

2. Description of the Related Art Variable display devices, lamps, and
There has been one having a predetermined electric component such as a speaker and configured to be able to produce a game by controlling the operation of the electric component.

In such a conventional gaming machine, a control signal is transmitted from an effect control microcomputer for controlling a game to an electric control component such as a control IC (integrated circuit), and in response to the control signal. The electric parts were controlled by the electric control parts. Then, a monitoring circuit using a watchdog timer is provided corresponding to the electric control component in order to prevent an uncontrollable state and runaway of the electric control component by the electric control component. If no control signal was sent to the control component, the electrical control component was reset.

[0004]

However, when the control signal transmitted from the performance control microcomputer to the electric control component is monitored by the watchdog timer as in the conventional case, even if the normal control signal is transmitted. Regardless, there is a problem in that the electric control parts are reset due to the time-out of the watchdog timer and the control is not performed. If a monitoring circuit using a watchdog timer as described above is provided separately from the production control microcomputer, the manufacturing cost of the gaming machine will increase due to the increase in the number of parts, and the monitoring circuit will be mounted on the board. There arises a problem that the component mounting area on the control board increases.

The present invention has been conceived in view of the above circumstances, and an object thereof is to prevent an increase in the manufacturing cost of a gaming machine when preventing an uncontrollable state and a runaway operation by an electric control component. Another object of the present invention is to provide a game machine capable of preventing an increase in the component mounting area on the control board.

[0006]

[Specific examples of means for solving the problems and the effects thereof]
(1) A gaming machine that has a predetermined electric component (variable display device 8 including the special symbol display unit 9, speaker 72, etc.) and can produce a game by controlling the operation of the electric component ( It is a pachinko gaming machine 1), and a game control board (game control board 81) on which a game control microcomputer (game control microcomputer 53) for controlling a game state is mounted, and a command transmitted from the game control board. Based on the above, an electric component control board (display control board 80, voice) on which an effect control microcomputer (display control microcomputer 800, sound control microcomputer 700, etc.) that performs control for effecting a game using the electric parts is mounted (Control board 70, etc.) and the electric component control board, and is transmitted from the effect control microcomputer. Electric control parts (VDP103, voice synthesis circuit 7) for controlling the electric parts based on the control signal.
02 etc.), the electric control component outputs a reception completion signal (feedback signal ACK, SIAK) indicating that the reception is completed in response to receiving the control signal from the production control microcomputer. When the production control microcomputer does not receive the reception completion signal within a predetermined period after outputting the control signal toward the electric control component, the operation of the electric control component is returned to the microcomputer. A reset signal for resetting the state is transmitted to the electric control component (S74 of FIG. 14, S144 of FIG. 19).

According to such a configuration, the production control microcomputer resets when the reception completion signal is not received from the electric control component within a predetermined period after outputting the control signal to the electric control component. Since the signal is transmitted to the electric control component, it is possible to recover from the uncontrollable state and the runaway of the electric control component. Furthermore, since the production control microcomputer monitors the state of the electric control components, it is not necessary to separately provide a circuit for monitoring, so that it is possible to prevent an increase in the manufacturing cost of the gaming machine and mount the components on the control board. It is possible to prevent an increase in area.

(2) The production control microcomputer, after outputting the reset signal, regulates execution of control for producing a game using the electric parts for a predetermined period (S7 of FIG. 10, FIG. 14). S77, S in FIG.
97, S147 in FIG. 14).

According to this structure, after the production control microcomputer outputs the reset signal,
Since the execution of the control that directs the game using the electric parts is regulated for a predetermined period, while the electric control parts after being reset are still in the unstable operation state, the game using the electric parts can be performed. It is possible to prevent the production control from being performed.

(3) The game control microcomputer and the effect control microcomputer are provided in correspondence with each other, and the game control microcomputer and the effect control microcomputer are system reset at the start of the power supply to the game machine. A system for outputting a reset signal for causing the reset power-off signal to be output on condition that the predetermined power supply voltage has reached a voltage level at which the game control microcomputer and the effect control microcomputer can operate. Reset means (reset signal circuit 941,
Delay circuits 942a to 946a and buffer circuit 942
b-946b).

According to such a configuration, the game control microcomputer and the effect control microcomputer can be surely set to the system reset state at the start of power supply to the gaming machine.

(4) In connection with the start of supply of electric power to the gaming machine, the time when the effect control microcomputer becomes operable is earlier than the time when the game control microcomputer becomes operable. Starting order regulation means (reset management circuit 94 in FIG. 7 etc.
0) is further included.

According to such a configuration, the starting sequence of the microcomputers is regulated so that the effect control microcomputer can operate earlier than the game control microcomputer, so that the power to the game machine is reduced. At the start of supply, the effect control microcomputer can surely receive the command from the game control microcomputer.

(5) The activation order regulation means regulates the activation order of the microcomputers by regulating the timing of outputting the reset release signal to the game control microcomputer and the effect control microcomputer (FIG. 9). ).

According to such a configuration, the starting sequence of the microcomputers is regulated by regulating the timing of outputting the reset release signal to the game control microcomputer and the effect control microcomputer, so that these microcomputers are more accurate. You can regulate when your computer is operational.

(6) The system reset means includes a capacitor for determining the timing of outputting the reset release signal, and the start order of the microcomputer is regulated by making the capacitance of the capacitor different (see FIG. 8). ).

According to such a configuration, the start-up order of the microcomputer is regulated by making the capacitance of the capacitor different for determining the timing of outputting the reset release signal, so that the start-up order of the microcomputer is simplified. It can be easily regulated using the configuration.

(7) The starting order regulation means is provided on each of the game control board and the electric component control board (FIG. 20).

According to such a configuration, since the starting order regulation means is provided on each of the game control board and the electric component control board, the starting order regulation means and the microcomputer of which the starting order is regulated are Since it is possible to shorten the distance between them, it is possible to make it difficult for noise to enter from the path between the boot order restricting means and the microcomputer whose boot order is to be restricted, and to restrict the boot order. It can be made less susceptible to noise.

(8) It is provided separately from the game control board and the electric component control board, and is used for each of the game control board and the electric component control board from a power source supplied to the gaming machine. A power supply board (power supply board 910) for generating electric power of a voltage is further included, and the activation order regulation means is provided on the power supply board (FIG. 7).

According to this structure, since the power supply board is provided with the activation sequence regulating means, it is possible to prevent an increase in the component mounting area on the electric component control board and to provide a plurality of electric component control boards. In this case, it is possible to reduce the number of manufacturing steps and the number of parts by disposing the start-up order regulating means collectively on the power supply board, so that the manufacturing cost can be reduced.

(9) The electric parts are movable members (center movable member 10, side movable members 18, 1) provided at a position where the player can visually recognize the movements and used for producing the game.
8) is included.

According to such a configuration, since the movable member which is an electric part is controlled by the effect control microcomputer, the game control microcomputer does not need to directly control the movable member, and thus the game control microcomputer. The control load on the computer can be reduced.

(10) The electric component (speaker 27) is provided on the basis of a command (sound control command) which is provided separately from the effect control microcomputer (display control microcomputer 800) and is transmitted from the effect control microcomputer. It further includes a sub-production control microcomputer (sound control microcomputer 700) for performing control to produce a game using the sub-production control microcomputer, in response to receiving the command from the sub-production control microcomputer. A command reception completion signal (feedback signal ACK) indicating that the reception is completed is returned to the sub-effect control microcomputer (FIG. 17), and the effect control microcomputer sends the command to the sub-effect control microcomputer. Output After that, when the command reception completion signal is not received within a predetermined period, a reset signal for resetting the state of the sub-effect control microcomputer is transmitted to the sub-effect control microcomputer (S82 in FIG. 15).

With this configuration, when the production control microcomputer does not receive the reception completion signal from the sub production control microcomputer within a predetermined period after outputting the command to the sub production control microcomputer. In addition, since the reset signal is transmitted to the sub-effect control microcomputer, it is possible to recover from the uncontrollable state of the sub-effect control microcomputer and the runaway operation.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In this embodiment, a pachinko game machine is shown as an example of the game machine,
The present invention is not limited to this, and may be another game machine such as a coin game machine or a slot machine, which has a predetermined electric component and produces a game by controlling the operation of the electric component. Any gaming machine capable of

First Embodiment First, the overall structure of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of the pachinko gaming machine 1 as viewed from the front, and FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1.

As shown in FIG. 1, the pachinko gaming machine 1 is
Outer frame 2a formed into a vertically long rectangular shape, and the outer frame 2a
A front frame 2b that is pivotally supported on the inner side of the frame and that is provided with the main components of the pachinko gaming machine 1 collectively, and a frame-shaped glass that is pivotally supported on the front upper part of the front frame 2b to be freely rotatable. It is composed of a door frame 2. Glass door frame 2
A ball hitting tray 3 is provided on the lower surface of the. In the front frame 2b, on the lower part of the hit ball supply tray 3, the hit ball supply tray 3 is provided.
A surplus ball receiving tray 4 for storing the stored balls overflowing from the ball and a hit ball operation handle (operation knob) 5 for firing a hit ball are provided. Further, a game board 6 having a game area 7 formed on the front side is detachably provided on the front frame 2b located behind the glass door frame 2. Front frame 2b and glass door frame 2
Is pivotally supported at an end portion on the left side when viewed from the front of the pachinko gaming machine 1, and is opened and closed with the pivotal support position as an opening and closing shaft. The glass door frame 2 is provided with a see-through window through which the game area 7 of the game board 6 can be almost seen through, and a glass plate is attached from the rear surface of the see-through window.

In this game area 7, a hit ball operation handle 5 is provided.
A game ball launched by a ball launching device (a ball launching device 34 shown in FIG. 2) in response to the operation of is guided and driven into the guide rail 76. The game ball is guided by the guide rail 76 and the game area 7 It is detected by a hitting ball switch 77 constituted by a proximity switch provided on the boundary between and. The number of game balls detected by the hit ball switch 77 is specified by a game control board 81 described later.

In the vicinity of the center of the game area 7, there is provided a variable display device 8 including a special symbol display section 9 made of a liquid crystal display and a normal symbol display section 3 made of an LED display.
The special symbol display unit 9 is not limited to the liquid crystal display, but CR
T (Cathode Ray Tube), FED (Field Emission Dis)
play), PDP (Plasma Display Panel), dot matrix, 7 segment LED, etc. LED (Light Emitti)
ng Diode), electroluminescence, a fluorescent display tube, and other image display type display devices. Further, the special symbol display unit 9 is not limited to an image display type display device, but is a rotary drum type that rotationally drives a rotary drum having a plurality of types of symbols drawn on the outer periphery, and a belt having a plurality of types of symbols drawn on the surface It may be a variable display device of other mechanical type (mechanical type driven by an electric drive source) such as one for rotating and moving a disc or one for rotating a disc on which a plurality of types of patterns are drawn (rotamint). Good.

The special symbol display portion 9 variably displays (also referred to as update display or variable display) special symbols as plural kinds of identification information (special identification information) such as numbers, characters other than numbers, figures, patterns, and characters. Possible, ordinary pattern display section 3
Is capable of variably displaying ordinary symbols as a plurality of types of identification information (ordinary identification information) such as figures. Here, the character means an image representing a human, an animal, an object, or the like displayed on the variable display device. The identification information variably displayed by the special symbol display unit 9 and the normal symbol display unit 3 may be any identification information as long as it is identification information such as numbers, characters, figures, patterns, characters, and the like. Numbers only, letters only, figures only, patterns only, characters only,
Alternatively, a combination of these may be used.

In the special symbol display portion 9, the left symbol, the middle symbol,
A plurality of (three) symbols called right symbols are arranged side by side and variably displayed, and a plurality of (three) display areas capable of deriving and displaying a display result are provided, and these symbols can be variably displayed by a method such as scrolling. . These display areas are arranged side by side in the left-right direction. Here, the case where the display area is fixed is shown as an example, but the display area is not limited to this, and the range of the display area is enlarged or reduced as a display area for variably displaying symbols. May be
Further, the position of the display area may be changed.
That is, the display area shown here may be any display area as long as the identification information is variably displayed and the display result can be derived and displayed.

Further, the normal symbol display portion 3 includes a hit indicator 31 capable of illuminating and displaying a hit symbol ◯, and a defect indicator 32 capable of illuminating and displaying a dissimilar symbol x. The hit indicator 31 and the off indicator 32 are LEDs.
It is configured to be lit and displayed by a (light emitting diode), and is provided side by side at a predetermined distance. In such a normal symbol display portion 3, the hit indicator 31
And blinking so that the off indicator 32 is alternately turned on (because it is turned on alternately, it means that each indicator is blinking at a predetermined cycle).
The mark and the X mark are variably displayed (also referred to as update display and variable display) at predetermined time intervals.

In the present embodiment, the case where the hit indicator 31 and the off indicator 32, which are LEDs, are used for the normal symbol display section 3 has been described, but the present invention is not limited to this. The other symbols that can be variably displayed may be used for the normal symbol display unit 3. In other words, the normal symbol may be one that can be recognized in some form by being distinguished from the special symbol. Here, the example in which the normal symbol display unit 3 and the special symbol display unit 9 are separately configured is shown, but the normal symbol display unit is the special symbol display unit 9
It may be configured by a part of the display area of the liquid crystal display constituting the above.

Further, the variable display device 8 is provided with a start memory indicator 18 and a gate passage memory indicator 41 each of which is composed of four LEDs. This starting memory indicator 1
Depending on the number of LEDs that are lit, the number of winnings to the starting winning opening 14 for starting the variable display of the special symbol is stored with an upper limit of 4 (called a starting winning memory).
Is displayed. In addition, the LE of the gate passage memory display 41
Depending on the number of lights of D, it is displayed that the number of passing game balls to the passing gate 11 for starting the variable display of the normal symbols is stored with the upper limit being 4 (normal start winning memory). .

In the passage of the game ball that has passed through the starting winning opening 14, there is provided a starting opening switch 17 for detecting a winning ball (winning ball) which is a winning gaming ball. When the sphere is detected, the control for turning on the starting memory indicator 18 is performed, and the control for starting the variable display of the special symbol is performed. Further, in the passage of the game ball that has passed through the passage gate 11, a gate switch 12 for detecting the game ball that has passed is provided, and when the gate switch 12 detects the game ball, the gate passage memory indicator 41. While the control for turning on is performed, the control for starting the variable display of the normal symbols is performed.

At a position below the variable display device 8, there is a starting winning opening 14 which also serves as a starting winning ball device 15 (electric tulip accessory) which is opened and closed by a solenoid (solenoid 16 in FIG. 3), and a solenoid (see FIG. 3). Solenoid 2
The variable winning ball device 30 having the special winning opening 20 opened and closed by the opening and closing operation of the opening and closing plate 29 driven by 1) is arranged in order from the top. The ball entering the starting winning opening 14 is detected by the starting opening switch 17 and then guided to the back surface of the game board. Also, the ball that entered the special winning opening 20,
V count switch 23 or count switch 22
After being detected by, is guided to the back of the game board. Of the balls that enter the variable winning ball apparatus 30 from the special winning opening 20,
The sphere detected by the V count switch 23 is then guided toward the count switch 22 and detected by the count switch 22. Therefore, all the balls that have entered from the special winning opening 20 are detected by the count switch 22 as a result.

The game board 6 is provided with a plurality of winning openings 19 and 24 as normal winning openings. Game ball winning hole 19,
The winning of 24 is detected by the winning opening switches 19a and 24a, respectively. Since the winning opening switches 19a and 24a are provided corresponding to the plurality of winning openings 19 and 24, respectively, a winning ball can be detected quickly for each winning opening 19 and 24.

On the left and right sides of the game area 7, there are provided decorative lamps 25 which are lit and displayed during the game. In addition, at the lower part of the game area 7, there is provided an outlet 26 for absorbing hit balls which have not been won. In addition, two speakers 27 that emit a sound effect are provided on the upper left and right sides outside the game area 7. A game effect LED (not shown) is provided on the outer periphery of the game area 7.

In addition, the game effect lamp 28a is the game area 7
Above, the game effect lamp 28b is on the left side of the game area 7,
The game effect lamps 28c are provided on the right side of the game area 7, respectively. In this example, the prize ball lamp 51 that lights up near the game effect lamp 28b when the prize ball is paid out.
Is provided, and a ball-out lamp 52 that is turned on when the supply ball runs out is provided near the game effect lamp 28a. Further, FIG. 1 also shows a card unit 50 which is installed adjacent to the pachinko gaming machine 1 and enables a ball lending by inserting a prepaid card. When the balance information is stored in the card inserted in the card unit, a game ball is lent to the player according to the withdrawal of the balance.

The card unit 50 has a usable indicator lamp 151 indicating whether or not it is usable, and a fraction (a number less than 100 yen) remaining in the balance information stored in the card, if the fraction remains. A fraction display switch 152 for causing a frequency display LED provided in the vicinity of the hitting ball supply tray 3 and a connecting board direction indicator 153 indicating which side the card unit 50 corresponds to the pachinko gaming machine 1. , A card insertion indicator lamp 154 indicating that a card has been inserted into the card unit 50, a card insertion slot 155 into which a card as a storage medium is inserted, and a card reader provided on the back surface of the card insertion slot 155. When checking the mechanism of the writer, the card unit 5
A card unit lock 156 for releasing 0 is provided.

Game area 7 which is shot from the hitting ball launching device 34
The hit ball (hit ball) that has entered comes down from the game area 7. When a hit ball is detected by the gate switch 12 through the passage gate 11, the normal symbol display unit 3 variably displays for a predetermined period based on the detection signal (blinks so as to alternately light as described above), The control is performed in which the display result is derived and displayed (the blinking is stopped and one of them is lit). If the variable display result of the normal symbol display unit 3 is a predetermined display mode as a winning symbol in the ordinary symbol, that is, a lighting display of the hit indicator 31 (lighting display of a circle), a start winning ball device 15 is controlled from the closed state to the open state for a predetermined time, and the hitting ball is ready to enter the starting winning opening 14. After that, the starting winning ball device 15 is closed.

When the hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17, if the variation of the symbol can be started, the special symbol display portion 9 is controlled to start the variable display of the special symbol. Be done. On the other hand, if the variable display of the symbols is not in a startable state, the start winning memory is incremented by one. Then, each time the variable display on the special symbol display portion 9 is started, the start winning memory is decremented by 1 and the LED is turned on
Is decremented by 1.

The variable display of the special symbol on the special symbol display portion 9 is stopped when a certain period of time has passed, and the display result is derived and displayed. When the combination of symbols at the time of stop becomes a combination of big hit symbols (for example, a specific symbol combination of 777 etc.), a big hit game state which is a specific game state advantageous to the player occurs, and a normal game state. The control for shifting from the jackpot to the gaming state is performed. In the big hit game state, by the operation of the opening / closing plate 29, the big winning opening 20 which is closed in the normal state is opened until a predetermined time has passed or until a predetermined number (for example, 10) of hit balls is won. Control is performed. And
A ball hits a specific winning area while the special winning opening 20 is open.
When it is detected by the count switch 23, the continuation right is generated and the control for opening the special winning opening 20 is performed again. The generation of such continuation right is allowed a predetermined number of times (for example, 15 rounds). Such control that repeats the generation of the continuation right is called repeat continuation control.

Although not shown in the drawing, inside the variable winning ball device 30 (in the special winning opening 20), there is provided a special winning opening guiding plate as a seesaw type ball distributing member. The special winning opening guide plate can be switched to either a state in which it is inclined toward the direction of the V count switch 23 or a state in which it is inclined toward the direction opposite to the direction of the V count switch 23. Solenoid (Solenoid 3 in FIG. 3
The drive is controlled by 3). In that case, when the special winning opening 20 is opened once (during one round), the distribution member is V until the V count switch 23 detects one ball.
By making the ball inclined toward the direction of the count switch 23, the balls are made to be easily detected by the V count switch 23, and after the V count switch 23 detects one ball, the distribution member is V Count switch 2
The ball is made to be in a state in which it is hard to be detected by the V count switch 23 by being inclined in a direction opposite to 3.

Further, during variable display of the variable display device 8 (in this case, during update display of the special symbol display portion 9),
A reach state (reach display) may occur. Here, the reach has a variable display device whose display state is changeable, the variable display device derives and displays the display results of a plurality of identification information at different times, and the plurality of display results are predetermined. In the gaming machine in which the game state becomes a specific game state that is advantageous to the player when the combination of the specified display modes is set, a part of the display results of the plurality of identification information is not yet derived and displayed. Then, a display state in which the display result of the identification information that has already been derived and displayed satisfies the condition that is a combination of the specific display modes. In other words, the reach is defined as a case where the display result of the identification information in the variable display device having a plurality of variable display portions whose display states can be changed is a combination of predetermined specific display modes. In a gaming machine in which the gaming state is a specific gaming state that is advantageous to the player, a variable display mode in which the combination of the specific display modes is easily displayed at a stage where the display result of the variable display device is not yet derived and displayed. It is a display state to make the player think that it has become. And, for example,
The reach display state includes a state in which variable display is performed by the plurality of variable display units while maintaining a state in which the combination of the specific display modes is complete. Furthermore, some of the reach is likely to cause a big hit when it appears, compared to a normal reach. Such a specific reach is called super reach.

The reach state is a display condition in which the display mode becomes the specific display mode even when the display control progresses after the variable display device is variably started to reach the stage before the display result is derived and displayed. It also refers to a display mode that does not deviate from the above.

The reach state is a display state at the time when the display control of the variable display device progresses to reach the stage before the display result is derived and displayed, and the display result is derived and displayed. It also refers to a display state in the case where at least a part of the display results of the plurality of variable display areas that have been determined in advance satisfy the condition of the specific display mode.

The combination of the special symbols in the special symbol display portion 9 when the variable display is stopped is the combination of the big hit symbols accompanied by the probability variation of the big hit occurrence (also called the combination of the probability variation symbols).
In the case of, or when the lottery indicating whether or not to change the probability of occurrence of a big jackpot is displayed on the display device and the winning is won, the probability of the next big jackpot becomes high. That is, in such a case, until a predetermined probability variation ending condition is satisfied, a probability variation state as a special game state (hereinafter, referred to as “probability variation”) becomes a more advantageous state for the player.

Further, in the probability change state, the probability that the stop symbol in the normal symbol display portion 3 becomes a winning symbol is increased, and the opening time of the starting winning ball device 15 is increased and the number of times of opening is increased (to open plural times). Will be performed. Further, in the probability variation state, time reduction control (variation time reduction control) is performed in which the time from the update start to the update stop in the special symbol display unit 9 and the normal symbol display unit 3 is reduced.

Next, it is determined whether to make a big hit or a big hit in the pachinko gaming machine shown in this embodiment (also called a big hit judgment), and whether to make a reach state (also called a reach judgment). , And, regarding the determination of the variation pattern in the update display of the special symbol, the processing procedure for the determination will be briefly described.

The decision whether to make a big hit or not
It is performed using the count value of the random counter for determining the big hit. This random counter is for randomly determining whether or not to generate a big hit. For example, the numerical data is updated by counting up from 0, counting up to a predetermined upper limit value, and then counting up from 0 again. It is a means. This counting operation is incremented by 1 in a predetermined cycle (every 2 msec). When a start winning is detected by the start opening switch 17, the count value of the random counter is extracted accordingly, and it is determined whether or not the extracted value matches a predetermined jackpot determination value. When the extracted value of the random counter and the jackpot determination value match, it is determined that a jackpot is to be generated, and the jackpot state is controlled. In normal stochastic states other than the stochastic state,
The jackpot determination value is set to one numerical value, for example. In the probability varying state, the jackpot determination value is set to a plurality of numerical values, so that in the probability varying state, the probability of occurrence of the jackpot is improved.

Next, the determination as to whether or not to reach the reach state (also referred to as the reach determination) is made by using the count value of the random counter for the reach determination. This random counter is for randomly determining whether or not a reach state is generated when it is determined to be out in the jackpot determination, and is numerical data that functions similarly to the random counter for determining the jackpot. It is an updating means, and when the value of the counter extracted at a predetermined timing such as the start of variation of the special symbol matches the predetermined reach determination value, the reach state is determined. On the other hand, when a big hit is determined in the big hit determination, the decision using the random counter for reaching is not made, and the reach state is reached in all cases.

In addition, when it is determined that the reach state is reached in the update display of the special symbol (including both the case of making a big hit and the case of making a big hit), The reach state variation pattern is selectively determined (randomly determined) from a plurality of types of variation patterns. Such fluctuation pattern determination is performed using the count value of the random counter for fluctuation pattern determination. This random counter is for randomly determining the variation pattern of the reach state, and is numerical data updating means that functions similarly to the random counter for determining the big hit, and is a predetermined number such as when the variation of the special symbol starts. It is determined that the value of the counter extracted at the timing is the fluctuation pattern corresponding to the matching one of the plurality of kinds of predetermined fluctuation pattern determination values.

Further, the determination of the stop symbol in the update display of the special symbol is performed by using the respective count values of the three random symbols for determining the stop symbols corresponding to the left, middle, and right symbols. Each of the random counters is for randomly determining a stop symbol of a corresponding special symbol, and is a numerical data updating means that functions similarly to a random counter for determining a big hit. Numerical data for symbol determination is associated with each of a plurality of types of stop symbols, and if it is determined that the symbol is out of sync, it is extracted from each random counter at a predetermined timing such as when the special symbol starts changing. The symbol corresponding to the numerical data that matches the value of the counter that has been set is determined as the left, middle, and right stop symbols. On the other hand, when it is determined to be a big hit, the symbol corresponding to the numerical data that coincides with the value of the counter extracted from the random symbol for the left symbol determination at the predetermined timing such as the start of fluctuation of the special symbol is left. , Middle, right is determined as each stop symbol.

In this pachinko gaming machine, the game control microcomputer determines the control content using such various random counters, and the game control is executed according to the determination.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. On the back surface of the variable display device 8, as shown in FIG. 2, a game machine tank 38 is provided on the upper part of the mechanism board 36, and the game ball is from above the pachinko game machine 1 installed on the game machine installation island. Game ball tank 3
8 are supplied. The game balls in the game ball tank 38 reach the ball payout device 97 through the guide gutter 39.

On the mechanism board 36, a display control unit 20a including a display control board 80 for controlling the special symbol display section 9 and the ordinary symbol display section 3 and a display device, and a game control micro covered with a board case 82. A game control board (also referred to as a main board) 31 on which a computer or the like is mounted, a game effect lamps 28a, 28b, 28c, a lamp control board 35 for sending a signal to a prize ball lamp 51 and a ball out lamp 52, and is related to voice. Power is supplied to a sound control board 70 that controls, a payout control board 37 that has a payout control microcomputer that controls payout of prize balls and the like, and electric components and electric component control boards provided in the pachinko gaming machine 1. A power supply board 910 and the like are installed. Further, at the lower part of the mechanism board 36, a hitting ball launching device 34 that launches a hitting ball to the game area 7 by utilizing the rotational force of the motor is installed. Further, on the side of the card unit 50 below the pachinko gaming machine 1, the pachinko gaming machine 1 and the card unit 5 are provided.
A connector 100 for communicatively connecting with 0 is provided. Further, the harness 55 having one end connected to the connector 100 has the other end connected to the connector 500 provided on the card unit 50.

The game ball that has passed through the guide trough 39 passes through the ball breakage detector 187 and reaches the ball payout device 97 through the supply troughs 186a and 186b. The game balls paid out from the ball payout device 97 are supplied to the hitting ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the communication port. A surplus ball passage communicating with a surplus ball tray 4 provided on the front surface of the pachinko gaming machine 1 is formed on the side of the communication port. A large number of prize balls based on winnings are paid out, the hitting ball supply tray 3 becomes full, and finally, when the game balls reach the communication port and further game balls are paid out, the game balls pass through the surplus ball passage and surplus balls. It is guided to the saucer 4. Further, when the game ball is paid out, the sensing lever pushes the full tank switch 48 to turn on the full tank switch. In this state, the rotation of the stepping motor in the ball payout device 97 is stopped, the operation of the ball payout device 97 is stopped, and the driving of the hitting ball launching device 34 is stopped as necessary. In this embodiment, as a ball payout device for paying out game balls by driving an electric drive source,
The ball payout device 97 for paying out the game ball by the rotation of the stepping motor is illustrated, but a ball payout device having a structure for sending the game ball by another drive source may be used, or a stopper may be provided by driving an electric drive source. You may use the ball payout device of the structure which removes and pays out by the own weight of the game ball.

Further, in order to perform the prize ball payout control, signals from the winning opening switches 19a, 24a, the starting opening switch 17 and the V count switch 23 are sent to the game control board 8.
Sent to 1. The CPU 56 of the game control board 81 knows that when the start opening switch 17 is turned on, a prize corresponding to the six prize ball payouts is generated. Also, the count switch 2
When 2 is turned on, it is known that a prize corresponding to the payout of 15 prize balls has occurred. And the winning opening switches 19a, 24
When a is turned on, it is known that a prize corresponding to the payout of 10 prize balls has occurred. In this embodiment, for example, the game ball that has won the winning opening 24 is detected by the winning opening switch 24a provided in the safe ball flow path from the winning opening 24, and the gaming ball that has won the winning opening 19 is detected. Is the winning opening 19
Winning hole switch 1 provided in the safe sphere flow path from
9a is detected.

FIG. 3 is a block diagram showing an example of the configuration of a control circuit including various control boards in the pachinko gaming machine 1. Note that FIG. 3 shows a game control board 81, a payout control board 37, a lamp control board 35, a sound control board 70, and a display control board 80 as control boards.

Variable winning ball apparatus 30 and winning ball apparatus 15
The operation is controlled by a game control board 81 provided (mounted) with the game control microcomputer 53. Further, the operation of the variable display device 8 is controlled by the display control board 80 provided (mounted) with the display control microcomputer 800. Further, during the game, the sound control board 70 provided with (mounted) the sound control microcomputer 700 controls to generate sound in accordance with the operations of the variable winning ball device 20 and the variable display device 40. . Further, during the game, the lamp control board 35 provided with (mounted on) the lamp control microcomputer 350 controls various lamps and light emitters such as LEDs. Further, when there is a prize in the game, the payout control board 37 provided with (equipped with) the payout control microcomputer 370 controls the payout of prize balls (prize balls) according to the prize. When the player operates the operation knob 5 to shoot a ball, the shooting control board 91 drives the drive motor 94 of the ball shooting device 34 (see FIG. 2) to shoot a pachinko ball. Control is performed.

Game control board 81, lamp control board 35,
Sound control board 70, display control board 80, payout control board 37
The firing control board 91 is composed of boards formed separately from each other, and each receives the power supply from the power supply board 910 to operate the various mounted components. The power supply board 910 provides each control board with a reset signal for resetting the system of each control microcomputer in addition to the power supply power. This reset signal is a low active signal, which is high level when the system reset is not performed, and is low level when the system reset is performed. In other words, the reset signal in this embodiment functions as a reset signal for causing a system reset in the case of a high level and as a reset release signal for canceling the system reset state in the case of a low level. To do.

On the game control board 81, a game control microcomputer 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 12, and a starting opening switch 1
7, V count switch 23, count switch 22,
Winning hole switch 19a, 24a, full tank switch 14
8, ball out switch 187, ball out detection switch 16
7, and a switch circuit 58 for giving signals from various switches such as a prize ball count switch 301A and a clear switch (clear switch 251 in FIG. 7) to the game control microcomputer, and a solenoid 16 for opening and closing the prize ball device 15. A solenoid 21 that opens and closes the opening and closing plate 29 of the special winning opening 20, and a solenoid circuit 59 that drives the solenoid 33 that drives the induction plate inside the special winning opening according to a command from the game control microcomputer 53 are provided.

Further, the game control board 81, according to the data given from the game control microcomputer 53,
The big hit information indicating the occurrence of the big hit, the effective start information indicating the number of starting winning prize balls used for the variable display start (start) of the special symbol display portion 9, and the probability variation information indicating that the probability variation has occurred, the hole management. An information output circuit 64 for outputting to a host computer such as a computer is included.

The game control microcomputer 53 has a ROM 54 which is an example of a storage means for storing a game control program, a RAM 55 which is an example of a storage means used as a work memory, and a CPU 56 which performs a control operation according to a control program. And a game control microcomputer including an I / O port unit 57. In this embodiment, the ROM 54 and the RAM 55 are mounted on the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The CPU 56 and the ROM 5
4, The RAM 55 does not have to be integrated into one chip.
That is, the ROM 54, the RAM 55, and the I / O port unit 57 may be external or built-in. Also,
The I / O port section 57 is a terminal capable of inputting / outputting information in the microcomputer. The game control microcomputer 53 receives signals from various connected switches (detectors) and controls the connected equipment to be controlled.

Further, the game control board 81 decodes an address signal given from the game control microcomputer 53 to decode one of the I / O port sections 57.
An address decoding circuit 67 for outputting a signal for selecting the / O port portion is provided. There is also switch information input from the ball payout device 97 to the game control board 81, but these are omitted in FIG.

Further, the special symbol display portion 9 for variably displaying the special symbol and the normal symbol display portion 3 for variably displaying the ordinary symbol
The display control is performed by a display control microcomputer 800 which is a display control means mounted on the display control board 80. The configuration of the display control microcomputer 800 is similar to that of the game control microcomputer 53 described above. Information such as a display control command as command information relating to display control of the variable display device 8 is transmitted from the game control board 81 to the display control board 80. The display control command shares command data with a lamp control command for lamp control and a sound control command for sound control, which will be described later, and the display control board 80
When the display control command is received, the display control of the special symbol display portion 9 and the ordinary symbol display portion 3 is performed according to the instruction of the display control command, and the command having the same data structure as the display control command is ramped. Output as a lamp control command for control and a sound control command for sound control.

The sound control command output from the display control board 80 is command information relating to control of sound such as a sound effect output from the speaker 27 by the sound control board 70.
Information such as an output sound control command is transmitted from the display control board 80 to the sound control board 70. Sound control board 70
In this case, a sound control microcomputer 700 (sound control means) is mounted, and this sound control microcomputer controls the sound output from the speaker 27 in response to the sound control command. The configuration of the sound control microcomputer 700 is the same as that of the game control microcomputer 53 described above.

Further, in this embodiment, the lamp control microcomputer 350, which is the lamp control means mounted on the lamp control board 35, controls the game effect lamp 28.
a, game effect lamps 28b, 28c, prize ball lamp 51,
The display control of the light emitters such as the out-of-bulb lamp 52, the start memory display 18, and the gate passage memory display 41 is performed. The configuration of the lamp control microcomputer 350 is similar to that of the game control microcomputer 53 described above.

The lamp control command output from the display control board 80 is command information for controlling the equipment controlled by the lamp control board 35. The lamp control command is sent from the display control board 80 to the lamp control board 35. Information such as commands is transmitted.

In the lamp control board 35, the lamp control microcomputer 350 controls the drive of the controlled device according to the lamp control command.

Further, from the game control board 81 to the payout control board 37, information such as a payout control command as command information relating to payout control of prize balls by the ball payout device 97 which is driven and controlled by the payout control board 37 is transmitted. It The payout control command is a command for instructing the number of payouts of prize balls according to the occurrence of winning balls. On the payout control board 37, a payout control microcomputer 370 (payout control means) is mounted, and the payout control microcomputer 3 is provided.
70 performs payout control of prize balls according to the payout control command. The structure of the payout control microcomputer 370 is the same as that of the game control microcomputer 53 described above. In addition, the payout control microcomputer 370 also controls the payout of lent balls according to a command from the card unit 50 by mutually communicating information with the card unit 50.

In this embodiment, the RAM provided on the game control board 81 and the payout control board 37 are backed up by a backup power supply. That is, even if the power supply to the pachinko gaming machine 1 is stopped, the contents of the RAM are saved for a predetermined period. Then, when the CPU in each control board detects a decrease in the power supply voltage, it performs a predetermined process (for example, a process of storing the contents of RAM) and then waits for the power supply to be restored. Further, when the power is turned on, the CPU in each control board restores the state before the power is turned off based on the stored data when the data is stored in the RAM.

Information transmitted from the game control board 81 to the display control board 80, the sound control board 70 from the display control board 80.
The information sent to the display control board 80 and the information sent from the display control board 80 to the lamp control board 35 include a control command indicating the content of a control command and an INT signal indicating the timing of fetching the command. Where the command is
One command is composed of 2 bytes of data, and 1 byte of MODE data for instructing the type of control mode,
It is composed of 1-byte EXT data for instructing concrete control contents in the control mode instructed by the MODE data.

In the case of this pachinko gaming machine 1, each of the game control microcomputer 53 and the display control microcomputer 800 controls by sequentially transmitting such 2-byte data to each control board of the command destination. Command the contents.

Next, the circuit configuration in the display control board 80 will be described in detail. FIG. 4 is a block diagram showing a circuit configuration in the display control board 80 together with a part of the circuit configurations of the variable display device 8 and the game control board 81.

In the game control board 51, the display control commands CD0 to CD7 are output from the output port (output port 2) 572 via the output buffer circuit 62A, and the output buffer circuit 620 is output from the output port (output port 0) 570. An INT signal for outputting an interrupt is output via.

The display control microcomputer 800 is
Display control CPU 101 having a built-in RAM, and control data ROM 10 storing display control control data
2, the CPU 101 uses the RAM as a work area and executes the programs stored in the ROM 102 to perform various display controls.

The CPU 101 receives an INT signal from the game control board 51 via the noise filter 107 and the input buffer circuit 105B. When the INT signal is input, the CPU 101 enters an interrupt operation state and the noise filter 107 is sent from the game control board 51. And the display control commands CD0 to CD7 are fetched via the input buffer circuit 105A. The output buffers 62A and 620 of the game control board 51 are circuits that output signals from the game control board 51 to the outside.
The signal is transmitted only in one direction (direction from the game control board 51 to the display control board 80).

Then, the display control CPU 101 carries out display control of the image displayed on the special symbol display section 9 and display control of the normal symbol displayed on the normal symbol display section 3 in accordance with the fetched display control command. A lamp control command and a reset signal can be transmitted to the lamp control board 35, and a sound control command and a reset signal can be transmitted to the sound control board 70. Further, when the reception of the control command is completed, each of the lamp control board 35 and the sound control board 70 displays a feedback signal ACK having a meaning as a reception completion signal for feeding back the fact that the reception is completed. Send to CPU 101.

When the feedback signal ACK is not returned from the lamp control board 35 within the predetermined period, the reset signal which is the system reset signal for resetting the lamp control microcomputer 350 is the display control C.
From PU 101 to lamp control microcomputer 350
, Which causes the lamp control microcomputer 350 to system reset. Further, when the feedback signal ACK is not returned from the sound control board 770 within the predetermined period, the sound control microcomputer 700
A display control CPU 101 transmits a reset signal, which is a system reset signal for resetting, to the sound control microcomputer 700, whereby the sound control microcomputer 700 is system reset.

Specifically, from the display control CPU 101, VDP (Vide) which is an IC (integrated circuit) for image display is displayed.
Display control data is transmitted to the display processor 103 as command data for displaying an image according to the display control command. When the VDP 103 receives the display control data, a feedback signal ACK having a meaning as a reception completion signal for feeding back that the reception is completed is sent from the VDP 103 to the display control CPU 10.
It is sent (replied) to 1. This feedback signal AC
When K is not returned within the predetermined period, the display control CPU 101 transmits a reset signal, which is a system reset signal for resetting the VDP 103, to the VDP 103. As a result, the VDP 103 is system reset.

The VDP 103 has a character ROM 86 for displaying an image in accordance with the received display control data.
Read the required data from. Then, the VDP 103
Image data to be displayed on the variable display device 40 is generated according to the read data, and the image data is stored in the VRAM.
(Video Random Access Memory) 87. The image data in the VRAM 87 is R (red), G
(Green), B (blue) signals (RGB signals) are converted and given to the special symbol display portion 9.

FIG. 4 also shows a reset circuit 83 for resetting the VDP 103 and an oscillator circuit 85 for supplying an operating clock to the VDP 103. The character ROM 86 stores frequently used image data. The frequently used image data is, for example, a person, an animal, or a character, a figure, or a symbol displayed on the variable display device 40. Such as an image.

Further, from the display control CPU 101 to the normal symbol display section 3, a control signal for operating the normal symbol display section 3 is given according to a display control command.

The display control CPU 101 transmits to the sound control board 70 a sound control command having the same data as the display control command received by the display control CPU 101. As described above, the sound control command has the same display control command and command data. When the display control CPU 101 receives the display control command, the command data is directly transmitted to the sound control board 70 as the sound control command. It When the sound control board 70 receives the sound control command, a feedback signal (ACK) for feeding back the reception is sent from the sound control board 70 to the display control CPU 101 (reply). When the feedback signal is not returned within the predetermined period, the display control CPU 101 transmits a reset signal, which is a system reset signal for resetting the sound control microcomputer 700, to the sound control board 70.
This reset signal is a low active signal and is high level when system reset is not performed,
It goes low when the system is reset.

Further, the display control CPU 101 transmits to the lamp control board 35 a lamp control command having the same data as the display control command received by the display control CPU 101. The lamp control command has the same command data as the display control command, and when the display control CPU 101 receives the display control command, the command is directly transmitted to the lamp control board 35 as the lamp control command. That is, the lamp control board 35
When the lamp control command is received, a feedback signal (ACK) for feeding back the reception is sent from the lamp control board 35 to the display control CPU 101 (reply). If the feedback signal is not returned within the predetermined period, a reset signal, which is a system reset signal for resetting the lamp control microcomputer 350, is transmitted from the display control CPU 101 to the lamp control board 35. This reset signal is a low active signal, which is high level when the system reset is not performed, and is low level when the system reset is performed.

In the CPU 101 for display control, the transmission and reception of various signals and data as described above between the sound control board 70 and the lamp control board 35 are carried out through the built-in I / O port 170. I / O ports 170 include input and output ports as shown in FIGS. 5 and 6. As will be described later, in the display control board 80, signals and data output from the I / O port are transmitted via the output buffer, and signals input to the I / O port are Although the data is transmitted via the output buffer, the illustration is omitted in FIG.

Next, the circuit configuration in the sound control board 70 will be described in detail. FIG. 5 is a block diagram showing a configuration example of the signal transmission portion of the sound control command in the display control board 80 and the sound control board 70.

The sound control board 70 is provided with a sound control microcomputer 700. The sound control microcomputer 700 is a CP with a built-in ROM and RAM.
Including U701.

Regarding the display control board 80 in FIG. 5, the I / O port 1 in the CPU 101 for display control described above is used.
One input port 176 and two output ports 174, 175 out of the input port and the output port constituting the 70.
, And two output buffers 190
A, 190B and one input buffer 190C are shown. Each of the input and output ports has a C
It is connected to the PU 101 by a bus.

Sound control reset signal and INT described above
The signal (strobe signal) is output from the output port 174 via the output buffer 190A. The sound control command is output from the output port 175 via the output buffer 190B. The feedback signal ACK described above is
It is input to the CPU 101 via the input buffer 190C and the input port 176.

In the sound control board 70, the display control board 8
The INT signal transmitted from 0 is input buffer 705A.
Is input to the CPU 701 via. Display control board 80
The display control command transmitted from the input buffer 70
It is input to the CPU 701 via 5B.

In the sound control board 70, the power supply board 91
A reset circuit 712 for providing a reset signal received from 0 to the CPU 701 is provided, and an output signal of the reset circuit 712 is output from one input terminal of an AND circuit 713 whose output terminal is connected to the reset terminal of the CPU 701. 713 is input. The logic level of the output signal of the reset circuit 712 becomes the same logic level as the reset signal from the power supply board 910. Then, the reset signal transmitted from the display control board 80 is AND
The other input terminal of the circuit 713 is input to the AND circuit 713.

Therefore, the reset signal from the power supply board 910 is not input (when the reset signal is high level), and the reset signal from the display control board 80 is not input (the reset signal is high). If it is a level), the output of the AND circuit 713 becomes a high level. On the other hand, in other cases, that is, when the reset signal is input from the power supply board 910 (when the reset signal is at the low level), the display control board 8
When at least one of the case where the reset signal from 0 is input (when the reset signal is low level) and the active state, the output of the AND circuit 713 becomes low level.

As a result, the AND circuit 713 causes the reset signal from the reset circuit 712 and the display control board 8 to operate.
When at least one of the reset signals from 0 becomes active, the reset signal given to the CPU 701 is made active (low level). When this reset signal becomes active, the sound control microcomputer 700 is reset.

In the sound control board 70, the above-mentioned feedback signal ACK is sent from the CPU 701 via the output buffer 705C to the input buffer 19 of the display control board 80.
Given to 0C.

The CPU 701 controls the speaker 27 to output a sound effect in accordance with the instruction of the received sound control command. Specifically, control is performed to output a sound effect in accordance with a sound output pattern defined according to each sound control command. The sound output pattern is stored in the ROM.

The input buffer circuits 705A and 705B transmit signals only in one direction (direction from the display control board 80 to the sound control board 70). Therefore, there is no room for signals to be transmitted from the sound control board 70 side to the display control board 80 side. Even if the circuit in the sound control board 70 is tampered with, the signal output by the tampering is not transmitted to the display control board 80 side. A noise filter may be provided on the input side of the input buffer circuits 705A and 705B.

In the ROM (not shown) of the sound control board 70, in order to generate voices corresponding to various sound control command data in the voice synthesizing circuit (for example, digital signal processor) 702 which is an IC for voice synthesizing. The sound control data of is stored. The sound control CPU 701 reads out sound control data corresponding to the received various sound control command data from the ROM and transmits the sound control data to the voice synthesis circuit 702.

In this embodiment, the voice synthesis circuit 702 is used.
Are controlled by a transfer request signal (SIRQ), a serial clock signal (SICK), a serial data signal (SI) as sound control data for sound control, and a transfer end signal (SRDY). Speech synthesis circuit 702
When SIRQ goes low, SI is taken in bit by bit in synchronization with SICK, and when SRDY goes low, the data consisting of each SI received up to that point is interpreted as one voice reproduction data. Speech synthesis circuit 702
When the sound control data is received by SI, generates a sound according to the received sound control data. Speech synthesis circuit 7
When 02 receives the sound control data, a feedback signal SIAK having a meaning as a reception completion signal for feeding back the fact that the reception is completed is sent to the voice synthesis circuit 702.
Is transmitted (replied) to the CPU 701. If the feedback signal SIAK is not returned within the predetermined period, the reset signal RESET, which is a system reset signal for resetting the voice synthesis circuit 702, is set to the CPU1.
01 to the voice synthesizing circuit 702, which resets the voice synthesizing circuit 702.

The voice synthesizing circuit 702 generates a voice or a sound effect according to the instruction by the sound control data from the CPU 701 and outputs it to the volume switching circuit 703. Volume switching circuit 70
3 sets the output level from the CPU 701 to a level according to the set volume and outputs it to the volume amplification circuit 704. The volume amplifier circuit 704 outputs the amplified audio signal to the speaker 27. As a result, the voice and the sound effect are output from the speaker 27.

Next, the circuit configuration in the lamp control board 35 will be described in detail. FIG. 6 is a block diagram showing a configuration example of the lamp control command signal transmission portion of the display control board 80 and the lamp control board 35.

The lamp control board 35 is provided with a lamp control microcomputer 35. The lamp control microcomputer 35 includes a CPU 351 including a ROM and a RAM.

Regarding the display control board 80 of FIG. 6, the I / O port 1 in the above-mentioned display control CPU 101 is used.
One input port 173 and two output ports 171 and 172 of the input port and the output port constituting the 70.
, And two output buffers 180
A, 180B and one input buffer 180C are shown. Each of the input and output ports has a C
It is connected to the PU 101 by a bus.

The reset signal and the INT signal (strobe signal) for lamp control described above are output port 171.
From the output buffer 190A. Ramp control commands are sent from output port 174 to output buffer 1
It is output via 90B. The feedback signal ACK described above corresponds to the input buffer 190C and the input port 1
It is input to the CPU 101 via 76.

The CPU 101 uses the I / O port 170.
In the case where the CPU is not built in, the CP and the input buffer and the output buffer are provided outside the CPU 101.
An I / O port is provided between the U101 and the U101.

The lamp control CPU 351 outputs a lighting / extinguishing signal to each lamp / LED in accordance with the lamp lighting / extinguishing pattern defined according to each lamp control command. In addition, the lighting / extinguishing pattern is RO
It is stored in M.

In the lamp control board 35, the INT signal transmitted from the display control board 80 is input to the input buffer 35.
It is input to the CPU 351 via 5A. The display control command transmitted from the display control board 80 is input to the CPU 351 via the input buffer 355B.

Further, the lamp control board 35 is provided with a reset circuit 352 for giving the reset signal received from the power supply board 910 to the CPU 351, and the output signal of the reset circuit 352 has its output terminal connected to the reset terminal of the CPU 351. One of the input terminals of the AND circuit 353 is input to the AND circuit 353. The logic level of the output signal of the reset circuit 352 is determined by the power supply board 91.
It has the same logic level as the reset signal from 0. Then, the reset signal transmitted from the display control board 80 is
From the other input terminal of the AND circuit 353 to the AND circuit 35
Input to 3.

Therefore, the reset signal from the power supply substrate 910 is not input (when the reset signal is high level) and the reset signal from the display control substrate 80 is not input (the reset signal is high). If it is a level), the output of the AND circuit 353 becomes a high level. On the other hand, in other cases, that is, when the reset signal is input from the power supply board 910 (when the reset signal is at the low level), the display control board 8
In at least one of the case where the reset signal from 0 is input (when the reset signal is low level), the output of the AND circuit 353 becomes low level.

As a result, the AND circuit 353 receives the reset signal from the reset circuit 352 and the display control board 8.
When at least one of the reset signals from 0 becomes active, the reset signal given to the CPU 351 is made active (low level). When the reset signal becomes active, the lamp control microcomputer 350 is reset.

In the lamp control board 35, the above-mentioned feedback signal ACK is given from the CPU 351 to the input buffer 180C of the display control board 80 via the output buffer 355C.

The CPU 351 lights up the game effect lamps 28a, the game effect lamps 28b and 28c, the prize ball lamp 51, the out-of-ball lamp 52, the start memory indicator 18, the decoration lamp 25, etc. in accordance with the instruction of the received lamp control command. / Outputs a signal to control turning off.

The input buffer circuits 355A and 355B are unidirectional (from the display control board 80 to the lamp control board 3).
Signal only in direction 5). Therefore,
There is no room for signals to be transmitted from the lamp control board 35 side to the display control board 80 side. Even if the circuit in the lamp control board 35 is tampered with, the signal output by the tampering is not transmitted to the display control board 80 side. A noise filter may be provided on the input side of the input buffer circuits 355A and 355B.

Next, the circuit configuration of the power supply board 910 will be described. FIG. 7 is a block diagram showing a configuration example of the power supply board 910.

The power supply board 910 is AC24 in this example.
V, VSL (DC + 30V), DC + 21V, DC + 12
Generates V and DC + 5V. Further, the capacitor 916 serving as a backup power source is charged from DC + 5V (VBB), that is, from the power source line for driving the IC or the like on each substrate. VSL is generated in the rectifier circuit 912 by rectifying and boosting AC24V with a rectifying element.

The transformer 911 converts the AC voltage from the AC power supply into 24V. 24V AC voltage is applied to connector 9
It is output to 15. In addition, the rectifier circuit 912 is an AC 24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. A low-pass filter is provided in the rectifier circuit 912 and the transformer 9
The noise generated between 11 and the rectifier circuit 912 is removed. The DC-DC converter 913 has one or a plurality of converter ICs 920 (only one is shown in the figure), generates + 21V, + 12V and + 5V based on VSL and outputs them to the connector 915.

A relatively large-capacity capacitor 923 is connected to the input side of converter IC 920. Therefore, when the power supply to the pachinko gaming machine from the outside is stopped, the DC voltage such as + 21V, + 12V, and + 5V drops relatively gently. Further, the input side of the connector 915 also has a capacitor 92 of a relatively large capacity.
4 is connected. Therefore, the + 30V DC voltage output to the connector 915 decreases relatively slowly. As a result, the capacitors 923 and 924 act as a backup power supply source. Connector 915
Is connected to a relay board, for example, and the relay board supplies electric power of a voltage required for each control board and mechanical parts. The input side of the transformer 911 has a power switch 9 for stopping and starting power supply to the game machine.
14 are installed.

However, the power supply board 910 may be provided with respective connectors reaching the respective control boards, and the respective voltages reaching the respective boards may be supplied from the power supply board 910 without passing through the relay board. Further, although one connector 915 is representatively shown in FIG. 7, the connector is provided for each control board.

DC + from the DC-DC converter 913
The 5V line branches to form a backup + 5V line. A large-capacity capacitor 91 is provided between the backup DC + 5V (Vcc) line and the ground level (GND).
6 is connected. The capacitor 916 has power so that the memory state can be retained with respect to the backup RAM of each control board (RAM that is backed up by the power source, that is, memory means that can be in the memory content retaining state) when the power supply to the gaming machine is cut off. Will be the backup power supply. The backup RAM in the case of the game control board 81 is the RAM 55 itself. Further, a backflow prevention diode 917 is inserted between the DC + 5V line and the backup DC + 5V (VBB) line. In this embodiment, + 5V for backup is
It is supplied to the game control board 81 and the payout control board 77. In this way, when the power supply is cut off,
By supplying backup power from the capacitor 916, the stored data is automatically backed up and stored in the backup RAM. Regarding the backup RAM, the storage data in all storage areas of the area for storing data may be backed up, or the storage data in some storage areas may be backed up. If the storage data of some storage areas is backed up, it is necessary to store the data necessary for the game control recovery at the time of power recovery in the storage area of the RAM to be backed up.

A battery that can be charged from a + 5V power source may be used as the backup power source. When a battery is used, a rechargeable battery is used which loses its capacity when the power is not supplied from the + 5V power source for a predetermined time. Also, instead of the capacitors 923 and 924, +3
A battery that can be charged from a 0V power source may be used. When the battery is used as described above, the battery does not have to have a charging function, and for example, a battery having no charging function such as a NiCd battery, an alkaline battery, or a manganese battery may be used.

Further, the power supply board 910 is mounted with a power supply monitoring IC 902 which constitutes a power supply monitoring circuit. The power supply monitoring IC 902 detects the occurrence of a decrease in power supply to the pachinko gaming machine by introducing the power supply voltage VSL and monitoring the power supply voltage VSL. Specifically, the power supply voltage V
When SL falls below a predetermined value (+22 V in this example), the power supply is shut down or a voltage drop occurs, and a power shutoff signal is output. The power supply voltage to be monitored is the power supply voltage of the circuit element mounted on each electric component control board (+5 in this example).
It is preferable that the voltage is higher than V). In this example, the voltage VSL (+30
V) is used. The power-off signal from the power monitoring IC 902 is supplied to various control boards such as the game control board 51 and the payout control board 77. In each of the control boards such as the game control board 51 and the payout control board 77 which have received the power-off signal,
A power-off process for backing up and storing predetermined control data is executed. The backup-stored control data is continuously stored for a predetermined period. By storing the control data when the power is cut off as described above, for example, when the power supply is cut off due to an abnormal state such as a power failure, the backup control data is used when the power supply is restored. By restarting the control by the control, the control is restarted from the control state when the power supply was cut off.

The predetermined value for the power supply monitoring IC 902 to detect a power failure or a voltage drop is lower than the normal voltage, but is a voltage at which the CPU on each control board can operate for a while. In addition, the power supply monitoring IC 902 is a CP
Voltage for driving circuit elements such as U (+5 in this example)
The voltage is higher than V) and is configured to monitor the voltage immediately after the conversion from AC to DC, so that the monitoring range can be expanded with respect to the voltage required by the CPU. Therefore, more precise monitoring can be performed.

Further, VSL (+ 30V) is used as the monitoring voltage.
In the case of using, since the voltage supplied to the various switches of the gaming machine is + 12V, it can be expected to prevent erroneous switch-on detection when the power is cut off. That is, if the voltage of the + 30V power supply is monitored, it will be created after + 30V is created.
It can be detected before 12V starts to drop. Therefore, if the voltage of the + 12V power supply drops, the switch output will be in the ON state, but if the + 30V power supply voltage, which drops faster than + 12V, is monitored and power failure is recognized, the power supply is turned on before the switch output turns on. It is possible to enter a state of waiting for restoration and enter a state in which no switch output is detected.

Further, VSL (+ 30V) as a monitoring voltage
Unlike the input line to the power supply monitoring IC 902, VSL (+3
A large-capacity capacitor 924 is connected to the input line of the 0 V) connector 915. Therefore, VSL (+30 V) as the monitoring voltage is V output to the connector 915 to which the large-capacity capacitor 924 is connected.
It drops faster than SL (+ 30V). That is, even after VSL (+ 30V) as the monitoring voltage starts to drop, VSL as the voltage supplied to the solenoid, the motor, etc. is maintained for a predetermined period.
SL (+ 30V) gradually decreases. Therefore,
Even when VSL (+ 30V) as the monitoring voltage starts to drop, the solenoid, motor, etc. can be driven for a predetermined period. Further, it is possible to recognize the stop of the power supply to the power source before the VSL (+ 30V) output to the connector 915 starts to drop.

Further, since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric component control board, it is possible to supply the power-off signal from the power supply monitoring circuit to the plurality of control boards. No matter how many control boards require a power-off signal, only one power supply monitoring means needs to be provided. Therefore, even if each control means (microcomputer) in each control board performs a return control described later, a gaming machine. The cost of will not improve much.

Further, the detection output (power cutoff signal) of the power supply monitoring IC 902 is transmitted as a power cutoff signal to each control board (for example, the game control board 51, the payout control board 77) via the buffer circuits 918 and 919. It The buffer circuits 918 and 919 include a delay circuit section, and are configured so that the power-off signal is first transmitted to the game control board 51 and then the power-off signal is transmitted. The detection output of the power supply monitoring IC 902 is, for example, 1
It is also possible to transmit one detection output to the relay board and distribute the same signal from the relay board to each control board. In addition, a buffer circuit may be provided according to the number of substrates that require a power-off signal. Furthermore, the game control board 51 and the payout control board 77
For the power-off signal output to and, the monitoring voltage of the power-source monitoring circuit that outputs the power-off signal may be different.

The clear switch 921 is a push button structure switch, and when it is pushed down, a low level (on state) clear signal is output and transmitted to the game control board 51 or the like via the connector 915. If the clear switch 921 is not pushed down, a high-level (off-state) clear signal is output.

The reset management circuit 940 is a circuit for managing a reset signal given to each of the game control board 81, the display control board 80, the lamp control board 35, the voice control board 70, and the payout control board 37. is there. The reset management circuit 940 monitors the power supply voltage VSL, and when the power is off, the power supply voltage VSL has a predetermined value (+ 9V in this example).
In the following cases, a reset signal for system reset is given to each control board. This reset signal is a low active signal, which is high level when the system reset is not performed, and is low level when the system reset is performed. In this way, after the power-off processing is performed based on the power-off signal described above,
The system will be reset.

When the power is turned on, the power supply voltage VSL
Is above a predetermined value (+ 22V in this example) at which various control microcomputers can operate, the power-off signal is stopped and the output of the power-off signal is stopped, but the reset management circuit 940 does not operate when the power is turned on. Power supply voltage VSL
After the output of the power-off signal is stopped (after the power supply voltage VSL becomes + 22V in this example), the reset signal applied to each control board is set to the high level and the system reset state in each control board is monitored. To cancel. When the reset signal is set to the high level, this reset signal will be used as the reset release signal.

Such a reset signal (a signal having two functions of a system reset signal and a system reset release signal) is output by the reset management circuit 940.
After being first output to the display control board 80, the lamp control board 35, the sound control board 70, and the payout control board 37,
The output order is managed so as to be output to the game control board 81. As a result, the starting sequence of the control microcomputer provided on each control board is regulated.

In the following description, the voltage drop state including the power-off state in which the power-off signal is output is generically referred to as the power-off state. The clear switch 921 may be a switch having a structure other than the push button structure described above.

Next, the reset management circuit 9 shown in FIG.
The configuration of 40 will be described. FIG. 8 is a block diagram showing the configuration of the reset management circuit 940. The reset management circuit 940 includes a reset signal circuit 941, a plurality of delay circuits 942a to 946a, and a plurality of buffer circuits 942.
b to 946b.

The reset signal circuit 941 is a power monitor I
The power supply voltage VSL equal to the power supply voltage monitored by the C902 is monitored, and the voltage level of the power supply voltage VSL is a predetermined value (the power supply monitoring IC
2 becomes lower than the voltage level at which the power-off signal is output) or less, the output becomes low level, and when the voltage level exceeds a predetermined value, the output becomes high level. The signal output from the reset signal circuit 941 is a plurality of delay circuits 94.
2a to 946a.

The signal inputted to the delay circuit 942a is outputted from the delay circuit 942a via the buffer circuit 942b as a reset signal given to the payout control board 37. The signal input to the delay circuit 943a is the delay circuit 9
The signal 43a is output as a reset signal to the display control board 80 via the buffer circuit 943b. The signal input to the delay circuit 944a is output from the delay circuit 944a via the buffer circuit 944b as a reset signal applied to the lamp control board 35. Delay circuit 9
The signal input to 45 a is output from the delay circuit 945 a via the buffer circuit 945 b as a reset signal applied to the sound control board 70. The signal input to the delay circuit 946a is output from the delay circuit 946a to the buffer circuit 9
It is output as a reset signal given to the game control board 81 via 46b.

Thus, the reset signal output to each control board is a low active signal, and the CPU of each control board is in an operable state when the reset signal applied to the reset terminal is at a high level. When the reset signal becomes low level, a reset (system reset) for returning the operating state to the initial state is performed.

The delay circuits 942a to 946a basically delay the reset signal so that the reset signal becomes high level after a predetermined time delay after the output of the power-off signal is stopped when the power is turned on. The time and the reset signal are first displayed on the display control board 80 and the lamp control board 3.
5, the delay time of the signal is set so that the delay time for delaying the signal to be output to the game control board 81 after being output to the voice control board 70 and the payout control board 37 can be secured. . Here, after the output of the power-off signal is stopped, the signal is delayed so that the reset signal becomes high level after a predetermined time delay, that is, when the reset state is released by the reset signal, that is, when the power is supplied. This is to prevent the power-off process from being executed by the power-off signal when the power is restarted and restored.

Each of the delay circuits 942a to 946a is a signal processing circuit including a capacitor for signal delay, and the delay time is set by the magnitude of the capacitance of the capacitor. Therefore, the delay circuits 942a to 946a
In each of the above, the delay time is determined by the capacitance of the capacitor, and the delay time can be lengthened as the capacitance increases, for example.

After the output of the power-off signal is stopped,
Since the delay time for delaying the reset signal so that the reset signal becomes high level after a predetermined time delay is common to all reset signals, a delay circuit is provided in the reset signal circuit 941 to collectively reset the reset signals. It may be delayed. In that case, after the reset signal is output to the display control board 80, the lamp control board 35, the voice control board 70, and the payout control board 37, the game control board 8
In order to delay the reset signal so that it is output to 1, the delay circuit 9 is provided without providing the delay circuits 942a to 945a.
It is possible to provide only 46a and realize such a function.

Next, the game control board 8 when the power is turned on
The start timing of the microcomputer in each of the control boards 1, 1, the display control board 80, the lamp control board 35, the sound control board 70, and the payout control board 37 will be described. FIG. 9 is a timing chart showing the activation timing of the microcomputer in each control board.

Referring to FIG. 9, as shown in FIG. 9B, when power is turned on in the pachinko gaming machine 1 and power supply is started, first, the display control board 80, The reset signal output from the power supply board 915 is input to the lamp control board 35, the voice control board 70, and the payout control board 37. In response to the reset signal, each of the display control board 80, the lamp control board 35, the voice control board 70, and the payout control board 37 undergoes a predetermined security check and then starts executing the control program. To be done.

Then, as shown in (a), the reset signal is delayed by a predetermined delay time t,
The reset signal output from the power supply board 915 is input to the game control board 81. In response to the reset signal, the game control board 81 performs a predetermined security check, and then starts executing the control program.

In this way, the reset management circuit 9 described above is used.
By 40, the reset signal is managed so that the reset signal is output to the display control board 80, the lamp control board 35, the voice control board 70, and the payout control board 37, and then to the game control board 81. As a result, the display control board 80, the lamp control board 35, the sound control board 70,
And, after each control microcomputer of the payout control board 37 is activated, the control microcomputer of the game control board 81 is activated.

Next, the display control microcomputer 80
The control executed by the 0 CPU will be described. First, the main process of display control will be described. FIG. 10 is a flowchart showing a display main process executed by the display control microcomputer 800.

Referring to FIG. 10, in the display main process, first, in step S (hereinafter simply referred to as S) 1, execution of the interrupt process is prohibited. Then, in S2, the RAM 55 is cleared (initialized). After that, predetermined initialization processing such as initialization of the designated address of the stack pointer, initialization of various registers and flags, and setting of the timer interrupt time that defines the timing of executing the timer interrupt processing described later is performed. Be done. And S
4, the execution of interrupt processing (timer interrupt processing) is permitted.

Next, in S5, it is judged whether or not an interrupt flag, which is a flag that is turned on (set) when a timer interrupt process described later is executed, is turned on (set). It In S5, it waits until the interrupt flag is turned ON, and the process proceeds to S6.

If the process proceeds to S6, the interrupt flag is cleared (reset). Next, in S7, it is determined whether or not the value of the reset timer for VDP reset has become 0. Here, the reset timer for VDP reset is a timer set in a VDP reset process described later, and when the VDP 103 is reset, the display control of the display control is performed until the VDP 103 becomes stable and operable after the reset. It is a timer that measures (counts down) a predetermined time in order to stop the execution (put in a waiting state).

If it is determined in S7 that the value of the reset timer is not 0, the display control (S8-S1) is performed.
In order to stop the execution of the process of 2), the process proceeds to S14 described later. On the other hand, when it is determined in S7 that the value of the reset timer has become 0, the process proceeds to S8, and the received command recognition process is executed. In this received command recognition processing, the received display control command is input (stored) in a buffer serving as a work area of the RAM, and the content of the command is recognized.

Next, in S9, it is determined whether or not to give a advance notice (announce that the reach state will occur) and an advance notice such as a big hit notice (announce that the big hit state will occur). Random counter for advance notice determination (numerical data updating means) used based on determination
A counter update process is performed to update various counters such as. Here, in the case of this pachinko gaming machine 1,
Whether or not to give the advance notice as described above is determined by the display control microcomputer 800 based on the numerical data extracted from the advance notice determination random counter at a predetermined timing.

Next, in S10, a sound control command output process for outputting a sound control command to the sound control microcomputer 700 is performed based on the display control command recognized in S8. The detailed content of the sound control command output process will be described later with reference to FIG. And S
11, the lamp control command output process of outputting the lamp control command to the lamp control microcomputer 350 is performed based on the display control command recognized in S8.

Next, in S12, display process processing is performed. In this display process process, a process for performing image display on the special symbol display portion 9 according to the game state is performed by sequentially executing a plurality of display control processes. Next, in S13, a display data output process for outputting display control data for displaying an image to the VDP 103 according to the display process process in S12 is performed. Detailed contents of the display data output process will be described later with reference to FIG. It progresses to S14 after S13.

When the process proceeds to S14, the VDP reset process for resetting the VDP 103 is performed when the feedback signal in response to the display control data transmitted to the VDP 103 is not returned. Detailed contents of the VDP reset process will be described later with reference to FIG.

Next, in S15, a sound CPU reset process for resetting the sound control microcomputer 700 is performed when a feedback signal in response to the sound control command transmitted to the sound control microcomputer 700 is not returned. The details of the sound CPU reset process will be described later with reference to FIG.

Next, in S16, the lamp CPU reset process for resetting the lamp control microcomputer 350 is performed when the feedback signal in response to the lamp control command transmitted to the lamp control microcomputer 350 is not returned. After S16,
It returns to S5 mentioned above.

Next, the display control microcomputer 80
The timer interrupt process executed by 0 will be described. Figure 11
9 is a flowchart showing a timer interrupt process executed by the display control microcomputer 800.

In the timer interrupt process, the time value of the timer for timer interrupt managed by the display control microcomputer 800 is the set value (timer interrupt time set in S3:
Specifically, the execution is started every 0.002 seconds. The timer interrupt process ends after the above-described interrupt flag is turned on in S20.

Next, the display control microcomputer 80
The sound control command output process (S10 of FIG. 10) executed by 0 will be described. FIG. 12 is a flowchart showing a sound control command output process executed by the display control microcomputer 800.

First, in S31, it is determined whether or not the output flag indicating the output state of the sound control command is ON. The output flag in this case is a flag that is turned on when a display control command (common to the sound control command) is received, and when the display control command is received, it is necessary to transmit the sound control command based on it. Therefore, for example, in the command recognition processing described above, O
The N state is set.

Next, in S32, the output flag indicating the output state of the sound control command is cleared.
Then, in S33, the process of setting the number of processes to "2" is performed. Here, the number of processes is data indicating the number of bytes (the number of times of transmission) to be transmitted in order to transmit one command of the display control command composed of 2 bytes by dividing it by 1 byte into 2 times. In S33, numerical data indicating 2 bytes corresponding to one command is set as the processing number.

Next, in S34, a process of loading (reading) the data of the address outputting the data among the addresses of the buffer storing the received command is performed. Then, in S35, a process of setting the data read in S34 in a state in which it can be output is performed. Next, in S36, a process of outputting the data set in S35 is performed. As a result, 1-byte data of the command received as the display control command and output as the sound control command is output as the sound control command.

Next, in S37, the process of setting the ACK waiting counter is performed. Here, the ACK wait counter is a counter for defining the time to wait for the reply of the feedback signal ACK from the sound control microcomputer 700 after transmitting the sound control command, and is set to a predetermined number and then down-counted. It The ACK wait counter defines a predetermined time to wait for the feedback signal ACK to be returned.

Next, in S38, a process of subtracting (counting down) the value of the ACK waiting counter set in S37 is performed (for example, 1 is subtracted). Next, in S39, it is determined whether or not the value of the ACK waiting counter set in S38 has become "0". When it is determined in S39 that the value becomes “0”, it means that an abnormal state occurs in which the feedback signal ACK is not returned for a predetermined period, and the communication between the display control microcomputer 350 and the sound control microcomputer 700 is performed. Considering that an error has occurred, S46
Then, the processing for turning on the communication error flag is performed, and the sound control command output processing ends. here,
The communication error flag is a flag indicating whether or not a communication error has occurred between the display control microcomputer 350 and the sound control microcomputer 700, and is turned on when a communication error occurs. The communication error in this case is caused by the cause such as the control inoperable state of the sound control microcomputer 700, the runaway, and the abnormality of the communication path. When the communication error flag is turned on, the sound control microcomputer 7
00 is reset.

On the other hand, if it is determined in S39 that the value of the ACK wait counter set in S38 is not "0", the process proceeds to S40, in which feedback from the port 4, that is, the sound control microcomputer 700 is performed. A process of checking the reception status of the port that receives the signal ACK is performed. Then, the process proceeds to S41 and S40.
As a result of the check, it is determined whether or not the feedback signal ACK has been received. If it is determined in S41 that the feedback signal ACK has not been received, S38
Then, the above-mentioned processing is carried forward. On the other hand, S4
If it is determined by 1 that the feedback signal ACK has been received, the process proceeds to S42 and a process of stopping the output of the output data is performed.

Next, in S43, a process of subtracting "1" from the number of processes described above is performed. As a result, when there is a reception response for the output 1 byte of the command, it is determined that the data transmission is normally performed, and the number of processes is reduced.

Then, in S44, it is determined whether or not the current number of processes is "0". If it is determined in S44 that the number of processes is “0”, it is considered that the 2-byte command has been normally transmitted, and this sound control command output process ends. On the other hand, the processing number is "0" by S44.
If it is determined that it is not, the process proceeds to S45, and in order to output the remaining 1-byte data, the offset value is added to the address of the buffer in which the received command is stored. The stored address is set.

After S45, the process returns to S34, and the above-mentioned processing is carried over to output the data of the second byte (the remaining 1 byte) of the command. As described above, in the sound control command output process, the data of the command received as the display control command is transmitted to the sound control microcomputer 700 as the sound control command. Then, when the sound control command is transmitted, if there is no reply of the feedback signal ACK from the sound control microcomputer 700, it is judged as a communication error state.

Next, the display control microcomputer 80
Lamp control command output processing executed by
S11) of 0 will be described. The content of the lamp control command output processing is that each step of the sound control command output processing shown in FIG. 12 is replaced for the lamp control command. Therefore, redundant description will not be repeated here. As a result, in the lamp control command output process, the data of the command received as the display control command is transmitted to the lamp control microcomputer 350 as the lamp control command. When the lamp control command is transmitted, the lamp control microcomputer 3
If the feedback signal ACK is not returned from 50, the communication error state is determined for the same reason as in the sound control command output process.

Next, the display control microcomputer 80
Display data output processing executed by 0 (S1 in FIG. 10).
3) will be described. FIG. 13 is a flowchart showing a display data output process executed by the display control microcomputer 800.

First, in S51, it is determined whether or not the output flag indicating the output state of the display control data is ON. The output flag in this case is a flag which is turned on when the display control command is received, and when the display control command is received, it is necessary to transmit the display control data based on the display control command. It is turned on in the reception command recognition process.

Next, in S52, a process of clearing the output flag indicating the output state of the display control data is performed.
Then, in S53, the process of setting the number of processes to "2" is performed. Here, the number of processings is the number of bytes to be processed for transmission so that one piece of display control data composed of 2 bytes is divided into two 1 byte transmissions.
Is data indicating. In this S53,
Numerical data indicating 2 bytes corresponding to 1 data is set.

Next, in S54, of the addresses of the buffer in which the display control data for displaying according to the progress of the above-mentioned display process processing is stored, the data of the address for outputting the data is loaded (read). Processing is done. Then, in S55, the process of setting the data read in S54 in a state in which it can be output is performed. Next, in S56, a process of outputting the data set in S55 is performed. As a result, 1-byte data of the display control data to be output according to the received display control command is output as the display control data.

Next, in S57, a process of setting the ACK waiting counter is performed. Here, the ACK wait counter is a counter for defining the time to wait for the reply of the feedback signal ACK after transmitting the display control data, and is set to a predetermined number and then down counted.
With this ACK waiting counter, the feedback signal A
The time to wait for a reply of CK is defined as a predetermined time.

Next, in S58, a process of subtracting (counting down) the value of the ACK wait counter set in S57 is performed (for example, 1 is subtracted). Next, in S59, it is determined whether or not the value of the ACK waiting counter set in S58 has become "0". The case where it is determined to be “0” in S59 is a case where an abnormal state occurs in which the feedback signal ACK is not returned for a predetermined period, and a communication error occurs between the display control microcomputer 350 and the VDP 103. In step S68, the process for turning on the reset flag is performed, and the display data output process ends. Here, the reset flag means VDP
This is a flag indicating whether or not to reset 103, and when a communication error occurs, it is necessary to reset the VDP 103, so it is turned on. The communication error in this case is caused by a cause such as an inoperable state of the VDP 103, a runaway, and an abnormality of the communication path. If the reset flag is turned on, VD
The system of P103 is reset.

On the other hand, if it is determined in S59 that the value of the ACK wait counter set in S58 is not "0", the process proceeds to S60 and the feedback signal ACK from the port 4, that is, the VDP 103 is received. A process for checking the reception status of the port to be performed is performed. Then, the process proceeds to S61, and as a result of the check in S60,
It is determined whether or not the feedback signal ACK has been received. If it is determined in S61 that the feedback signal ACK has not been received, the process returns to S58 and the above-described processing is carried forward. On the other hand, if it is determined in S61 that the feedback signal ACK has been received, S
The process proceeds to step 62, where processing for stopping the output of the data being output is performed.

Next, in S63, the process of subtracting "1" from the number of processes described above is performed. As a result, when a response is received for the output 1 byte of the display control data, it is determined that the data transmission is normally performed, and the number of processes is reduced.

Then, in S64, it is determined whether or not the current number of processes is "0". When it is determined in S64 that the number of processes is “0”, it is considered that the 2-byte command is normally transmitted, the above-described transfer end signal (SRDY) is output in S66, and after a lapse of a predetermined period, the S67 Output is stopped. After that, the display data output process ends.

On the other hand, if it is determined in S64 that the number of processes is not "0", the process proceeds to S65, in order to output the remaining 1-byte data, the offset value is added to the address of the buffer in which the display control data is stored. By adding, the address at which the remaining 1-byte display control data is stored is set.

After S65, the process returns to S54, and the above-described processing is carried forward to output the second byte (the remaining 1 byte) of the display control data. As described above, in the display data output process, the display control data for displaying the image is transmitted to the VDP 103 according to the received display control command. When the display control data is transmitted, if the feedback signal ACK is not returned from the VDP 103, it is determined that the reset is necessary.

Next, the display control microcomputer 80
0 VDP reset processing (S1 of FIG. 10
4) will be described. FIG. 14 is a flowchart showing the VDP reset processing executed by the display control microcomputer 800.

First, in S71, it is determined whether or not the above-mentioned reset timer is "0". S71
If it is determined that the reset timer is "0", the process proceeds to S73, which will be described later. On the other hand, if it is determined in S71 that the reset timer is not "0", the value of the reset timer is subtracted by "1" in S72 and the process proceeds to S73.

In the case of proceeding to S73, it is determined whether or not the above-mentioned reset flag is in the ON state. S
If it is determined by 73 that the reset flag is not in the ON state, this VDP reset processing ends. On the other hand, if it is determined in S73 that the reset flag is in the ON state, the process of outputting the reset signal to the VDP 103 is performed in S74, and the output is stopped in S75 after the elapse of a predetermined period.

Next, in S76, the above-mentioned reset flag is cleared in response to the output of the reset signal. Then, the above-mentioned reset timer is set to a predetermined value (100 in this example), and the process of starting the counting of the reset timer is performed. Then, this VDP reset process is completed.

As described above, in the VDP reset processing, VDP1 is set in response to the reset timer being turned on and the reset flag being turned on.
A process for resetting 03 is performed.

Next, the display control microcomputer 80
Sound CPU reset process executed by 0 (S in FIG.
15) will be described. FIG. 15 is a flowchart showing the sound CPU reset process executed by the display control microcomputer 800.

First, in S81, it is determined whether or not the above-mentioned communication error flag is in the ON state. S
If it is determined by 81 that the communication error flag is not in the ON state, the sound CPU reset process ends. On the other hand, if it is determined in S81 that the communication error flag is in the ON state, a process of outputting a reset signal to the sound control microcomputer 700 is performed in S82, and the output is output in S83 after a predetermined period has elapsed. Be stopped. Next, in S84, processing for clearing the above-mentioned communication error flag is performed in response to the output of the reset signal. Then this sound CP
The U reset process ends.

Next, the sound control microcomputer 700
The control executed by the CPU will be described. First, the main processing of sound control will be described. FIG. 16 is a flowchart showing a voice main process executed by the sound control microcomputer 700.

Referring to FIG. 16, in the sound main process, the same processes as S1 to S6 of the display main process shown in FIG. 10 are performed in S91 to S96. next,
In step S97, it is determined whether the value of the reset timer for resetting the voice IC has reached 0. Where voice IC
The reset timer for reset is a timer that is set in a voice IC reset process described later.
C, that is, when the speech synthesis circuit 702 described above is reset, the execution of the sound control (S98 to S100) processing is stopped until the speech synthesis circuit becomes stable and operable after reset (waiting state). Is a timer for counting a predetermined time (countdown).

If it is determined in S97 that the value of the reset timer has not become 0, the execution of the sound control is stopped, and the process proceeds to S101 described later. On the other hand, if it is determined in S97 that the value of the reset timer has become 0,
In step S98, command recognition processing is executed. In this command recognition process, the received sound control command is stored in the RAM.
Is input (stored) in the buffer as the work area of (1), the content of the command is recognized, and the above-mentioned feedback signal ACK is returned. Detailed contents of the command recognition processing will be described later with reference to FIG.

Next, in S99, voice process processing is performed. In this voice process process, a process for outputting a voice according to a game state is performed by sequentially executing a plurality of voice control processes. next,
Proceeding to S100, the voice data output process for outputting the voice control data for outputting the voice to the voice synthesizing circuit 702 according to the voice process process in S99 is performed. For details of the audio data output process,
It will be described later with reference to FIG. It progresses to S101 after S100.

When the process proceeds to S101, the voice synthesis circuit 7
If the feedback signal SIAK responsive to the voice control data transmitted to the No. 02 is not returned, the voice synthesis circuit 70
A voice IC reset process for resetting 2 is performed. The details of the voice IC reset process will be described later with reference to FIG.

Next, the sound control microcomputer 700
The timer interrupt processing executed by will be described. The sound control microcomputer 700 executes a timer interrupt process having the same contents as the timer interrupt process shown in FIG.

Next, the sound control microcomputer 700
Command recognition processing executed by (S98 in FIG. 16)
Will be explained. FIG. 17 shows a sound control microcomputer 7
10 is a flowchart showing a command recognition process executed by the command 00.

First, in S111, it is determined whether or not a sound control command has been received. If it is determined in S111 that the sound control command has not been received, this command recognition process ends. On the other hand, if it is determined in S111 that the sound control command has been received, S11
In step 2, the received sound control command is input (stored) in a buffer serving as a work area of the RAM, and the content of the command is recognized. Then, in S113, the above-mentioned feedback signal AC
K is output, and after a predetermined period has elapsed, the output is stopped in S114. After that, this command recognition processing ends.

Next, the sound control microcomputer 700
Audio data output processing executed by
0) will be described. FIG. 18 is a flowchart showing a voice data output process executed by the sound control microcomputer 700.

First, in S121, it is determined whether or not the output flag indicating the output state of the voice control data is ON. The output flag in this case is a flag that is turned on when the sound control command is received, and when the sound control command is received, it is necessary to transmit the sound control data based on the sound control command. It is turned on in the command recognition process.

Next, in S122, a process of clearing the output flag indicating the output state of the voice control data is performed. Then, in S123, the process of setting the number of processes to "2" is performed. Here, the number of processes means that one piece of voice control data composed of 2 bytes is divided into 1 byte and 2 bytes.
It is data indicating the number of bytes to be transmitted (the number of transmissions) in order to transmit the data dividedly. In this S123, numerical data indicating 2 bytes corresponding to 1 data is set as the processing number.

Next, in S124, of the addresses of the buffer in which the voice control data for displaying according to the progress of the above-mentioned voice process processing is stored, the data of the address for outputting the data is loaded (read). Processing is done. Then, in S125, the process of setting the data read in S124 in a state in which it can be output is performed. Next, in S126, a process of outputting the data set in S125 is performed. As a result, 1-byte data of the voice control data to be output according to the received sound control command is output as the voice control data.

Next, in S127, processing for setting the SIAK wait counter is performed. Here, the SIAK waiting counter is a counter for defining the time to wait for the reply of the feedback signal SIAK after transmitting the voice control data, and is set to a predetermined number and then down counted. The SIAK wait counter defines a predetermined time to wait for the feedback signal SIAK to be returned.

Next, in S128, a process of subtracting (counting down) the value of the SIAK wait counter set in S127 is performed (for example, 1 is subtracted). Next, in S129, it is determined whether or not the value of the SIAK waiting counter set in S128 becomes "0". When it is determined in S129 that the value becomes "0", the feedback signal S
This is a case where an abnormal state occurs in which no IAK is returned, and it is considered that a communication error has occurred between the sound control microcomputer 700 and the voice synthesis circuit 702, and S136
Then, the process for setting the reset flag to the ON state is performed, and the audio data output process ends. Here, the reset flag is a flag indicating whether or not to reset the voice synthesizing circuit 702, and when a communication error occurs, it is necessary to reset the voice synthesizing circuit 702, so that it is turned on. It The communication error in this case is caused by a state in which the voice synthesizing circuit cannot be controlled, a runaway, and an abnormality in the communication path. If the reset flag is turned on, the voice synthesis circuit 702 will be described later.
Is reset.

On the other hand, if it is determined in S129 that the value of the SIAK waiting counter set in S128 is not "0", the process proceeds to S130, in which the feedback signal from the port 4, that is, the voice synthesis circuit 702 is sent. Processing for checking the reception status of the port that receives SIAK is performed. Then, the process proceeds to S131 and S13.
As a result of checking 0, it is determined whether or not the feedback signal SIAK is received. If it is determined in S131 that the feedback signal SIAK has not been received, the process returns to S128 and the above-described processing is carried forward. On the other hand, the feedback signal SIAK
If it is determined that the message has been received, the process proceeds to S132,
Processing for stopping the output of the output data is performed.

Next, in S133, a process of subtracting "1" from the number of processes described above is performed. As a result, when there is a reception response for the output 1 byte of the voice control data, it is determined that the data transmission is normally performed, and the number of processes is reduced.

Then, in S134, it is determined whether or not the current number of processes is "0". When it is determined in S134 that the number of processes is “0”, it is considered that the 2-byte command is normally transmitted, the above-described transfer end signal (SRDY) is output in S136, and after a lapse of a predetermined period, in S137. Output is stopped. afterwards,
This audio data output process ends.

On the other hand, if it is determined in S134 that the number of processes is not “0”, the process proceeds to S135, in order to output the remaining 1-byte data, the offset value is added to the address of the buffer in which the voice control data is stored. By adding, the address in which the remaining 1-byte voice control data is stored is set.

After S135, the process returns to S124, and the above-mentioned processing is carried forward to output the second byte (the remaining 1 byte) of the voice control data. As described above, in the voice data output process, voice control data for outputting voice according to the received sound control command is transmitted to the voice synthesis circuit 702. Then, at the time of transmitting the voice control data, if the feedback signal SIAK is not returned from the voice synthesizing circuit 702, it is determined that the reset is necessary.

Next, the sound control microcomputer 700
Voice IC reset process (S1 of FIG. 16)
01) will be described. FIG. 19 is a flowchart showing a voice IC reset process executed by the sound control microcomputer 700.

First, in S141, it is determined whether or not the above-mentioned reset timer is "0". S1
When it is determined by 41 that the reset timer is "0", the process proceeds to S143 described later. On the other hand, S14
When it is determined that the reset timer is not "0" by 1, the value of the reset timer is subtracted by "1" in S142, and the process proceeds to S143.

If the process proceeds to S143, it is determined whether or not the above-mentioned reset flag is in the ON state.
If it is determined in S143 that the reset flag is not in the ON state, the voice IC reset process ends. On the other hand, if it is determined in S143 that the reset flag is in the ON state, then in S144,
A process of outputting the reset signal to the voice synthesizing circuit 702 is performed, and after a lapse of a predetermined period, the output is stopped by S145.

Next, in S146, the reset flag is cleared in response to the output of the reset signal. Then, the above-mentioned reset timer is set to a predetermined value (100 in this example), and the process of starting the counting of the reset timer is performed. afterwards,
This voice IC reset process ends.

As described above, in the voice IC reset process, the reset timer is timed and the process for resetting the voice synthesis circuit 702 is performed in response to the reset flag being turned ON.

Next, main effects obtained by the above-described embodiment will be described. As shown in FIGS. 14 and 19, etc., a production control microcomputer such as the display control microcomputer 800 and the sound control microcomputer 700 sends a control signal to the electric control components such as the VDP 103 and the voice synthesis circuit 702. When the reception completion signal is not received from the electrical control component within a predetermined period after output, a reset signal is sent to the electrical control component. Can be recovered from. Furthermore, since such a performance control microcomputer monitors the state of the electric control components, it is not necessary to separately provide a circuit for monitoring, so that it is possible to prevent an increase in the manufacturing cost of the pachinko gaming machine 1 and display control. It is possible to prevent an increase in the component mounting area on the control boards such as the board 800 and the sound control board 700.

Further, as shown in S7 of FIG. 10, S77 of FIG. 14, S97 of FIG. 16, and S147 of FIG. 14, by the production control microcomputer such as the display control microcomputer 800 and the sound control microcomputer 700, After the reset signal is output, since the execution of the control that directs the game using the variable display device 8 including the special symbol display portion 9 and the electric components such as the speaker 27 is restricted for a predetermined period, it is reset. It is possible to prevent the control for producing a game using the electric parts from being performed while the electric control parts after the operation are still in an unstable operation state.

As described with reference to FIGS. 7 and 8,
Since the game control microcomputer 53 and the production control microcomputer as described above are set to the system reset state at the time of starting the supply of the power supply of the pachinko gaming machine 1, the game control microcomputer and the production at the start of the power supply of the gaming machine. The control microcomputer can be surely placed in the system reset state. Furthermore, if the voltage level at which these microcomputers are operable exceeds the voltage level, the reset signal becomes high level (which means that the reset release signal is output), and the system reset state is released.
Even if an abnormality occurs in the reset state of the electric control parts as described above, respond to the control signals such as the display control data and the sound control data which are first output from the production control microcomputer which becomes operable. By confirming the return of the feedback signal (reception completion signal) from the electrical control component, the electrical control component can be put into the system reset state again at the start of the operation.

As shown in the timing chart of FIG. 9, the display control microcomputer 800, the lamp control microcomputer 350, the sound control microcomputer 700, and the payout control microcomputer 3
Since the start-up order of the microcomputers is regulated so that 70 can be operated earlier than the game control microcomputer 53, at the start of supply of power source power to the pachinko gaming machine 1, from the game control microcomputer It is possible to ensure that each control microcomputer on the hand side can receive the command of.

As described with reference to FIGS. 7 to 9, the display control microcomputer 800, the lamp control microcomputer 350, the sound control microcomputer 70.
0, the payout control microcomputer 370, and the game control microcomputer 53 is reset to a high level at the timing of releasing the system reset state (which means that a reset release signal is output) to start the control microcomputer. Is regulated, it is possible to more accurately regulate the time when these control microcomputers can operate.

Further, the delay circuits 942a to 946a for determining the timing for releasing the reset state of each control microcomputer system (timing for outputting the reset release signal) are made different in capacitance of the control microcomputers. Since the starting order is restricted, the starting order of the control microcomputer can be easily restricted using a simple configuration.

Further, since the power supply board 910 is provided with the reset management circuit 940 including the delay circuits 942a to 946a as the activation order regulating means, the display control microcomputer 800 and the lamp control microcomputer 35.
0, the sound control microcomputer 700, the payout control microcomputer 370, and the game control microcomputer 53 can prevent an increase in the component mounting area on each control board, and when a plurality of such control boards are provided. Since it is possible to reduce the number of manufacturing steps and the number of parts by disposing the start-up order regulating means collectively on the power supply board, the manufacturing cost can be reduced.

Further, the display control microcomputer 80
0 outputs a command to another effect control microcomputer (which can also be expressed as a sub effect control microcomputer) such as the lamp control microcomputer 350 and the sound control microcomputer 700, and then the effect control microcomputer within a predetermined period. Since the reset signal is transmitted to the lamp control microcomputer 350 and the sound control microcomputer 700 when no feedback signal is received from the control microcomputer, it is possible to recover from the uncontrollable state and runaway of the control microcomputer. it can.

Second Embodiment Next, a second embodiment will be described. In the second embodiment, the power supply board 91 in FIG. 8 of the first embodiment is used.
An example will be described in which the delay circuits 942a to 946a provided in the 0 reset management circuit 940 are provided in the control board to which the reset signal is transmitted.

FIG. 20 is a block diagram showing an installation example of the reset signal delay circuit according to the second embodiment. The difference between the configuration of FIG. 20 and the configuration of FIG. 8 will be mainly described.

Referring to FIG. 20, in the case of the second embodiment,
In the reset management circuit 940 of the power board 910,
The delay circuits 942a to 946a are not provided, and the reset signal output from the reset signal circuit 941 is directly output to each control board via the buffer circuits 942b to 946b.

In the payout control board 37, the delay circuit 9
42a is provided, and the input reset signal is supplied via the delay circuit 942a to the payout control microcomputer 3
Given to 70. The display control board 80 is provided with a delay circuit 943a, and the input reset signal is applied to the display control microcomputer 800 via the delay circuit 943a. The lamp control board 35 is provided with a delay circuit 944a, and the input reset signal is applied to the lamp control microcomputer 700 via the delay circuit 944a. The sound control board 70 is provided with a delay circuit 945a, and the input reset signal is given to the sound control microcomputer 700 via the delay circuit 945a. Game control board 8
In 1, the delay circuit 946a is provided, and the input reset signal is given to the game control microcomputer 53 via the delay circuit 946a.

As described above, the reset signal delay circuit is provided not on the power supply substrate but on each control substrate. The reset signal delay circuit provided on each control board functions similarly to the case provided on the power supply board as described above.
As described above, the second embodiment shows an example in which the system reset means is provided on each control board.

According to the second embodiment described above, the following effects can be obtained in addition to the effects obtained by the first embodiment described above. The delay circuits 942a to 946a as the activation order regulation means are provided with the display control board 80,
Since the lamp control board 35, the voice control board 70, the payout control board 37, and the game control board 81 are provided respectively, the distance between the activation order regulation means and the microcomputer of which the activation order is regulated is shortened. Therefore, it is possible to prevent noise from entering the path between the boot order restricting means and the microcomputer whose boot order is to be restricted, and restricting the boot order is less susceptible to noise. You can

Third Embodiment Next, another example of the connection form of the game control board 81, the lamp control board 35, the sound control board 70, and the display control board 80 according to the third to tenth embodiments. explain.

FIG. 21 is a block diagram showing a connection form of the control board according to the third embodiment. A production control command, which is a command for instructing all of display control, lamp control, and sound control, is transmitted from the game control board 81 to the production control board 810. The effect control board 810 has an effect microcomputer that performs comprehensive control for transmitting a control command to each control board based on the received effect control command, transmits the display control command to the display control board 80, and outputs the lamp. The lamp control command is transmitted to the control board 35, and the lamp control command is transmitted to the sound control board 70.
Such an effect control board 810 determines, by lottery, whether or not to give an advance notice such as a reach advance notice and a big hit advance notice, and when the advance notice is given, a notice display is displayed on the display control board 80. And a lamp display command for advance light emission to the lamp substrate 35. When the display control board 80, the lamp control board 35, and the sound control board 70 each receive a control command, the display control board 80, the lamp control board 35, and the sound control board 70 perform the processing for returning the feedback signal as described in the first embodiment, and output the feedback signal. It transmits to the production control board 810. Thereby, the production control board 810 confirms that the control command is normally transmitted.

A feedback signal may be transmitted from the effect control board 810 to the game control board 81 in response to the reception of the effect control command.

Fourth Embodiment FIG. 22 is a block diagram showing a connection form of control boards according to the fourth embodiment. A display control command is transmitted from the game control board 81 to the display control board 80. The display control board 80 transmits a lamp control command to the lamp control board 35 based on the received display control command. The lamp control board 35 transmits a sound control command to the sound control board 70 based on the received lamp control command. Then, when the sound control board 70 receives the sound control command, the sound control board 70 transmits a feedback signal to the display control board 80. As a result, the display control board 80 confirms that the control command is normally transmitted.

Fifth Embodiment FIG. 23 is a block diagram showing a connection form of control boards according to the fifth embodiment. A display control command is transmitted from the game control board 81 to the display control board 80. The display control board 80 transmits the lamp / sound control command to the lamp / sound control board 35a based on the received display control command. Here, the lamp / sound control board 35a has a lamp control circuit and a sound control circuit provided on one board, and is controlled by one microcomputer. The lamp / sound control command is a control command commonly used for the lamp control and the sound control. Note that two microcomputers may be provided so that the lamp control circuit and the sound control circuit are individually provided. Lamp / sound control board 3
In 5a, when a lamp / sound control command is received,
The feedback signal is transmitted to the display control board 80. As a result, the display control board 80 confirms that the control command is normally transmitted.

Sixth Embodiment FIG. 24 is a block diagram showing a connection form of control boards according to the sixth embodiment. Display / lamp control commands are transmitted from the game control board 81 to the display / lamp control board 80a. Here, the display / lamp control board 80a has a display control circuit and a lamp control circuit provided on one board, and is controlled by one microcomputer. The display / lamp control command is a control command commonly used for display control and lamp control. Two microcomputers may be provided so that the display control circuit and the lamp control circuit are individually provided. The display / lamp control board 80a transmits a sound control command to the sound control board 70 based on the received display / lamp control command. When the sound control board 70 receives the sound control command, it sends a feedback signal to the display / lamp control board 80a. Thereby, the display / lamp control board 80a confirms that the control command is normally transmitted.

Seventh Embodiment FIG. 25 is a block diagram showing a connection form of control boards according to the seventh embodiment. Display / sound control commands are transmitted from the game control board 81 to the display / sound control board 80b. Here, the display / sound control board 80b has a display control circuit and a lamp control circuit provided on one board.
Controlled by two microcomputers. The display / sound control command is a control command commonly used for display control and sound control. The microcomputer is
Two display control circuits and sound control circuits may be provided separately. The display / sound control board 80b uses the lamp control board 3 based on the received display / sound control command.
5 to send a lamp control command. Lamp control board 3
In No. 5, when the lamp control command is received, the feedback signal is transmitted to the display / sound control board 80b. As a result, the display / sound control board 80b confirms that the control command is normally transmitted.

Eighth Embodiment FIG. 26 is a block diagram showing a connection form of control boards according to the eighth embodiment. A display control command is transmitted from the game control board 81 to the display control board 80. Display control board 8
At 0, the board-side lamp control command is transmitted to the board-side lamp control board 35b and the frame-side lamp control command is sent to the frame-side lamp control board 35c based on the received display control command. Here, the board side lamp control board 3
5b is a board having a microcomputer for controlling various lamps provided on the game board 6 side, and a frame side lamp control board 35c is a microcomputer for controlling various lamps provided on the frame side of the glass door frame 2 and the like. A board having a computer. The board-side lamp control command is a control command used for board-side lamp control, and the frame-side lamp control command is a control command used for frame-side lamp control. The board-side lamp control board 35b transmits a feedback signal to the display control board 80 when the board-side lamp control command is received. The frame side lamp control board transmits a feedback signal to the display control board 80 when the frame side lamp control command is received. With these feedback signals, the display control board 80 confirms that the control command is normally transmitted.

Ninth Embodiment FIG. 27 is a block diagram showing a connection form of control boards according to the ninth embodiment. A display control command is transmitted from the game control board 81 to the display control board 80. The display control board 80 transmits a board-side lamp control command to the board-side lamp control board 35b, a frame-side lamp control command to the frame-side lamp control board 35c, and a sound control board based on the received display control command. The sound control command is transmitted to 80. The board side lamp control board 35b transmits a feedback signal to the display control board 80 when a board side lamp control command is received, and the frame side lamp control board 35c displays a feedback signal when a frame side lamp control command is received. The sound control board 70 transmits the feedback signal to the display control board 80 when the sound control command is received. With these feedback signals, the display control board 80 confirms that the control command is normally transmitted.

Tenth Embodiment FIG. 28 is a block diagram showing a connection form of control boards according to the tenth embodiment. A display / board side lamp control command is transmitted from the game control board 81 to the display / board side lamp control board 80c. Here, display / board side lamp control board 8
0c has a display control circuit and a board side lamp control circuit provided on one board and is controlled by one microcomputer. The display / board side lamp control command is a control command commonly used for display control and board side lamp control. It should be noted that two microcomputers may be provided so that the display control circuit and the panel side lamp control circuit are individually provided.

The display / board side lamp control board 80c transmits a sound / frame side lamp control command to the sound / frame side lamp control board 70a based on the received display / board side lamp control command. Here, the sound / frame side lamp control board 70a
The sound control circuit and the frame side lamp control circuit are provided on one board, and are controlled by one microcomputer. The sound / frame side lamp control command is a control command commonly used for the sound control and the frame side lamp control. Two microcomputers may be provided so that the sound control circuit and the frame side lamp control circuit are individually provided.

Sound / frame side lamp control board 70a
When the frame side lamp control command is received, a feedback signal is transmitted to the display / board side lamp control board 80c. As a result, the display / board side lamp control board 80c is
Confirm that the control command was sent normally.

Eleventh Embodiment Next, the eleventh embodiment will be described. In the eleventh embodiment, an example in which the display control microcomputer 800 controls a movable member for games will be described.

FIG. 29 is a front view showing a game board surface of a pachinko gaming machine according to the eleventh embodiment. 29, the same parts as those in FIG. 1 described above are designated by the same reference numerals, and repeated description will not be repeated. Here, FIG.
Regarding the pachinko gaming machine, the differences from the pachinko gaming machine of FIG. 1 will be mainly described. The structure of the front side of the pachinko gaming machine according to the eleventh embodiment differs from the structure of the pachinko gaming machine according to the first embodiment described above in that the movable members 10 and 18 are provided.
Is provided.

On the upper part of the special variable display portion 9 of the variable winning ball device 8, there is provided a center movable member 10 as movable effect means (movable effect device) imitating the shape of a monster. The center movable member 10 is driven by a solenoid 21 and operation-controlled to perform a predetermined effect operation in a game. The center movable member 10 is provided with two accessory decoration lamps 40, 40 at predetermined locations (in the monster's mouth) as luminous objects for decoration. Also,
At the left and right ends of the game area 7, side movable members 18, 1 as movable effect means (movable effect device) imitating the shape of a person.
8 are provided one by one. This side movable member 1
8 and 18 are solenoids 7 arranged near them.
It is driven by a corresponding one of 2, 2 and is operated and controlled in an interlocking manner in order to perform a predetermined effect operation in the game.

As described above, the movable member as described above is provided at a position where its operation can be visually recognized by the player. It should be noted that the movable member may be configured so as to be hidden at a predetermined position when not in operation and to appear in a position visible to the player when operated. Further, the above-mentioned two types of movable members are shown as an example imitating the shapes of a monster and a person, but the movable member may imitate other than a monster and a person. In addition, the movable member used for the display effect of the update display of the special variable display unit 9 as described above, if a predetermined character is displayed in the update display, if such a character is imitated, the effect is produced. Thus, the display effect of the special variable display section 9 and the operation effect of the movable member can be expressed as one.

The center movable member 10 and the side movable member 18 are basically provided at positions where the screen of the display such as the special variable display section 9 is not blocked by the operation and the flow path of the hitting ball is not changed. There is. However, the installation positions of the center movable member 10 and the side movable member 18 are not limited to this.

FIG. 30 is a block diagram showing an example of the configuration of a control circuit including various control boards in the pachinko gaming machine according to the eleventh embodiment. In this FIG. 30, the same parts as those in FIG. 3 described above are designated by the same reference numerals,
Do not repeat duplicate explanations. Here, the difference between the block diagram of FIG. 30 and the block diagram of FIG. 3 will be mainly described.

The configuration of the block diagram of FIG. 30 is different from that of FIG. 3 in that the display control microcomputer 800 provided on the display control board 80 includes a solenoid 71 for driving the center movable member 10 and a side movable member 18, 18
A drive pulse signal is applied to the drive solenoids 72, 72 to move the center movable member 10 and the side movable members 18, 1
8 is drive-controlled.

In this case, the display control microcomputer 800, based on the received display control command, causes the solenoids 71, 72, 72 to drive pulses so that each movable member operates in accordance with the control state designated by the command. Give a signal.

In this embodiment, an example in which the display control microcomputer 800 controls the operation of each movable member based on the received display control command in accordance with the control state designated by the command has been described. Not limited to this, each movable member is received by the control microcomputer other than the game control microcomputer 53 such as the sound control microcomputer 700 and the lamp control microcomputer 350 in addition to the display control microcomputer 800. The operation may be controlled based on the command.

According to such an eleventh embodiment, the following effects can be obtained in addition to the effects obtained by the above-described embodiments. Since the center movable member 10 and the side movable members 18, 18 which are electric parts are controlled by the display control microcomputer 800 which is a production control microcomputer, the game control microcomputer 53 needs to directly control these movable members. Therefore, the control load on the game control microcomputer 53 can be reduced.

Next, modifications and characteristic points of the above-described embodiment will be listed below. (1) In the above-described embodiment, as an example of the special game state, a case where various game states are added to the probability variation state is shown as an example, but the present invention is not limited to this, and the special game state is as follows. They may be used alone or in combination. Probability fluctuation state, normal game permutation to improve the probability of occurrence of hits of regular symbols, which shortens the variation time from the start of variation of the symbols until the display result is derived and displayed. A gaming state in which improvement control is performed, a gaming state in which variation time reduction control is performed to shorten the variation time from the start of variation of the special symbol until the display result is derived and displayed, start winning opening 14
The game state in which the opening number increase control is performed to increase the opening number of the pair of left and right movable pieces (electric tulip) provided in, and the game state in which the opening time extension control is performed to extend the opening time of the movable piece.

(2) In the above-described embodiment,
Based on a control signal transmitted from the production control microcomputer, V is used as an electric control component for controlling the electric component.
Although the DP and the voice synthesizing circuit are shown as an example, other electric control parts such as an IC (integrated circuit) that controls a light emitting body such as a lamp are also included in such electric control parts.

(3) In the above embodiment,
As the electric parts controlled by the electric control parts, the variable display device 8 including the special symbol display portion 9 and the speaker 72 are shown as an example, but as such electric parts, other games such as a light emitter such as a lamp are used. Other electric parts used for the production of are also included.

(4) As described above, the delay circuits 942a to 946a for delaying the output of the reset signal having the function of resetting and resetting the system include, in addition to the circuit for delaying the signal using the capacitor, the reset signal. A switching circuit that outputs the received reset signal when receiving the output permission signal is provided in the output path of each reset signal, and the output permission signal is switched by the predetermined switching control circuit. It may be given to the circuit. When such a configuration is adopted, the reset signal (low level reset signal) is output after the output of the power-off signal is stopped when the power is turned on, and the reset release signal is output as described above. The (high-level reset signal) is displayed first on the display control board 80, the lamp control board 35,
After being output to the voice control board 70 and the payout control board 37, the output sequence may be controlled by the switching control circuit so as to be output to the game control board 81.

(5) In the above-described embodiments, the same signal (reset signal ON / OFF (low level and high level) for resetting the operating state of the electric control component (system reset) and releasing the reset is used. However, the present invention is not limited to this, and a reset signal for resetting the operating state of the electrical control parts (system reset) and a reset release signal for releasing the reset are also provided. As in the case of use, another signal may be used.

(6) The embodiments disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[Brief description of drawings]

FIG. 1 is a front view of a pachinko gaming machine as viewed from the front.

FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine.

FIG. 3 is a block diagram showing an example of a configuration of a control circuit including various control boards in a pachinko gaming machine.

FIG. 4 is a block diagram showing a circuit configuration in a display control board together with a partial circuit configuration of a variable display device and a game control board.

FIG. 5 is a block diagram showing a configuration example of a signal transmission portion of a sound control command in the display control board and the sound control board.

FIG. 6 is a block diagram showing a configuration example of a signal transmission portion of a lamp control command in the display control board and a lamp control board.

FIG. 7 is a block diagram showing a configuration example of a power supply board.

FIG. 8 is a block diagram showing a configuration of a reset management circuit.

FIG. 9 is a timing chart showing start-up timing of a microcomputer in each control board.

FIG. 10 is a flowchart showing a display main process executed by a display control microcomputer.

FIG. 11 is a flowchart showing a timer interrupt process executed by the display control microcomputer.

FIG. 12 is a flowchart showing a sound control command output process executed by the display control microcomputer.

FIG. 13 is a flowchart showing a display data output process executed by the display control microcomputer.

FIG. 14 is a flowchart showing a VDP reset process executed by the display control microcomputer.

FIG. 15 is a flowchart showing a sound CPU reset process executed by a display control microcomputer.

FIG. 16 is a flowchart showing a voice main process executed by a sound control microcomputer.

FIG. 17 is a flowchart showing command recognition processing executed by a sound control microcomputer.

FIG. 18 is a flowchart showing a sound data output process executed by a sound control microcomputer.

FIG. 19 is a flowchart showing a voice IC reset process executed by a sound control microcomputer.

FIG. 20 is a block diagram showing an example of installation of a reset signal delay circuit according to the second embodiment.

FIG. 21 is a block diagram showing a connection form of a control board according to a third embodiment.

FIG. 22 is a block diagram showing a connection form of a control board according to the fourth embodiment.

FIG. 23 is a block diagram showing a connection form of a control board according to a fifth embodiment.

FIG. 24 is a block diagram showing a connection form of control boards according to a sixth embodiment.

FIG. 25 is a block diagram showing a connection form of a control board according to a seventh embodiment.

FIG. 26 is a block diagram showing a connection form of a control board according to an eighth embodiment.

FIG. 27 is a block diagram showing a connection form of a control board according to a ninth embodiment.

FIG. 28 is a block diagram showing a connection form of control boards according to a tenth embodiment.

FIG. 29 is a front view showing a game board surface of the pachinko gaming machine according to the eleventh embodiment.

FIG. 30 is a block diagram showing an example of a configuration of a control circuit including various control boards in the pachinko gaming machine according to the eleventh embodiment.

[Explanation of symbols]

1 Pachinko gaming machine, 9 special symbol display unit, 8 variable display device, 72 speaker, 80 display control board, 70
Voice control board, 800 display control microcomputer, 700 sound control microcomputer, 103 V
DP, 702 voice synthesis circuit, 940 reset management circuit, 942a to 946a delay circuit, 942b to 946
b buffer circuit, 10 center movable member, 18 side movable member.

Claims (10)

[Claims] 1. A gaming machine having a predetermined electric component, capable of producing a game by controlling the operation of the electric component, wherein a game control microcomputer for controlling a game state is mounted. A game control board, an electric part control board on which an effect control microcomputer for performing control for effecting a game using the electric parts based on a command transmitted from the game control board, and an electric part An electric control component that is provided on a control board and controls the electric component based on a control signal transmitted from the effect control microcomputer, the electric control component receiving the control signal from the effect control microcomputer. In response to this, a reception completion signal indicating that the reception is completed is returned to the effect control microcomputer, The control microcomputer outputs the control signal to the electric control component, and then outputs a reset signal for resetting the operation state of the electric control component when the reception completion signal is not received within a predetermined period. A game machine characterized by transmitting to an electric control component. 2. The effect control microcomputer,
The gaming machine according to claim 1, wherein after the reset signal is output, execution of control for producing a game using the electric component is restricted for a predetermined period. 3. The game control microcomputer and the effect control microcomputer are provided corresponding to each, and the game control microcomputer and the effect control microcomputer are system reset at the time of starting the supply of electric power to the game machine. A system reset that outputs a reset signal for outputting a reset release signal on condition that the predetermined power supply voltage has reached a voltage level at which the game control microcomputer and the effect control microcomputer can operate. The gaming machine according to claim 1 or 2, further comprising means. 4. In connection with the start of the supply of electric power to the gaming machine, the time when the effect control microcomputer becomes operable is earlier than the time when the game control microcomputer becomes operable. 4. The gaming machine according to claim 3, further comprising a boot order restricting means for restricting the boot order, wherein the boot order restricting means is constituted by the system resetting means. 5. The activation order regulation means regulates the activation order of the microcomputers by regulating the timing of outputting the reset release signal to the game control microcomputer and the effect control microcomputer. The gaming machine according to claim 4, wherein 6. The system reset means includes a capacitor for determining the timing of outputting the reset release signal, and the start order of the microcomputers is regulated by making the capacitance of the capacitor different. The gaming machine according to claim 5. 7. The gaming machine according to claim 4, wherein the starting order regulation means is provided on each of the game control board and the electric component control board. . 8. A voltage which is provided separately from the game control board and the electric component control board, and which is used by each of the game control board and the electric component control board from a power supply supplied to the gaming machine. 7. The gaming machine according to claim 4, further comprising a power supply board for generating electric power of the power supply board, wherein the starting order regulation means is provided on the power supply board. 9. The game according to claim 1, wherein the electric component includes a movable member which is provided at a position where a player can visually recognize a motion and which is used for rendering a game. Machine. 10. A sub-production control microcomputer provided separately from the production control microcomputer, for performing control for producing a game using the electric parts based on a command transmitted from the production control microcomputer. The sub production control microcomputer, in response to receiving the command from the sub production control microcomputer, returns a command reception completion signal indicating that the reception is completed to the sub production control microcomputer, The control microcomputer resets the state of the sub-production control microcomputer when the command reception completion signal is not received within a predetermined period after outputting the command to the sub-production control microcomputer. A signal is sent to the sub production control And transmitting to the black computer, a game machine according to any one of claims 1 to 9.