JP2002045547A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of preventing the disadvantages of players and also improved in convenience for them even if power down occurs. SOLUTION: When it is confirmed that the machine is restored to a jackpot control state or to a state having a start winning record in the process of restoring the game state on the basis of information stored in a backup RAM, the machine issues a command for displaying a restoration waiting screen to a symbol displaying means and stays on standby. Then the machine restores the game state when it receives a standby canceling signal issued on the basis of the intention of the player for starting the game. As a result, the machine does not restore the jackpot state while players are absent to be improved in convenience for them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko game machine or a coin game machine in which a game is played in response to a player's operation. It relates to a gaming machine in which a game is performed.

[0002]

2. Description of the Related Art As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of prize balls are obtained. Are paid out to players.
Furthermore, a variable display unit capable of changing the display state is provided,
There is a configuration in which a predetermined game value is provided to a player when a display result of the variable display unit has a predetermined specific display mode.

[0003] When the display result of the variable display section for displaying a special symbol is a combination of a predetermined specific display mode, it is usually called a "big hit". In addition, the game value is a right to make the state of the variable prize ball device provided in the game area of the gaming machine advantageous for a player who is easy to win a hit ball, or a right for the player to be in an advantageous state. Or to generate.

[0004] When a big hit occurs, for example, a big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state in which a hit ball is easy to win. Then, in each open period, when a predetermined number (for example, 10) of winning prizes is won, the winning prize opening is closed. The number of opening of the special winning opening is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. If the predetermined condition (for example, winning in the V zone provided in the special winning opening) is not satisfied at the time when the special winning opening is closed, the big hit gaming state ends.

[0005] In addition, among the combinations of display modes other than the "big hit" combination, at a stage where some of the display results of the plurality of variable display portions have not been derived and displayed yet, the display results have already been derived and displayed. A state in which the display mode of the variable display unit that satisfies the display condition that is a combination of the specific display modes is referred to as “reach”. If the display result of the identification information variably displayed on the variable display unit does not satisfy the condition of “reach”, the result is “out” and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

When a game ball wins a winning opening provided on the game board, a predetermined number of award balls are paid out. Since the progress of the game is controlled by the game control means mounted on the main board, the number of winning balls based on the winning is determined by the game control means,
Sent to the prize ball control board. Hereinafter, the game control means and the other control means may be respectively referred to as electric component control means.

[0007]

As described above, a gaming machine is equipped with various electric component control means including game control means. Generally, each electric component control means is constituted by a microcomputer. That is, a program is stored in a ROM or the like, and data that temporarily occurs in control or data that changes as the control progresses is stored in the RAM. Then, when a power-off state occurs due to a power failure or the like in the gaming machine, data in the RAM is lost. Therefore,
At the time of recovery from a power failure or the like, the player has to return to the initial state (for example, the state when the game machine is first turned on at the game store for the day), which may be disadvantageous to the player. . For example, if a power failure occurs during a jackpot game and the gaming machine returns to the initial state, the player will not be able to enjoy the benefits based on the occurrence of the jackpot.

In order to avoid such a situation, necessary data is stored in a power supply backup RAM when an unexpected power failure such as a power failure occurs, and data stored when power is restored is restored. And then resume the game. However, such control may give a disadvantage to the player. For example, if a power failure occurs and the game cannot be continued, and the player is standing by at a place away from the gaming machine, and the power is restored and the game is resumed, the player returns. Occasionally, for example, it is conceivable that a disadvantage such as that the big hit state has already ended is incurred.

Accordingly, the present invention provides a method for controlling
It is an object of the present invention to provide a gaming machine that can prevent a disadvantage from being brought to a player and can also improve convenience for the player.

[0010]

A gaming machine according to the present invention comprises:
A gaming machine capable of performing a predetermined game, an electrical component control board equipped with an electrical component control microcomputer for controlling electrical components provided in the gaming machine, and an electrical component control microcomputer controlling the Fluctuation data storage means (for example, RAM) for storing fluctuation data generated at the time of performing, and storage content holding capable of holding the last storage content of the fluctuation data storage means immediately before power-off for at least a predetermined period after power supply is stopped. Control restoration means capable of restoring control of electrical components based on the final storage contents when the last storage contents are held in the variable data storage means when power supply is started; and control restoration. Recovery start suspending means capable of suspending the recovery start of the control by the means. There if entered, is characterized in that which is capable of releasing the hold of the recovery period.

It is preferable that the recovery start suspending means determines whether to suspend the recovery start by referring to the final storage contents. For example, as a result of referring to the final storage contents, if it is considered that it is better to suspend the recovery start (if the recovery is started without the suspension, there is a possibility that the player will be disadvantaged), It may be determined that the start is suspended.

A specific game state advantageous to the player (for example, if the result of the predetermined game is a specific mode) (for example,
It is preferable that the game control unit be provided with a game control unit capable of controlling a large hit state, and the recovery start holding unit hold the start of recovery when the final storage content is at least the content indicating the specific game state.

A start detecting means for detecting start in response to a predetermined winning is provided, and a predetermined game for deciding whether or not to enter a game state advantageous to the player in response to one start detection. Is started, and the start detection number can be held by a predetermined number, and the recovery start holding means should hold the recovery start when the final storage content indicates at least that the start detection number is held. preferable.

A display device (for example, a symbol display section 9) for giving a predetermined notification to the player may be provided, and a predetermined screen display may be displayed on the display device while the recovery start is suspended. In this case, the predetermined screen display includes a display for instructing the player on a method of starting recovery and a display for notifying the final storage contents (accordingly, a control state at the time of recovery is notified). preferable.

Preferably, the recovery start signal is transmitted by a predetermined operation of the player. For example, a touch sensor (for example, a touch switch 5a) for detecting that the player has touched the gaming machine may be provided, and a game restart signal may be transmitted in response to the detection of the touch sensor. Further, a firing operation means (for example, an operation knob 5) operated by a player to fire a game ball, and a firing ball for detecting a game ball fired in response to a predetermined operation of the firing operation means by the player A detector (for example, a launching ball detection switch 7a) may be provided, and a recovery start signal may be transmitted in response to detection of the launching ball detector.

[0016]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. FIG. 1 is a front view of the pachinko gaming machine 1 as viewed from the front. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine. Further, the present invention can be applied to an image-type gaming machine or a slot machine.

As shown in FIG. 1, the pachinko gaming machine 1
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. A surplus ball tray 4 for storing premium balls overflowing from the hit ball supply tray 3 and a hit ball operation handle (operation knob) 5 for firing a hit ball are provided below the hit ball supply tray 3. Note that the hitting operation handle 5
Is provided with a touch switch 5a capable of detecting whether or not the player is touching the hit ball operation handle 5. A game board 6 is detachably mounted behind the glass door frame 2. A game area 7 is provided on the front of the game board 6. In addition, near the entrance of the hit ball in the game area 7, there is provided a shot ball detection switch 7a for detecting whether or not a shot ball has been released into the game area 7 (whether or not a hit ball has been shot). .

In the vicinity of the center of the game area 7, a variable display section 9 for variably displaying a plurality of types of symbols and a 7-segment L
A variable display device 8 including a variable display 10 using an ED is provided. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In the passage between the passage gate 11 and the ball exit 13, there is a gate switch 12 for detecting a hit ball passing through the passage gate 11. In addition, the winning ball that entered the starting winning port 14 is
It is guided to the back of the game board 6 and is detected by the starting port switch 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16.

An opening / closing plate 20 opened by a solenoid 21 in a specific game state (big hit state) is provided below the variable winning ball device 15. In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. A winning ball that has entered one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V winning switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. At the bottom of the variable display device 8, the number of winning balls entering the starting winning opening 14 is displayed.
A start winning storage display 18 having a plurality of display units is provided. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The gaming board 6 is provided with a plurality of winning ports 19 and 24, and the winning of the game balls to the winning ports 19 and 24 is detected by the winning port switches 19a and 24a. At the left and right sides of the game area 7, there are provided decorative lamps 25 which are displayed blinking during the game, and at the lower part there is an out port 26 for absorbing hit balls which have not won. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. A gaming effect LED 2 is provided on the outer periphery of the gaming area 7.
8a and gaming effect lamps 28b and 28c are provided.

In this example, one of the speakers 27
Is provided with a prize ball lamp 51 which is lit when a premium ball is paid out, and a ball out lamp 52 which is lit up when the supply ball is out is provided near the other speaker 27. Further, FIG. 1 also shows a card unit 50 which is installed adjacent to the pachinko gaming table 1 and enables lending of a ball by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card is in a usable state. When there is a fraction (a number less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter, the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passage gate 11, the display number of the variable display 10 is changed continuously. Further, when a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17, the symbol in the variable display section 9 starts rotating if the symbol can be changed. If it is not possible to start changing the symbol, the start winning memory is increased by one.

The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. When the hit ball wins in the specific winning area while the opening and closing plate 20 is being opened and is detected by the V winning switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. The continuation right is generated a predetermined number of times (for example, 15 rounds)
Permissible.

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols with probability fluctuation, the probability of the next big hit increases. That is, a high probability state, which is more advantageous for the player, is obtained. Also, when the stop symbol on the variable display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the variable display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, each board disposed on the back of the pachinko gaming machine 1 will be described. As shown in FIG. 2, on the back surface of the pachinko gaming machine 1, a ball storage tank 38 is provided above the mechanism plate in the frame 2A, and above the pachinko gaming machine 1 installed on the gaming machine installation island. The game ball is supplied to the ball storage tank 38 from. The game balls in the ball storage tank 38 pass through a guiding gutter 39 to reach a ball payout mechanism (not shown).

On the back side of the gaming machine, a variable display control unit 29 for controlling the variable display section 9 and a game control board (main board) 31 on which a game control microcomputer and the like are mounted are installed. A payout control board 37 on which a payout control microcomputer or the like for performing ball payout control is mounted;
And a hit ball launching device that launches a hit ball into the game area 7 using the rotational force of a motor. Furthermore, the decoration lamp 25, the game effect LED 28a, the game effect lamp 28
b, 28c, a lamp control board 35 for sending signals to the prize ball lamp 51 and the ball out lamp 52, a voice control board 70 for controlling the generation of voice from the speaker 27, and a launch control for controlling the hit ball launching device. A substrate 91 is also provided. Note that an error display LED 374 is also mounted on the payout control board 37.

Also, DC30V, DC21V, DC12
A power supply board 910 on which a power supply circuit for generating V and DC5V is mounted is provided, and a terminal board 16 having terminals for outputting various information to the outside of the gaming machine is provided above.
0 is set. The terminal board 160 has at least a ball-cutting terminal for introducing and outputting the output of a ball-out detection switch 167 described later, a prize-ball terminal for externally outputting a prize-ball number signal, and a ball lending number signal. Ball lending terminals for external output.
In the vicinity of the center, an information terminal board (external information output device) 34 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed.

In FIG. 2, signals from the lamp control board 35 and the sound control board 70 are transmitted to the game effect LEDs 28a, game effect lamps 28b, 28 provided on the frame side.
c, an illuminated relay board A77 for supplying the prize ball lamp 51 and the ball out lamp 52, and a balance display board 74 mounted with a frequency display LED and the like are shown. Although not shown, other relay boards are provided as needed for signal relay.

FIG. 3 is a rear view of the mechanical plate of the pachinko gaming machine 1 as viewed from the rear. The game balls stored in the ball storage tank 38 pass through the guide gutter 39 and, as shown in FIG. 3, the ball-out detectors (ball-out switches) 187a and 187.
b passes through the ball supply gutters 186a and 186b to reach the ball dispensing device 97. The game balls paid out from the ball payout device 97 are supplied to the hit ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the communication port 45. On the side of the communication port 45, an excess ball passage 46 communicating with the excess ball tray 4 provided on the front of the pachinko gaming machine 1 is formed. When a large number of prize balls are paid out based on the winning and the hitting ball supply tray 3 becomes full, and finally, after the game balls reach the contact port 45, further game balls are paid out, the game balls surplus through the surplus ball passage 46. It is led to the ball tray 4. When the game ball is further paid out, the sensing lever 47 is set to the full switch 4.
By pressing 8, the full tank switch 48 is turned on. In that state, the rotation of the stepping motor in the ball discharging device 97 stops, the operation of the ball discharging device 97 stops, and the driving of the hit ball firing device 34 also stops.

Signals from a winning port switch (not shown), a starting port switch 17 and a V winning switch 22 are sent to the main board 31 to perform the prize ball payout control. When the starting port switch 17 is turned on, the CPU 56 of the main board 31 knows that a winning corresponding to the payout of six winning balls has occurred.
Further, when the count switch 23 is turned on, it is known that a winning corresponding to the payout of 15 prize balls has occurred. Then, when the winning opening switch is turned on, it is known that a winning corresponding to the payout of 10 prize balls has occurred. In this embodiment, for example, a game ball that has won the winning opening 24 is the winning opening 2
Prize hole switch 2 provided in the prize ball channel from 4
The game ball detected in 4a and winning in the winning opening 19 is detected by a winning opening switch 19a provided in a winning ball flow path from the winning opening 19.

FIG. 4 is a block diagram showing an example of the circuit configuration of the main board 31. FIG. 4 also shows the payout control board 37, the lamp control board 35, the sound control board 70, the emission control board 91, and the symbol control board 80.
The pachinko machine 1 is provided on the main board 31 according to the program.
Circuit 53, the gate switch 12, the starting port switch 17, the V winning switch 22, the count switch 23, the ball out switch 187, and the winning port switch 19.
a, 24a, a prize ball count switch 301A, a launch ball detection switch 7a, and a switch circuit 58 for giving signals from the touch switch 5a to the basic circuit 53; a solenoid 16 for opening and closing the variable winning ball device 15;
And a solenoid circuit 59 that drives the solenoid 21 and the like that opens and closes according to a command from the basic circuit 53.

According to the data supplied from the basic circuit 53, jackpot information indicating occurrence of a jackpot, effective start information indicating the number of start winning balls used to start image display of the variable display section 9, and probability fluctuation have occurred. And an information output circuit 64 that outputs probability change information or the like indicating the fact to a host computer such as a hall management computer.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as an example of a storage means used as a work memory, a CPU 56 for performing a control operation according to the program, and an I / O port unit 5.
7 inclusive. In this embodiment, the ROM 54 and the RAM 5
5 is built in the CPU 56. That is, the CPU 5
Reference numeral 6 denotes a one-chip microcomputer. In addition, 1
The chip microcomputer has at least the RAM 55
And the ROM 54 and the I / O port unit 57 may be external or internal. The I / O port unit 57 is a terminal capable of inputting and outputting information in the microcomputer.

Further, the main board 31 includes a system reset circuit 65 for resetting the basic circuit 53 when the power is turned on, and an I / O port unit 57 which decodes an address signal supplied from the basic circuit 53 and decodes the address signal. I /
An address decode circuit 67 for outputting a signal for selecting the O port is provided. Note that the ball payout device 9
There is also switch information input to the main board 31 from 7,
In FIG. 4, they are omitted.

A hit ball launching device that hits and launches a game ball is driven by a drive motor 94 controlled by a circuit on a launch control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

In this embodiment, the lamp control means mounted on the lamp control board 35 is used to display the start memory display 18, the gate passage memory display 41 and the decoration lamp 25 provided on the game board. Controls the game and the game effect lamp / LED 28 provided on the frame side.
a, 28b, and 28c, display control of the award ball lamp 51, and the ball out lamp 52 are performed. The display control of the variable display section 9 for variably displaying special symbols and the variable display 10 for variably displaying ordinary symbols is performed by display control means mounted on the symbol control board 80.

FIG. 5 shows the circuit configuration in the symbol control board 80 by using an LCD (liquid crystal display) 82 as an example of the variable display section 9, an ordinary symbol display 10, and an output port (port 0) of the main board 31. , 2) are block diagrams shown together with 570, 572 and output buffer circuits 620, 62A. Output port (output port 2) 572 outputs 8-bit data, and output port 570 outputs a 1-bit strobe signal (INT signal).

The display control CPU 101 controls the control data R
It operates according to the program stored in the OM 102, and receives an INT signal from the main board 31 via the noise filter 107 and the input buffer circuit 105B, and receives a display control command via the input buffer circuit 105A. As the input buffer circuits 105A and 105B, for example, 74HC540 and 74HC14, which are general-purpose ICs, can be used. When the display control CPU 101 does not include an I / O port, an I / O port is provided between the input buffer circuits 105A and 105B and the display control CPU 101.

The display control CPU 101 performs display control of the screen displayed on the LCD 82 according to the received display control command. Specifically, a command corresponding to the display control command is given to the VDP 103. VDP103
Reads necessary data from the character ROM 86. The VDP 103 controls the LCD 8 according to the input data.
2 to generate image data to be displayed on the LCD 2, and output R, G, B signals and a synchronization signal to the LCD 82.

FIG. 5 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, an animal, or an image composed of characters, figures, or symbols displayed on the LCD 82.

The input buffer circuits 105A and 105B
Signals can be passed only in the direction from the main board 31 to the symbol control board 80. Therefore, the symbol control board 8
There is no room for a signal to be transmitted from the 0 side to the main board 31 side. That is, the input buffer circuits 105A and 105B together with the input ports constitute irreversible information input means. Even if the circuit in the symbol control board 80 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side.

The outputs of the output ports 570 and 572 may be directly output to the symbol control board 80, but the output buffer circuits 620 and 62A capable of transmitting signals only in one direction.
, The main board 31 to the symbol control board 8
One-way signal transmission to 0 can be more reliably performed. That is, the output buffer circuits 620 and 62A together constitute an irreversible information output unit with the output ports. By the irreversibility information output means, the input of the illegal signal to the symbol control board 80 via the signal transmission line is surely prevented.

For example, a three-terminal capacitor or a ferrite bead is used as the noise filter 107 for cutting off the high-frequency signal. The effect is eliminated. Note that a noise filter may be provided on the output side of the buffer circuits 620 and 62A of the main board 31.

FIG. 6 is a block diagram showing an example of the configuration around the CPU 56. As shown in FIG. 6, a voltage drop signal from a first power supply monitoring circuit (first power supply monitoring means or power supply monitoring means) is connected to a non-maskable interrupt terminal (XNMI terminal) of the CPU 56. The first power supply monitoring circuit is a circuit that monitors a voltage of any one of various DC power supplies used by the gaming machine and detects a power supply voltage drop. In this embodiment, the power supply voltage of VSL is monitored, and when the voltage value becomes equal to or less than a predetermined value, a low-level voltage drop signal is generated. VSL is the largest DC voltage used in gaming machines, and is +30 V in this example. Therefore, the CPU 56 can confirm the occurrence of power interruption by the interrupt processing. In this embodiment, the first power supply monitoring circuit is mounted on a power supply board, which will be described later, and the occurrence of power interruption is confirmed by the interrupt processing.

FIG. 6 also shows a system reset circuit 65, but in this embodiment, the system reset circuit 65 also serves as a second power supply monitoring circuit (second power supply monitoring means). That is, the reset IC 651
When the power is turned on, the output is set to the low level for a predetermined time determined by the capacity of the external capacitor, and the output is set to the high level after the predetermined time has elapsed. That is, the reset signal is raised to a high level to make the CPU 56 operable. The reset IC 651 monitors the power supply voltage of VSL, which is the same power supply voltage as the power supply voltage monitored by the first power supply monitoring circuit, and sets the voltage value to a predetermined value (the first power supply monitoring circuit outputs a voltage drop signal). When the voltage falls below the power supply voltage value), a low-level voltage drop signal is generated. Accordingly, the CPU 56 performs a predetermined power supply stop processing in response to the voltage drop signal from the first power supply monitoring circuit, and then performs a system reset. In this embodiment, the reset signal and the voltage drop signal from the second power supply monitoring circuit are the same signal.

As shown in FIG. 6, the reset signal from the reset IC 651 is input to the NAND circuit 947 and also to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. Counter I
When the input to the clear terminal goes low, the C941 counts the clock signal from the oscillator 943.
The Q5 output of the counter IC 941 is output to the NOT circuit 9
45, 946 and input to the NAND circuit 947. The Q6 output of the counter IC 941 is input to a clock terminal of a flip-flop (FF) 942.
The D input of the flip-flop 942 is fixed at a high level, and the Q output is input to an OR circuit (OR circuit) 949. The other input of the OR circuit 949 is connected to the NAND circuit 9.
The output of 47 is introduced via NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56. According to such a configuration, two reset signals (low-level signals) are supplied to the reset terminal of the CPU 56 when the power is turned on.
Starts operation reliably.

Then, for example, the detection voltage of the first power supply monitoring circuit (the voltage at which the voltage drop signal is output) is increased by +
22 V, and the detection voltage of the second power supply monitoring circuit is +9 V. In such a configuration, since the first power supply monitoring circuit and the second power supply monitoring circuit monitor the voltage of the same power supply VSL, the timing at which the first voltage monitoring circuit outputs the voltage drop signal The difference between the timings at which the second voltage monitoring circuit and the second voltage monitoring circuit output the voltage drop signal can be reliably set to a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop processing in response to the voltage drop signal from the first power supply monitoring circuit until the power supply stop processing is completely completed.

In this example, the first detection condition that the first power supply monitoring means outputs a detection signal is that the +30 V power supply voltage has dropped to +22 V, and the second power supply monitoring means outputs the detection signal. The second detection condition to be output is that the +30 V power supply voltage has dropped to +9 V.
However, the voltage value used here is an example,
Other values may be used.

However, although the monitoring range is narrowed, the monitoring voltage of the first voltage monitoring circuit and the second voltage monitoring circuit is +
It is also possible to use a 5V power supply voltage. Also in that case, the detection voltage of the first voltage monitoring circuit is set higher than the detection voltage of the second voltage monitoring circuit.

While power is not supplied from the +5 V power supply which is the driving power supply of the CPU 56 and the like, at least a part of the RAM is backed up by the backup power supply supplied from the power supply board, and the contents are maintained even if the power supply to the gaming machine is cut off Is saved. Then, when the + 5V power supply is restored, a reset signal is issued from the system reset circuit 65, so that the CPU 56 returns to the normal operation state. At that time, since the necessary data is stored in the backup RAM, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovering from a power failure or the like.

In FIG. 6, when the power is turned on, the CPU 56
A reset signal (low-level signal) is given twice to the reset terminal. However, in the case of using a CPU in which reset is surely released even if the reset signal rises only once, Reference numerals 941 to 9
The circuit element indicated by 49 is unnecessary. In that case, the output of the reset IC 651 is directly connected to the reset terminal.

CPU 56 used in this embodiment
Incorporates an I / O port (PIO) and a timer / counter circuit (CTC). PIO is PB0-PB
It has a port of 3 4 bits and 1 byte of PA0 to PA7. The ports PB0 to PB3 and PA0 to PA7 can be set for both input and output. However, in this embodiment, no built-in PIO is used. In that case, for example, all ports are set to the input mode, and all ports are connected to the ground level. When power is turned on, P
IO is automatically set to input mode.

FIG. 7 is a block diagram showing a configuration example of a power supply board 910 of a gaming machine. The power supply board 910 is installed independently of the electric component control boards such as the main board 31, the symbol control board 80, the voice control board 70, the lamp control board 35, and the payout control board 37, and controls each of the electric component control boards in the game machine. Generates voltages used by mechanical components. In this example, AC24V, VSL (DC + 30V), DC + 21
V, + 12V DC and + 5V DC. Also,
The capacitor 916 serving as a backup power supply is DC + 5
V, that is, charged from a power supply line for driving an IC or the like on each substrate.

The transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
The C converter 913 has + 22V, + 12V and + 5V.
V is generated and output to the connector 915. Connector 91
5 is connected to, for example, a relay board, from which electric power of a voltage required for each electric component control board and mechanism components is supplied. A power switch 920 for stopping or starting power supply to the gaming machine is provided on the input side of the transformer 911.

+5 V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is provided with an electric power so as to be able to hold a storage state in a backup RAM (power-backed-up RAM, that is, storage means that can be in a storage state) when the power supply to the gaming machine is cut off. Backup power supply. Also,
A diode 917 for preventing backflow is inserted between the + 5V line and the backup + 5V line.

Note that a battery that can be charged from a +5 V power supply may be used as a backup power supply. In the case of using a battery, a rechargeable battery is used which runs out of capacity when power is not supplied from a + 5V power supply for a predetermined time.

The power supply board 910 has the first
The power supply monitoring IC 902 constituting the power supply monitoring circuit of FIG. The power supply monitoring IC 902 detects the occurrence of power interruption by introducing the VSL power supply voltage and monitoring the VSL power supply voltage. Specifically, when the VSL power supply voltage becomes equal to or lower than a predetermined value (+22 V in this example), a voltage drop signal is output assuming that power supply is cut off. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after conversion from AC to DC, is used. The voltage drop signal from the power supply monitoring IC 902 is supplied to the main board 31, the payout control board 37, and the like.

The predetermined value for the power supply monitoring IC 902 to detect a power-off is lower than the normal voltage, but is a voltage at which the CPU on each electric component control board can operate for a while. Further, the power supply monitoring IC 902 is configured to monitor a voltage higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and a voltage immediately after conversion from AC to DC. Therefore, the monitoring range can be extended for the voltage required by the CPU. Therefore,
More precise monitoring can be performed. Furthermore, when VSL (+30 V) is used as the monitoring voltage, since the voltage supplied to the various switches of the gaming machine is +12 V, prevention of erroneous switch-on detection upon momentary power interruption can be expected. That is, when monitoring the voltage of the + 30V power supply,
The drop can be detected at a stage before + 12V generated after the generation of 0V starts to fall. Therefore, when the voltage of the + 12V power supply decreases, the switch output comes to the on state. However, if the + 30V power supply voltage that drops faster than + 12V is monitored and the power cutoff is recognized, the power supply is turned on before the switch output turns on. It is possible to enter a state of waiting for restoration and to enter a state where the switch output is not detected.

Since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric component control board, the first power supply monitoring circuit supplies a voltage drop signal to the plurality of electric component control boards. Can be. Regardless of how many electrical component control boards require a voltage drop signal, it is sufficient that only one first power supply monitoring unit is provided. Doing so does not add much to the cost of the gaming machine.

In the configuration shown in FIG. 7, the detection output (voltage drop signal) of the power supply monitoring IC 902 is supplied to the respective electric component control boards (for example, the main board 31 and the payout control) via the buffer circuits 918 and 919. Although transmitted to the board 37), for example, a configuration in which one detection output is transmitted to the relay board, and the same signal is distributed from the relay board to each electric component control board may be employed. Further, a buffer circuit may be provided according to the number of substrates requiring a voltage drop signal.

Next, the operation of the gaming machine will be described. FIG.
9 is a flowchart showing a main process executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main process, the CPU 56 first performs necessary initial settings.

In the initial setting process, the CPU 56 first sets interrupt prohibition (step S1). Next, the interrupt mode is set to the interrupt mode 2 (step S2), and a stack pointer designated address is set to the stack pointer (step S3). Then, the internal device registers are initialized (step S4). After initializing a built-in device (built-in peripheral circuit) CTC (counter / timer) and PIO (parallel input / output port) (step S5), the RAM is set to an accessible state (step S6).

CPU 5 used in this embodiment
6 has the following three types of modes as maskable interrupt (INT) modes. When an interrupt that can be masked occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter on the stack.

Interrupt mode 0: The built-in device which has issued the interrupt request receives the RST instruction (1 byte) or the CALL instruction (3
Byte) on the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. Upon reset, CPU 56 automatically switches to interrupt mode 0
become. Therefore, when it is desired to set the mode to the interrupt mode 1 or the interrupt mode 2, it is necessary to perform a process for setting the mode to the interrupt mode 1 or the interrupt mode 2 in the initial setting process.

Interrupt mode 1: When an interrupt is accepted,
In this mode, the camera always jumps to the address 0038 (h).

Interrupt mode 2: The address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is the interrupt address. Mode. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary (albeit skipped) even address. Each built-in device has a function of sending an interrupt vector when making an interrupt request.

Therefore, when the interrupt mode 2 is set, it is possible to easily process an interrupt request from each built-in device, and it is possible to set an interrupt process at an arbitrary position in a program. Will be possible. Further, unlike the interrupt mode 1, it is easy to prepare an interrupt process for each interrupt occurrence factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

Then, it is confirmed whether or not the data protection processing of the backup RAM area (for example, the power failure occurrence NMI processing such as the addition of parity data) has been performed when the power is turned off (step S7). In this embodiment, when an unexpected power failure occurs, a process for protecting data in the backup RAM area is performed. The case where such protection processing has been performed is regarded as backup. After confirming that there is no backup, the CPU 56 executes an initialization process.

In this embodiment, whether or not there is backup data in the backup RAM area is confirmed by the state of the backup flag set in the backup RAM area when the power is turned off. For example, if “55H” is set in the backup flag area, it means that there is a backup (on state), and if a value other than “55H” is set, it means that there is no backup (off state). "5" set in the backup flag area
5H ”indicates that the backup R
This data is set when the data protection processing of the AM area is completed, and is a parity code based on the data of the backup RAM area.

When the backup data exists in the backup RAM area, the CPU 56
Data check (for example, parity check) of the M area is performed. If the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, and the check result becomes normal. If the check result is not normal, the internal state cannot be returned to the state at the time of power-off, so that the initialization processing is executed.

When the backup is confirmed and the check result is normal, the CPU 56 performs a game state restoring process for returning the internal state to the state at the time of power-off (step S).
8). As shown in FIG. 9, when the value of the backup flag is set to “55H” and the check result is normal, the game state restoring process of step S8 is executed. Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the program returns to that address.

In this embodiment, step S7
The backup area was checked if the backup data existed after the backup data was checked, but the backup area was checked if the backup area check result was normal. Confirmation of presence or absence may be performed. Alternatively, whether to execute the power failure recovery process may be determined by confirming whether there is backup data or checking the backup area.

Further, for example, at the time of a parity check for determining whether or not to execute the power failure recovery processing,
When determining whether or not to restore the gaming state, the gaming machine is placed in a gaming standby state (without changing the symbol, not during the jackpot game) according to the special process flag or the like in the saved RAM data or the number of start winning prizes. If it is confirmed that the game state is not being changed and that there is no start winning prize memory, the initialization processing may be executed without performing the game state restoration processing.

In the initialization process, the CPU 56 first sets R
An AM clear process is performed (step S11). In addition, a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer,
An initial value setting process for setting an initial value to a payout command storage pointer or the like is also performed. Further, a process for initializing the sub-boards (the lamp control board 35, the payout control board 37, the voice control board 70, and the symbol control board 80) is executed (step S13). The process of initializing the sub board is
For example, this is a process of transmitting an initial setting command, and an initial display command (see FIG. 16) described later is transmitted to the symbol control board 80.

Then, the register of the CTC provided in the CPU 56 is set so that the timer is interrupted periodically every 2 ms (step S14). That is,
A value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interrupt is prohibited in step S1 of the initial setting process, the interrupt is permitted before the initialization process is completed (step S1).
5).

In this embodiment, the built-in C
The TC is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. When a timer interrupt occurs, the CPU 56
Sets a timer interrupt flag indicating that a timer interrupt has occurred, for example.

Execution of initialization processing (steps S11 to S1)
When 5) is completed, the process proceeds to a loop process in which the main process checks whether or not a timer interrupt has occurred (step S17). In the loop, a display random number update process (step S16) is also executed.

The CPU 56 determines in step S17
Upon recognizing that a timer interrupt has occurred, step S2
The game control processing of 1 to S31 is executed. In the game control process, the CPU 56 firstly receives, via the switch circuit 58, the gate sensor 12, the starting port sensor 17, the count sensor 23, and the winning port switches 19a, 19b, 24.
The states of the switches such as a and 24b are input and their states are determined (switch processing: step S21).

Next, various abnormality diagnosis processes are performed by the self-diagnosis function provided in the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S22).

Next, a process of updating each counter indicating a random number for determination, such as a random number for big hit determination used in game control, is performed (step S23). The CPU 56 further includes:
A process for updating a display random number such as a random number for determining the type of stop symbol is performed (step S24).

Further, the CPU 56 performs a special symbol process (step S25). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Also, a normal symbol process is performed (step S26). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

Next, the CPU 56 sets a display control command relating to a special symbol in a predetermined area of the RAM 55 and sends out the display control command (special symbol command control process: step S27). Further, a display control command relating to a normal symbol is set in a predetermined area of the RAM 55, and a process of transmitting the display control command is performed (ordinary symbol command control process: step S28).

Further, the CPU 56 performs an information output process of outputting data such as jackpot information, start information, and probability variation information supplied to the hall management computer (step S29).

Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S30). The solenoid circuit 59 drives the solenoids 16 and 21 in response to the drive command, and brings the variable winning ball device 15 or the open / close plate 20 into an open state or a closed state.

The CPU 56 has switches 17, 23, 19a and 24a for detecting a winning in each winning opening.
The award ball processing for setting the number of award balls based on the detection output is performed (step S31). Specifically, a payout control command is output to the payout control board 37 in response to the winning detection. Dispensing control CP mounted on the dispensing control board 37
U371 sets the ball payout device 97 in response to the payout control command.
Drive.

With the above control, in this embodiment, the game control process is started every 2 ms.
In this embodiment, for example, in the timer interrupt processing, only a flag indicating that an interrupt has occurred is set, and the game control processing is executed in the main processing.
The game control process may be executed by a timer interrupt process.

The main process includes a process for determining whether or not to shift to the game control process. The internal timer of the CPU 56 performs a timer interrupt process based on a timer interrupt that is periodically generated. Since a flag for determining whether or not to shift is set or the like, all of the game control processing is reliably executed. In other words, until all of the game control processes have been executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all processes in the game control process will be completed. ing.

As described above, in this embodiment, the interrupt mode 2 is set by the initial setting process for the CPU 56 having a built-in CTC or PIO. Accordingly, a periodic timer interrupt process using the built-in CTC can be easily realized. Further, the timer interrupt processing can be set at an arbitrary position on the program. Further, switch detection processing using the built-in PIO can be easily realized by interruption processing. As a result, effects such as simplification of the program configuration and reduction in the number of program development steps can be obtained.

FIG. 10 is a flowchart showing an example of the power failure occurrence NMI process executed in response to the NMI based on the voltage change signal from the power supply monitoring circuit of the power supply board 910. In the power failure occurrence NMI process, first, the CPU 56 stores the contents of the interrupt prohibition flag in the parity flag in order to back up the interrupt permission / prohibition state immediately before the power failure such as during a power failure (step S41). Next, interrupt prohibition is set (step S42). Power failure occurrence NMI
In the process, a checksum generation process is performed to ensure that the contents of the RAM are preserved. If other interrupt processing is performed during that processing, the voltage may drop to a level where the CPU cannot operate before the checksum generation processing is completed. Is set so as not to occur. Steps S44 to S50 in the power failure occurrence NMI process are an example of a power supply stop process. Note that if a CPU having a specification that does not cause another interrupt during the interrupt process is used, the process of step S42 is unnecessary.

Next, the CPU 56 checks whether or not the backup flag has already been set (step S).
42). If the backup flag has already been set, no further processing is performed. If the backup flag is not set, the following power supply stop processing is executed. That is, the processing from step S44 to step S50 is executed.

First, the contents of each register are backed up R
It is stored in the AM area (step S44). Thereafter, a backup flag is set (step S45). Then, an appropriate initial value is set in the backup check data area of the backup RAM area (step S46),
The exclusive value is sequentially ORed with respect to the initial value and the data in the backup RAM area and then inverted (step S4).
7), the final operation value is set in the backup parity data area (step S48). Further, the RAM access is prohibited (step S49). Further, all output ports are turned off (step S50). When the power supply voltage decreases, the levels of various signal lines may become unstable and the contents of the RAM may be corrupted. However, if the RAM access is prohibited in this manner, the data in the backup RAM may be corrupted. There is no.

Next, the CPU 56 enters a loop process. That is, no processing is performed. Therefore, before the operation is disabled from the outside by the system reset signal from the reset IC 651 shown in FIG. 6, the operation is internally stopped. Therefore, when the power is turned off, the operation of the CPU 56 is reliably stopped. As a result, the RAM access prohibition control and the operation stop control described above can reliably prevent the contents of the RAM from being destroyed due to an abnormal operation that may occur as the power supply voltage decreases. .

In this embodiment, the power failure occurrence NM
In I processing, the program was looped in the last part,
It may be configured to issue a HALT instruction.

The backup flag set after storing the contents of the register in the RAM area is, as described above, whether or not there is backup data to be restored when the power is turned on (whether or not to recover from a power failure). Used to judge. Further, the processing of steps S41 to S50 is completed before the CPU 56 receives the system reset signal from the system reset circuit 65. In other words, the detection voltage of the voltage monitoring circuit is set so as to be completed before receiving the system reset signal from the system reset circuit 65.

In this embodiment, the backup flag is checked at the start of the power supply stop process. If the backup flag has already been set, the power supply stop processing is not executed. As mentioned above,
The backup flag is a flag indicating that the backup of necessary data has been completed and then the power supply stop processing has been completed. Therefore, for example, even if the NMI occurs again for some reason in the reset waiting loop state, the power supply stop processing will not be executed repeatedly.

However, when a CPU having a specification that does not cause another interrupt during the interrupt processing is used, the determination in step S43 is unnecessary.

FIG. 11 is an explanatory diagram for explaining an example of a backup parity data creating method. However,
In the example shown in FIG. 11, the size of the data in the backup data RAM area is set to 3 bytes for simplicity. In the power failure generation process based on the power supply voltage drop, as shown in FIG. 11, initial data (00H in this example) is set in the backup check data area. Next, "00
The exclusive OR of “H” and “F0H” is calculated, and the result is exclusive ORed with “16H”. Further, an exclusive OR of the result and “DFH” is obtained. Then, a value (“C6H” in this example) obtained by inverting the result (“39H” in this example) is set in the backup parity data area.

When the power is turned on again, parity diagnosis is performed in the power failure restoration process. If all the data in the backup area is stored as it is, the data as shown in FIG. 11 is set in the backup area when the power is turned on again.

In the process of step S5, the CPU 56
Performs the same processing as the processing executed in the power generation MNI processing. That is, initial data (00H in this example) is set in the backup check data area, and “0” is set.
An exclusive OR of “0H” and “F0H” is obtained, and an exclusive OR of the result and “16H” is obtained. Further, an exclusive OR of the result and “DFH” is obtained. And
A final operation result obtained by inverting the result (“39H” in this example) is obtained. If all data in the backup area is stored as it is, the final calculation result matches "C6H", that is, the data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final operation result does not become “C6H”.

Therefore, the CPU 56 compares the final operation result with the data set in the backup check data area, and if they match, determines that the parity diagnosis is normal. If they do not match, it is determined that the parity diagnosis is abnormal.

As described above, in this embodiment, the game control means is provided with the variable data storage means (backup RAM in this example) which is backed up for a predetermined period even if the power of the game machine is turned off. When the power is turned on, the CPU
56 (specifically, a program executed by the CPU 56)
Is configured to perform a game state restoration process (step S8) for restoring the game state based on the backup data if the variable data storage means is in the backup state.

In this embodiment, the power supply monitoring circuit is mounted on the power supply board 910 as shown in FIG. 6, and the system reset circuit 65 is mounted on the main board 31 as shown in FIG. When the system reset circuit 65 generates the low-level system reset signal when the power supply voltage decreases, the power supply monitoring circuit (the power supply monitoring IC 902 in this example) outputs the low-level NMI interrupt signal. It is set to be later than when it occurs. Further, a low-level system reset signal from the system reset circuit 65 is input to a reset terminal of the CPU 56.

Then, the CPU 56 enters the loop state after executing the power failure generation processing (power supply stop processing) based on the voltage drop signal from the power supply monitoring means (power supply monitoring IC 902). , And enters a reset state. That is, the operation of the CPU 56 is completely stopped. Below the + 5V power supply voltage value, the normal operation of the CPU 56 cannot be ensured (that is, a state in which the operation cannot be managed occurs), but the CPU 56 is in a reset state while the power supply that can operate normally is supplied. In addition, abnormal operation based on indefinite data is prevented.

As described above, in this embodiment, the CPU
56 is configured to enter a loop state in response to the input of the detection output from the power supply monitoring circuit and to be reset in response to the input of the detection output from the system reset circuit 65. Therefore, when the power is turned off, the data is reliably stored, thereby preventing the player from being disadvantaged.

In this embodiment, the power monitoring I
Although the C902 and the system reset circuit 65 monitor the same power supply voltage, they may monitor different power supply voltages. For example, the power supply monitoring circuit of the power supply board 910 has +30 V
Monitors the power supply voltage and sets the system reset circuit 65 to + 5V
The power supply voltage may be monitored. The threshold level of the system reset circuit 65 (system reset) is set so that the timing at which the system reset circuit 65 generates the low-level system reset signal is later than the timing at which the power supply monitoring circuit generates the NMI interrupt signal. The voltage level at which a signal is generated is set. For example, the threshold is 4.25V. 4.25 V is lower than the normal voltage, but is a voltage at which the CPU 56 can operate for a while. The power supply monitoring circuit adjusts the delay time (for example, the capacity of the capacitor) of the delay means provided in the system reset circuit 65, and determines when the system reset circuit 65 generates a low-level system reset signal by N.
The timing of generating the MI interrupt signal may be delayed.

In the above embodiment, the CPU 56
Detects an NMI interrupt signal from the power supply board (NMI interrupt signal from the power supply monitoring means) via a non-maskable interrupt terminal (NMI terminal), but detects the NMI interrupt signal as a maskable interrupt terminal. (IRQ terminal). In that case, the power supply stop processing is executed in the interrupt processing (IRQ processing). Further, an NMI interrupt signal from the power supply board via the input port may be detected. In that case, the input port is monitored in the main processing.

When an interrupt signal from the power supply board is detected via the IRQ terminal instead of the NMI interrupt signal,
An IRQ interrupt mask may be set at the start of the game control process in step S12 of the main process, and the IRQ interrupt mask may be released at the end of the game control process.
In such a case, an interruption occurs before and after the start of the game control process, so that the game control process is not interrupted halfway. Therefore, there is no possibility that the command transmission is interrupted when the display control command is transmitted to the symbol control board 80 or the like. Thus, even when a power failure occurs, the transmission of the display control command, the payout control command, and the like is reliably completed.

Further, in this embodiment, in the power failure occurrence processing (power supply stop processing), when the backup flag indicating that the data has already been backed up and the power supply stop processing has already been executed is set. Are configured not to execute the power supply stop processing.
In the process of turning off the power, NMI may occur again. Then, if the backup flag is not confirmed in the power failure occurrence processing, the power supply stop processing is executed again by the NMI that has occurred again.

In the normal power supply stop processing executed first, processing for storing the contents of the register in the backup RAM is performed (see step S44 in FIG. 10). Since the power supply voltage gradually decreases in the state of waiting for reset after the normal power supply stop processing executed first, the contents of the register may be destroyed. That is, the register value may have changed from the state at the time when the power-off was detected (when NMI first occurred). If the power supply stop processing is executed again in such a state, a value different from the register value in the state at the time when the power-off is detected is stored in the backup RAM. Then, in the power failure recovery process executed at the time of power recovery, a value different from the register value in the state at the time when the power failure is detected is restored to the register. as a result,
There is a possibility that a game state different from the game state when the power is turned off is reproduced.

Hereinafter, the game state restoring process will be described. FIG. 12 is a flowchart showing an example of the game state restoring process shown in step S8 of FIG. In this example, the CPU 56 restores the value stored in the backup RAM to each register (Step S61). Next, the CPU 56 confirms the game state at the time of the power failure based on the data stored in the backup RAM, and confirms whether or not the game will be restored during the big hit game (step S62). Note that whether or not a big hit game is being performed is confirmed by the value of the special symbol process flag stored even when the power is turned off. In this case, the game state may be determined based on the opening / closing state of the special winning opening (opening / closing plate 20) as to whether or not a big hit game is being played.

Unless the recovery is performed during the jackpot game, C
The PU 56 checks whether or not there is a special symbol starting hold (start winning prize memory) (step S63). Whether or not there is a start winning prize memory is confirmed by the starting prize storing number data in the stored RAM data.

If it is determined in step S62 that the game is to be restored during the jackpot game, or if there is a start winning prize memory in step S63, in this example, the CPU 56 instructs the symbol control board 80 to notify the player of the details of the restoration. Then, a display control command (see FIG. 16) for designating the display of the recovery standby state is transmitted (step S64).

Then, for example, FIG.
As shown in FIG. 7, various information is displayed to notify that the apparatus is waiting for recovery. In this case, for example, as shown in FIG. 13 (A), a display for letting the player recognize a method for canceling the standby state and restoring the game is performed. Further, as shown in FIG. 13 (B), for example, a display may be provided for letting the player recognize what kind of game state is to be restored after the standby state is released (here, the big hit game state is restored). . As another display for notifying the game state after restoration, for example, as shown in FIG.
It may be a display for causing the player to recognize that the change of the special symbol is started after the recovery. Note that FIG.
The display of FIG. 13A and the display of FIG. 13B or 13C may be periodically switched and displayed. Also,
All the contents displayed in FIG. 13A and FIG. 13B or FIG. 13C may be displayed on one screen. For example, a third-type pachinko gaming machine in which a predetermined right is generated or continued when there is a prize in a predetermined electric auditory product which is opened when a stop symbol of a symbol variably displayed based on a start winning prize is a predetermined symbol combination. For example, when it is assumed that the ball is hit toward the right side of the game area during the right generation, the method of hitting the game ball (right hit) may be displayed as the game method after the restoration.

Note that the content of the restoration may be notified by sound or a lamp. In this case, the CPU 56 sends a voice control command for outputting a sound corresponding to the restoration content to the voice control board 70,
For example, a lamp control command for turning on the lamp in accordance with the restoration content is transmitted to the control unit 5.

When a control command output for notifying the details of the restoration is transmitted, the CPU 56 enters a standby waiting signal input waiting state (step S64). In this example, the standby release signal indicates the output signal of the firing detection switch 7a or the output signal of the touch switch 5a.

If the standby release signal is input, or if there is no start winning memory in step S63 (if the number of start winning memories is 0), the CPU 56 sets the backup RA.
The game state at the time of the power failure is confirmed and restored based on the data stored in M (step S66). For example,
Based on the data stored in the backup RAM, the solenoid 16 and the solenoid 21 are driven through the solenoid circuit 59 to restore the open state of the start winning port 14 and the opening / closing plate 20. In addition, according to the value of the special symbol process flag and the normal symbol process flag that have been saved even during the power-off, the control command corresponding to the progress status of the special symbol process process and the normal symbol process process at the time of power-off, It is sent to the symbol control board 80, the lamp control board 35, and the voice control board 70 (step S6).
7).

As described above, in the game state restoring process, the states of various electric components are restored according to the restored internal state, and the symbol control board 80, the lamp control board 35, and the sound control board 70 are restored. Then, a control command for returning the control state to the power-off state (a control command for generating the control state at the time of power-off) is transmitted.
Such a control command is generally one or more control commands that were last sent out before power down.

As described above, in the game state restoring process, a predetermined game state (for example, a state in which a jackpot is generated, or a state in which a jackpot may occur immediately after resuming due to a start winning memory, etc.). When the game is resumed in the absence of the player, the game state may be disadvantageous for the player). When the game is restored to the standby state, the game state is restored. It is possible to prevent the player from being disadvantaged, and to improve the convenience of the gaming machine.

Further, as described above, in the game state restoring process, the player's intention (the intention to start the game, which is indicated by touching the operation knob 5 or firing the game ball). The game state is restored in response to the input of the standby release signal that is output by the player, so that the player's intention can determine when to resume the game state, and the game state can be restored in the absence of the player It is possible to prevent the player from being disadvantaged. Therefore, the convenience of the gaming machine can be improved.

As a result of the processing described above, in this embodiment, the following state recovery can be performed by the game state recovery processing.

The winning opening 14 and the winning opening (opening and closing plate 2)
The state of 0) is restored. Display state of normal symbols controlled by display control means (display state of variable display 10)
Is restored except when it is changing when the power is turned off. The display state of the special symbol controlled by the display control means (the display state of the variable display unit 9) is restored except for the case where it is changing when the power is turned off. Further, the variable display unit 9
Are restored except during the special symbol change and during the big hit game.

When the power is turned off during the change of the special symbol, information on the change time (for example, 10 seconds) of the variable display pattern and the already executed time (for example, 4 seconds) are backed up. Then, at the time of restoration, the main board 31 outputs a display control command indicating a display pattern and a display control command indicating a stop symbol to the symbol control board 80, and stops the symbol after a lapse of the remaining time (6 seconds in the above example). Output a display control command to cause Therefore, when the special symbol is changing when the power is turned off, the display state of the special symbol is variably displayed for the remaining time (6 seconds in the above example) not displayed at the time of restoration. The display control command indicating the display pattern output to the symbol control board 80 at the time of restoration may be the same as the display control command indicating the display pattern output before the power was turned off. It is good also as a command for displaying an image like "in the middle." In this case, the display "recovering from power failure" is displayed for the remaining time (6 seconds in the above example). The same control as described above is performed for the display state of the ordinary symbol when the power is turned off during the change of the special symbol.

When the power is turned off during the big hit game, the remaining time of the round or the interval between the rounds is restored when the power is turned off during the change of the special symbol. , Display, sound, lamp,
Although the solenoid 21 and the like are controlled, the main board 31 outputs a display control command to the symbol control board 80 which designates a symbol at the time of confirmation (stop symbol) output before the power is turned off.
Thereby, the effect by the big hit symbol during the round or between the rounds becomes possible (for the model that performs the big hit with the big hit symbol), and the symbol displayed at the start of the fluctuation after the big hit end can be recognized by the symbol control board 80. .

Decorative lamp 2 controlled by lamp control means
5, start memory display 18, gate passage memory display 41,
The display states of the award ball lamp 51 and the ball out lamp 52 are restored. Game effect lamps / LEDs 28a, 28b, 2
The display state of 8c is restored except when the special symbol is being changed and the big hit is being played. However, if a big hit is being played when the power is turned off, the initial state of each control section can be restored. The control sections are, for example, a jackpot start notification state, a state before the opening of the special winning opening, a state during opening of the special winning opening, and a notification state of the big hit end. When the power is turned off during the change of the special symbol and the power is turned off, the game effect lamps / LEDs 28a, 28b, and 2 are provided for the remaining time, similarly to the display control of the variable display unit 9 and the variable display device 10 described above.
Although the display state of 8c may be controlled, it may be turned off or turned on or off in a pattern specific to turning off or restoring the power failure.

The sound generation state controlled by the voice control means is restored except during a special symbol change and a big hit game. However, if a big hit is being played when the power is turned off, the initial state of each control section can be restored.
When the power is turned off during the special symbol change and the power is restored, the sound generation state is controlled for the remaining time in the same manner as the display control of the variable display unit 9 and the variable display device 10 described above. Alternatively, a sound pattern specific to silence or power recovery from a power failure (for example, a voice saying “power recovery is in progress”) may be output.

In this embodiment, at the time of restoration from power-off, a control command for restoring a state is sent from the game control means of the main board 31 to the display control means, the lamp control means and the voice control means. However, when the display control means, the lamp control means, and the sound control means are backed up by a power source, the display control means, the lamp control means, and the sound control means independently control without using a control command from the main board 31. The state may be restored.

Further, as described later, the payout control board 37
Since the payout control means mounted on the power supply is backed up by a power supply, the prize sphere payout state and the ball lending control state are restored to the state at the time of power-off when the power-off is restored. In this embodiment, since the firing control board is connected to the payout control means, the control state of the firing control board 91 is similarly restored.

When the game state is returned to the state at the time of power-off, in this embodiment, the CPU 56 restores the interrupt permission / prohibition state at the time of the previous power-off to save the parity stored in the backup RAM. The value of the flag is confirmed (step S68). If the parity flag is clear, interrupt permission setting is performed (step S69). On the other hand, if the parity flag is on, the state is unchanged (step S1).
The game state restoring process ends (with the interrupt prohibition state set in a).

Here, the game state restoring processing program is configured to return to the main processing when the game state restoring processing ends, but the stack area pointed to by the stack pointer stored in the power supply stop processing is set. The address stored in the backup RAM area (in the backup RAM area) (the address executed when the NMI interrupt occurs when the power is turned off) may be returned.

As described above, after the initial setting process is started, before the recovery process is completed, or before the initialization process is completed, the interrupt is prohibited. Can be prevented from being interrupted, the initial setting, the operation state of the clear switch 921 and the determination as to whether or not to restore the power-off state performed according to the contents of the backup data storage area, and the restoration The processing (or the initialization processing) can be surely completed. Even in the case where the interrupt prohibition state is set before the end of the recovery processing as described above, the interrupt prohibition / permission state at the time of power-off is backed up by the parity flag. The interrupt prohibition / permission state when the power is turned off can be reliably restored.

In the above embodiment, a case has been described in which the game control means performs the data saving processing and the recovery processing, but the payout control means, the voice control means, the ramp control means, and the RAM in the display control means.
May be backed up by a power source, and the payout control unit, the display control unit, the sound control unit, and the lamp control unit may also perform the above-described processing. However, the payout control means, the display control means, the sound control means, and the lamp control means do not need to perform the command transmission processing at the time of restoration.

Next, transmission of a control command from the main board 31 to another electric component control board will be described. Figure 1
4 is an explanatory diagram showing an example of a command form of a control command sent from the main board 31 to each electric component control board. In this embodiment, the control command has a 2-byte configuration, the first byte represents MODE (classification of command), and the second byte represents EXT (type of command). M
The first bit (bit 7) of the ODE data is always "1", and the first bit (bit 7) of the EXT data is always "0". The command form shown in FIG. 14 is an example, and another command form may be used.

FIG. 15 is a timing chart showing the relationship between an 8-bit control signal constituting a control command for each electric component control board and an INT signal (strobe signal). As shown in FIG. 15, when a predetermined period elapses after the MODE or EXT data is output to the output port, the CPU 56 outputs the signal INT indicating the data output.
Turn on the signal. When a predetermined period elapses therefrom, the INT signal is turned off.

FIG. 16 is an explanatory diagram showing an example of the contents of the display control command sent to the symbol control board 80 of the electric component control board. In the example shown in FIG. 16, commands 8000 (H) to 8022 (H), 8100 (H)
Reference numerals 8122 (H) denote display control commands for designating a variation pattern of a special symbol in the variable display section 9 for variably displaying a special symbol. Note that the command for designating the variation pattern also serves as the variation start instruction. Further, in the example shown in FIG. 16, 70 types of variation pattern designations are possible, but only a part of the variation pattern designations may be used.

The command 88XX (X = arbitrary value of 4 bits) is a display control command relating to the variation pattern of the ordinary symbol variably displayed on the ordinary symbol display 10. The command 89XX is a display control command for designating a stop symbol of a normal symbol. Command 8AXX (X = arbitrary value of 4 bits) is a display control command for instructing to stop variable display of a normal symbol.

Commands 91XX, 92XX and 93X
X is a display control command for designating a left middle right stop symbol of a special symbol. The command A0XX is a display control command for instructing to stop the variable display of the special symbol.
The command BXXX is a display control command sent from the start of the big hit game to the end of the big hit game. The commands C000 to EXXXX are display control commands related to the display state of the variable display unit 9 irrespective of the change of the special symbol and the jackpot game. For example, the command C0
01 is a display control command for instructing display of the standby state transmitted in step S64 of FIG. Upon receiving the above-described display control command from the game control means of the main board 31, the display control means of the symbol control board 80 changes the display state of the variable display section 9 and the ordinary symbol display 10 according to the contents shown in FIG. change.

In this embodiment, when the power of the gaming machine is turned on and the game control means starts the game control, an initial display command of the command C000 is transmitted to the display control means. When the power is turned on, the backup RAM stores information indicating the game state immediately before the last power-off (in this example, excluding the information indicating that there is a jackpot game state or a state in which there is a start winning memory). Then, a display control command is sent to the display control means so that the game state is restored and the control state of the display control means returns to the game state immediately before power-off.

On the other hand, when the power is turned on, the backup RAM
If the information indicating the gaming state immediately before the last power-off (in this example, the information indicating that there is a jackpot gaming state or a state in which there is a start winning memory) is stored in the standby state, the display control means is in the standby state. Display indicating that there is (see FIG. 13)
Is transmitted to the display control means in order to make the control state such that the display control command is executed. In this case, when the display control unit receives the command C001, the display state of the variable display unit 9 becomes a display indicating that the display unit is in the standby state (see FIG. 13).

When the standby release signal is input in step S65 of FIG. 12, the game state is restored based on various information indicating the game state immediately before the last power-off stored in the backup RAM, and the display state is displayed. A display control command is sent to the display control means so that the control state of the control means returns to the game state immediately before the power is turned off. For example, if the gaming state immediately before the power is turned off is the jackpot gaming state and the second round, the command B1
02 is sent to the display control means. When the display control unit receives the command B102, the display state of the variable display unit 9 returns to the display corresponding to the second round.

A display control command for returning the control state to the display control means is given, and a lamp control command and a voice control command for returning the control state to the lamp control means and the voice control means are transmitted. You may make it. In addition, a display control command for notifying the player of the standby state to the display control means is given, and the lamp control means and the sound control means are notified of the standby state to the player. May be transmitted.

The case where the information indicating the game state immediately before the last power-off is stored in the backup RAM is a case where a short-time power interruption (momentary interruption) occurs. As shown in FIG. 6, the power-off signal from the power supply board 910 is connected to the XNMI terminal (non-maskable interrupt terminal) of the CPU 56. Therefore, in this embodiment,
The CPU 56 performs processing for saving the gaming state at that time in the backup RAM by non-maskable interrupt processing when power supply to the gaming machine is stopped. The processing for storing the game state in the backup RAM is, for example,
This is a process for protecting the contents of the backup RAM area such as addition of parity data.

Next, the command sending process will be described. As described above, the symbol control board 8
When a control command is to be output to each electrical component control board such as 0, a command transmission table is set. FIG. 17A is an explanatory diagram illustrating a configuration example of the command transmission table. One command transmission table is 3
The first byte is set with INT data. In the command data 1 of the second byte, MODE data of the first byte of the control command is set. Then, in the command data 2 of the third byte, EXT data of the second byte of the control command is set.

Although the EXT data itself may be set in the command data 2 area, the command data 2
May be set to data for specifying an address of a table in which EXT data is stored. In this embodiment, bit 7 of command data 2
If (work area reference bit) is 0, it indicates that the EXT data itself is set in the command data 2. Such EXT data is data in which bit 7 is 0. If the work area reference bit is 1,
The other 7 bits indicate an offset for specifying the address of the table in which the EXT data is stored. In this embodiment, a command transmission table is prepared for each control command.

FIG. 17B is an explanatory diagram showing an example of the configuration of INT data. Bit 0 in the INT data indicates whether or not a payout control command should be sent to the payout control board 37. If bit 0 is "1", it indicates that a payout control command should be sent. Therefore, the CPU 56
For example, when sending out the payout control command in the prize ball processing, “01 (H)” is set in the INT data of the command transmission table for the payout control command.

Bits 1, 2, and 3 of the INT data are bits indicating whether or not to transmit a display control command, a lamp control command, and a voice control command, respectively.
If the PU 56 is to send those commands,
INT is stored in the command transmission table indicated by the pointer.
Data, command data 1 and command data 2 are set. When sending those commands, INT
The corresponding bit of the data is set to “1”, and MODE data and E
XT data is set.

FIG. 18 is a flowchart showing an example of the command sending process. The command sending process is a process including a command output process and an INT signal output process.
In the command control process, the CPU 56 first saves the address of the command transmission table in a stack or the like (Step S331). Then, the INT data of the command transmission table is loaded into the argument 1 (step S33).
2). Argument 1 is input information for a command transmission processing routine to be described later. Further, the address indicating the command transmission table is incremented by 1 (step S333). Therefore, the address indicating the command transmission table matches the address of the command data 1.

Therefore, the CPU 56 sets the command data 1
Is read and set as argument 2 (step S334).
The argument 2 also becomes input information for a command transmission processing routine described later. Then, a command transmission processing routine is called (step S335).

FIG. 19 is a flowchart showing a command transmission routine. In the command transmission routine,
First, the CPU 56 sets the data set in the argument 1, that is, the INT data, in the work area determined as the comparison value (step S351). Then
The number of processes = 4 is set in the work area determined as the number of processes (step S352). Then, the address of the port 1 for outputting the payout control signal is set to the IO address (step S353). In this embodiment, the address of port 1 is the address of output port 571.

Next, the CPU 56 shifts the comparison value one bit to the right (step S354). It is determined whether or not the carry bit has become 1 as a result of the shift processing (step S355). The fact that the carry bit has become 1 means that the rightmost bit in the INT data is “1”.
It means that it was. In this embodiment, four shift processes are performed. For example, when it is specified that a payout control command should be sent, the carry bit becomes 1 in the first shift process.

When the carry bit becomes 1, the data set in the argument 2, in this case, the command data 1 (ie, MODE data) is output to the address set as the IO address (step S3
56). When the first shift processing is performed, since the address of the port 1 is set in the IO address, the MODE data of the payout control command is eventually output to the port 1 (output port 571).

Next, the CPU 56 sets the IO address to 1
While adding (step S357), 1 is subtracted from the number of processes (step S358). If the port 1 is indicated before the addition, the IO address is set to the address of the port 2 by the addition processing for the IO address. Port 2 is an output port 572 in this embodiment.
And a port for outputting a display control command. Then, the CPU 56 checks the value of the number of processes (step S359), and returns to step S354 if the value is not 0. The shift process is performed again in step S354.

In the second shift processing, the value of bit 1 in the INT data is pushed out, and the carry flag becomes "1" or "0" according to the value of bit 1. Therefore,
A check is made as to whether it is specified that a display control command should be sent. Similarly, in the third and fourth shift processes, it is checked whether or not it is specified that the ramp control command and the voice control command should be transmitted. As described above, when each shift process is performed, the IO address corresponding to the command (payout control command, display control command, lamp control command, voice control command) set by the shift process is set in the IO address. Have been.

As described above, when the carry flag becomes "1", a control command is sent to the corresponding output port (port 1 to port 4). That is, a single common module (command transmission processing) can perform control command transmission processing to a plurality of electric component control means. In this embodiment, the addresses of ports 3 and 4 are an output port for transmitting a lamp control command and an address for transmitting a voice control command, respectively.

As described above, since it is determined to which electrical component control means the control command is to be output by only the shift processing, it is determined to which electrical component control means the control command is to be output. Processing has been simplified.

Next, the CPU 56 reads the contents of the argument 1 storing the INT data before the start of the shift processing (step S360), and outputs the read data to the port 0 (step S361). In this embodiment,
The address of port 0 is the address of output port 570. For the INT data, steps S351 to S359
Control commands (payout control commands,
The bit corresponding to the output bit of the INT signal according to the display control command, the lamp control command, and the voice control command is “1”. Therefore, port 1 to port 4
The INT signal corresponding to the control command (payout control command, display control command, lamp control command, voice control command) output to any of the above is turned on.

Next, the CPU 56 sets a predetermined value in the weight counter (step S362), and decrements by one until the value becomes 0 (steps S363 and S36).
4). This processing is performed according to I shown in the timing diagram of FIG.
This is a process for setting the ON period of the NT signal (control signal INT). When the value of the wait counter becomes 0, clear data (00) is set (step S365),
The data is output to port 0 (step S36)
6). Therefore, the INT signal is turned off. And
A predetermined value is set in the weight counter (step S36)
2) Subtract 1 by 1 until the value becomes 0 (steps S368 and S369). This process is a process for setting a period from the fall of the first INT signal to the start of EXT data output.

Therefore, the value set in the wait counter in step S367 is such that the period from the falling edge of the first INT signal to the start of the EXT data output is ensured by all the electric component control means to receive the control command. Is a value sufficient to perform the command reception process. Further, the value set in the weight counter is a value such that the period is longer than the time required for the processing of steps S351 to S359.

As described above, the MODE data of the first byte of the control command is transmitted. Therefore, CPU5
6, step S336 shown in FIG. 18 adds 1 to the value indicating the command transmission table. Therefore, the area of the command data 2 in the third byte is specified. The CPU 56
The contents of the indicated command data 2 are loaded into the argument 2 (step S337). Further, it is determined whether the value of bit 7 (work area reference bit) of the command data 2 is “0” (step S339). If it is not 0, the start address of the command extension data address table is set in the pointer (step S339), and the address is calculated by adding the value of bit 6 to bit 0 of the command data 2 to the pointer (step S340). Then, the data of the area indicated by the address is loaded into the argument 2 (step S341).

In the command extension data address table, EXT data that can be transmitted to the electric component control means is sequentially set. Therefore, if the value of the work area reference bit is “1” by the above processing, the EXT data in the command extension data address table corresponding to the content of the command data 2 is loaded into the argument 2 and the work area reference bit is set. If the value is “0”, the content of the command data 2 is loaded as it is into the argument 2. Even when EXT data is read from the command extension data address table, bit 7 of that data is “0”.

Next, the CPU 56 calls a command transmission routine (step S342). Therefore, MOD
The EXT data is transmitted at the same timing as the transmission of the E data.

As described above, the command transmission processing module, which is one control signal output module,
Each 2-byte control command (dispensing control command, display control command, lamp control command, voice control command) is transmitted to the corresponding electric component control means. In the electric component control means, when detecting the falling of the INT signal as the fetch signal, the control command fetch process is started. Is not output to the signal line. That is,
In each electric component control means, a reliable command receiving process is performed. Note that each electric component control unit may start the process of capturing a control command at the rising edge of the INT signal. Further, the polarity of the INT signal may be reversed from the case shown in FIG.

Next, the processing in the symbol control board 80 will be described. FIG. 20 is a flowchart showing the main processing of the symbol control CPU 101. In the main process, the symbol control CPU 101 first performs an initial value setting process such as clearing the RAM area (step S70).
1). For example, when data is set in a RAM area (backup RAM area) of the built-in RAM in which the power is backed up, those areas are not cleared. Thereafter, in this embodiment, the symbol control CPU 101 monitors the timer interrupt flag (step S
The flow shifts to a loop process for performing the confirmation in step 702).

In this embodiment, the symbol control CPU 10 is designed so that a timer interrupt is periodically performed every 2 ms.
Initial setting of the timer register provided in 1 (timeout is 2 ms and setting of repetition timer operation) is performed. That is, a process of activating a timer interrupt and a process of setting a timer interrupt interval are executed.

Therefore, in this embodiment, the internal timer of the symbol control CPU 101 is set so as to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. Then, as shown in FIG. 21, when a timer interrupt occurs, the symbol control CPU 101
Sets the timer interrupt flag (step S71)
1).

The symbol control CPU 101 proceeds to step S7.
In 02, when it is detected that the timer interrupt flag has been set, the timer interrupt flag is reset (step S703), and an image control process for performing display control according to a command from the game control means (step S70)
Execute 4). According to the above control, in this embodiment, the image control process is activated every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the image control process is executed in the main process. However, the image control process may be executed in the timer interrupt process. In the image control process, image control is performed on a special symbol, a normal symbol, a standby symbol (see FIG. 13), and the like.

FIG. 22 is a flowchart showing a display control command receiving process by the interrupt process. As described above, the display control INT signal from the main board 31 is the symbol control C signal.
The signal is input to the interrupt terminal of the PU 101. Therefore, when the display control INT signal from the main board 31 is turned on,
The symbol control CPU 101 is interrupted, and the display control command receiving process shown in FIG. 22 is started.

In the display control command receiving process, the symbol control CPU 101 reads 1-byte data from the input port assigned for inputting the display control command data (step S881). Then, the read data is stored in the work area as received data (step S882). Further, a communication end flag is set (step S883).

With the above processing, the display control command sent from the main board 31 is read by the symbol control CPU 101. Here, since there is a possibility that a plurality of display control commands may be continuously received, a plurality of work areas and communication end flags are prepared.

FIG. 23 is a flowchart showing an example of the special symbol display processing. This special symbol display processing is shown in FIG.
3 is a process included in step S704 of the display main process. In the special symbol display process, the symbol control CPU 101 first checks whether or not the special symbol is changing on the variable display unit 9 (step S14).
1). If it is changing, it is checked whether a display control command indicating a special symbol change stop has been received (step S).
142). If it has not been received, the special symbol variation process is continued (step S144). When the display control command indicating the special symbol stop is received, when the display control command including the information of the big hit is received in step S146 described later, the special symbol finalizing display of the symbol corresponding to the big hit is performed ( Step S143). When the display control command including the information indicating the loss is received in step S146, the special symbol confirmation display of the symbol corresponding to the loss is executed (step S143).

If it is determined in step S141 that the special symbol is not fluctuating, it is checked whether or not the special symbol confirmation display is being displayed on the variable display section 9 (step S145). If not, it is confirmed whether or not a display control command indicating the start of the special symbol change has been received (step S14).
6). If it has been received, the special symbol variation process is started (step S147). During the change of the special symbol, the symbol control CPU 101, for example,
The display is performed such that each symbol displayed in one display area changes.

If it is determined in step S145 that the special symbol confirmation display is being displayed, it is checked whether a display control command indicating a special symbol stop has been received (step S14).
8). If it has not been received, the special symbol confirmation display is continuously performed (step S150). When the display control command indicating the special symbol stop has been received, the special symbol determination display ends (step S149).

FIG. 24 is a flowchart showing an example of the ordinary symbol display processing. This normal symbol display process is a process performed subsequent to the special symbol display process, and is the process shown in step S704 of the display control main process in FIG. In the ordinary symbol display process, the symbol controlling CPU 101 first checks whether or not the ordinary symbol is changing on the variable display 10 (step S15).
1). If not, it is confirmed whether or not a display control command indicating the start of normal symbol change has been received (step S
152). If it has been received, the normal symbol variation process is started (step S153). Normally, during the fluctuation of the symbol, the symbol control CPU 101 causes the variable display 10 to display a numeral by counting up every 0.1 second, for example.

In step S151, if the ordinary symbol is changing, it is checked whether a display control command indicating the end of the ordinary symbol change has been received (step S15).
4). If it has not been received, the normal symbol variation process is continued (step S156). When the display control command indicating the end of the normal symbol change is received, the symbol change of the variable display 10 is stopped with the stop symbol already received (step S155).

As described above, in this embodiment, the symbol control CPU 101 mounted on the symbol control board 80 is
The symbol control of the variable display section 9 for variably displaying special symbols and the variable display 10 for variably displaying ordinary symbols is performed. Then, the CPU 56 of the main board 31 starts the change of the display on the variable display unit 9, at the end of the change, and at the end of the display,
Further, at the time of start and end of the change of the display on the variable display 10, a command indicating the change is sent to the symbol control board 80.

The symbol control CPU 101 can recognize the fluctuation time and the display time of the notification symbol based on each command. Since the CPU 56 of the main board 31 sends a command so that the fluctuation time can be specified, the CPU 56 does not need to send a command indicating other detailed control. For example, it is not necessary to send a command indicating a symbol after changing every 0.1 seconds or 0.2 seconds.

In this embodiment, the CPU 56 of the main board 31 sends a command at the start of the change, at the end of the change, and at the end of the display, whereby the CPU for the symbol control is sent.
Although 101 is capable of specifying the fluctuation time and the display time, a command indicating the fluctuation time itself may be transmitted at the start of the fluctuation, or a command indicating the display time may be transmitted at the end of the fluctuation. Is also good.
In the case of such a configuration, the symbol control CPU 101
By checking whether or not a command indicating the end of the change has been received when the change time has elapsed, and by checking whether or not a command indicating the end of the display has been received when the display time has elapsed, the change control of the normal symbol and the special symbol can be more improved It can be done reliably. For example, if a command indicating the end of the change is not received after the elapse of the change time, or if a command indicating the end of the display is not received after the elapse of the display time, it may be determined that some abnormality has occurred in the communication.

Also, instead of sending a command indicating the fluctuation time at the start of the fluctuation, At the end of the fluctuation period, a command indicating that may be sent. That is, a command indicating the end of the fluctuation period may be transmitted after the command indicating the end of the fluctuation (symbol determination) is transmitted. Similarly, instead of sending a command indicating the display time at the end of the change. At the end of the display period, a command to that effect may be sent. That is, after sending the command indicating the end of the display, a command indicating the end of the display period may be sent. Even with such a configuration, the fluctuation control of the ordinary symbol and the special symbol can be performed more reliably.

FIG. 25 is a flowchart showing an example of the standby symbol display processing. This standby symbol display process is a process performed before the restoration of the gaming state when the predetermined gaming state is restored by the power restoration, and is the processing shown in step S704 of the display control main processing in FIG. is there. In the standby symbol display process, the symbol control CP
U101 first checks whether or not a standby symbol is displayed on the variable display unit 9 (step S161). If it is not being displayed, it is confirmed whether or not a display control command for designating the display of the recovery standby state has been received (step S16).
2). If it has been received, a standby symbol display process is started (step S163). In the standby symbol display process, the symbol control CPU 101, for example, in the variable display unit 9,
For example, a display as shown in FIG. 13 is performed.

It should be noted that the notification of the standby state, the game state after recovery, etc. does not have to be displayed on the variable display unit 9; for example, it is displayed on a dedicated display device for notification. Is also good.

In step S161, if the standby symbol is being displayed, a display control command indicating the end of the standby state (here, a display control command that can recognize that the gaming state has been recovered may be used. It is confirmed whether or not a display control command other than the standby state display designation command) has been received (step S164). If not received, the standby symbol display process is continued (step S1).
66). When the display control command indicating the end of the standby state is received, the display of the standby symbol is ended (step S165), and the received display control command (the display control command also indicating the end of the standby state) is received. The symbol display control based on the symbol is executed.

As described above, in this embodiment, the symbol control CPU 101 mounted on the symbol control board 80 is
The symbol control of the variable display unit 9 for displaying the standby symbol is performed. Then, the CPU 56 of the main board 31 sends a command to that effect to the symbol control board 80 when the display of the standby symbol on the variable display section 9 starts and ends.

The symbol control CPU 101 can recognize whether or not to display the standby symbol based on each command and whether or not to end the display of the standby symbol.

As described above, the variable display section 9 displays the status of the recovery standby state and the like, so that the player can accurately grasp the current situation and avoid confusion. It becomes possible.

As described above, in the game state restoring process, in the predetermined game state (for example, a state in which a big hit may occur immediately after resumption due to a state of a big hit or a start winning prize memory). When the game is resumed in the absence of the player, the game state may be disadvantageous for the player). When the game is restored to the standby state, for example, the game state is restored in the absence of the player. Thus, it is possible to prevent the player from being disadvantaged, and to improve the convenience of the gaming machine.

Further, as described above, in the game state restoring process, the game state is restored in response to the input of the standby release signal output based on the player's intention. The timing for restoring the gaming state can be determined, and the gaming state is not restored in the absence of the player, thereby preventing the player from being disadvantaged. Therefore, the convenience of the gaming machine can be improved.

Further, as described above, after the initial setting process is started, before the restoration process is completed or before the initialization process is completed (during the initial preparation process), the interrupt is prohibited. With this configuration, processing can be prevented from being interrupted by an interrupt.
It is possible to determine whether or not to restore the state at the time of power interruption performed according to the contents of the backup data storage area, and to surely complete the restoration process (or the initialization process). Even in the case where the interrupt prohibition state is set before the end of the recovery processing as described above, the interrupt prohibition / permission state at the time of power-off is backed up by the parity flag. Prohibition of interrupt when power is turned off /
The permission state can be reliably restored. in this case,
The processing included in the initial preparation processing is an example, and the initial preparation processing is, for example, processing of the above-described processing, such as processing from starting the initial setting processing to determining whether to perform restoration based on backup data. It may be a part.

In each of the above-described embodiments, the game state is restored when the release signal is input in step S65 during the standby state. You may make it return a gaming state.

In this case, for example, as shown in FIG. 26, when in the standby state, the symbol control CPU 101 counts a predetermined wait time (step S70), and confirms that the predetermined wait time has elapsed. If so, the game state may be restored. During this wait time, various displays as shown in, for example, FIG. 13 described above are performed on the symbol display unit 9 to notify the user that the game is on standby, the game state after restoration, and the like. In addition, you may make it alert | report by a lamp or a sound.

With this configuration, if the content of the restoration of the game state is, for example, a jackpot control state in which the player may be disadvantaged if the player does not take immediate action,
The game state can be returned after a predetermined wait time has elapsed, and even if the player is not waiting near the gaming machine,
If the game can be brought into a playable state before the predetermined wait time has elapsed, it is possible to prevent the player from being disadvantaged. In other words, even if the player is away from the gaming machine while the power is turned off, the player can avoid disadvantage if the player is in a place where the game can be played before the predetermined wait time has elapsed.

Further, in each of the above-described embodiments, the power supply monitoring means is installed on either the power supply board or the electric component control board. Can be installed at any position according to the conditions.

In each of the above embodiments, the case where the RAM is used as the storage means is shown. However, if the storage means is an electrically rewritable storage means, the RAM is used.
Other than these may be used.

Further, in each of the above-described embodiments, the notification to the player about the standby state and the content of the recovery is made by the screen display, but the notification is made by turning on, off, blinking, blinking, etc. of the lamp. Or may be notified by sound.

In the above embodiment, the power supply monitoring circuit is provided on the power supply board 910. However, the power supply monitoring circuit may be provided on the electric board control board such as the main board 31 or the payout control board 37. . When an electric component control board on which a power supply circuit is mounted is configured, the power supply board includes
No power monitoring circuit is installed.

The pachinko gaming machine 1 of each of the above embodiments
Is a first-class pachinko gaming machine in which a predetermined game value can be given to a player when a stop symbol of a special symbol variably displayed on the variable display portion 9 based on a start winning prize is a predetermined symbol combination. However, if there is a prize in a predetermined area of the electric accessory that is opened based on a winning start, a second-type pachinko gaming machine that can give a predetermined game value to a player, or is variably displayed based on a starting prize. The present invention can be applied to a third-type pachinko gaming machine in which a predetermined right is generated or continued when there is a prize for a predetermined electric accessory which is opened when a symbol combination of a predetermined symbol is released.

Furthermore, not only for pachinko gaming machines, but also for slot machines and the like, when power is cut off due to a power failure or the like, data immediately before the power is cut off is stored in a backup RAM or the like, and when power is restored, control restart processing based on the stored data is performed. The present invention can be applied to such a case. For example, when the present invention is applied to a slot machine, it is possible to select whether an internal flag (a flag such as a big, regular, small part, etc.) or a state such as a big state is restored.

[0197]

As described above, according to the present invention, a gaming machine capable of playing a predetermined game is an electronic component for controlling an electrical component provided in the gaming machine. An electrical component control board on which a control microcomputer is mounted; a variation data storage means for storing variation data generated when the electrical component control microcomputer performs control; and a variation immediately before power-off for at least a predetermined period after the power supply is stopped. A storage content holding means capable of holding the final storage content of the data storage means; and an electric component based on the final storage content when the final storage content is stored in the variable data storage means when power supply is started. A control restoration unit capable of restoring control; and a restoration start suspension unit capable of suspending the restoration of control by the control restoration unit. The stage is characterized in that it is possible to release the suspension of the recovery start when a recovery start signal permitting the start of the recovery is input, so that the game state is recovered in the absence of the player and the player The disadvantage can be prevented, and the convenience of the gaming machine can be improved.

When the recovery start suspending means can determine whether or not to suspend the recovery start with reference to the final storage contents, the game state is restored without the player present. It is possible to determine whether to suspend the control start or to immediately start the control based on the determination as to whether or not to return to the gaming state in which the player will be disadvantaged if the game is not performed. Therefore, it is possible to prevent the player from being disadvantaged by restoring the game state while the player is absent, and to improve the convenience of the gaming machine.

A game control means capable of controlling a specific game state advantageous to the player on condition that the result of the predetermined game becomes a specific mode is provided. At least when the content indicates the specific game state, if the start of the recovery is suspended, for example, when resuming to the specific game state such as a big hit, the control can be suspended from being resumed. In addition, it is possible to prevent the player from being disadvantaged (for example, ending the big hit game state without the player) due to the restoration of the game state without the player.

[0200] A start detecting means for detecting start in response to a predetermined winning is provided, and a predetermined game for deciding whether or not to enter a gaming state advantageous to the player in response to one start detection. Is started, the start detection number can be held for a predetermined number, and the recovery start holding means holds the recovery start when the final storage content indicates at least that the start detection number is held. In the case of the feature, when the power is restored, for example, the start of the change of the special symbol can be suspended, so that the game state is restored without the player being present and the player is disadvantaged (for example, a big hit without the player being present) It is possible to prevent the player from being in a gaming state and further suffering disadvantages such as ending the jackpot gaming state.

A display device for providing a predetermined notification to the player is provided. When the recovery start is suspended, a predetermined screen is displayed on the display device. Can be notified to the outside, for example, to make the player recognize that the game is on hold.

When the predetermined screen display is characterized by including a display for instructing the player on a method of starting recovery, for example, the hold is released to the player or the like to resume the game. Can be notified, and the convenience of the gaming machine can be improved without any confusion on the player side.

When the predetermined screen display is characterized by including a display for notifying the final storage contents,
Since the player can be made aware of the control state at the time of resumption, after the player resumes (without grasping the current state)
You can play games immediately.

If the restoration start signal is transmitted by a predetermined operation of the player, the control can be restarted by the player's intention, and the convenience for the player can be improved.

If a touch sensor for detecting that the player has touched the gaming machine is provided, and a recovery start signal is transmitted in response to the detection of the touch sensor, the player may touch the touch sensor. As a result, control can be resumed, and convenience for the player can be improved.

If a firing ball detector for detecting that a game ball has been fired is provided, and a recovery start signal is transmitted in response to the detection of the firing ball detector, the game ball is fired. Control can be resumed according to
It is possible to improve the convenience for the player.

[Brief description of the drawings]

FIG. 1 is a front view showing an example of a pachinko gaming machine viewed from the front.

FIG. 2 is a front view showing an example of the gaming board of the pachinko gaming machine viewed from the front.

FIG. 3 is a rear view showing an example of a mechanical plate of the pachinko gaming machine viewed from the rear.

FIG. 4 is a block diagram showing a circuit configuration example of a game control board (main board).

FIG. 5 is a block diagram showing a circuit configuration in a symbol control board.

[Fig. 6] C for power supply monitoring and power supply backup
FIG. 3 is a block diagram illustrating a configuration example around a PU.

FIG. 7 is a block diagram illustrating a configuration example of a power supply board.

FIG. 8 is a flowchart showing main processing executed by a CPU on a main board.

FIG. 9 is an explanatory diagram showing an example of a method of determining whether or not to execute a game state restoration process.

FIG. 10 is a flowchart illustrating an example of a power failure occurrence NMI process.

FIG. 11 is an explanatory diagram for describing an example of a backup parity data creation method.

FIG. 12 is a flowchart illustrating an example of a game state restoration process.

FIG. 13 is an explanatory diagram showing an example of a display for notifying that the game state is a standby state for recovery from a game state.

FIG. 14 is an explanatory diagram illustrating an example of a command form of a control command.

FIG. 15 is a timing chart showing the relationship between an 8-bit control signal and an INT signal that constitute a control command.

FIG. 16 is an explanatory diagram showing an example of the content of a display control command.

FIG. 17 is an explanatory diagram illustrating a configuration example of a command transmission table.

FIG. 18 is a flowchart illustrating an example of a command sending process.

FIG. 19 is a flowchart illustrating an example of a command transmission process.

FIG. 20 is a flowchart showing a main process executed by a symbol control CPU.

FIG. 21 is a flowchart showing a timer interrupt process in the symbol control CPU.

FIG. 22 is a flowchart showing a display control command reading process.

FIG. 23 is a flowchart showing a special symbol display process.

FIG. 24 is a flowchart showing a normal symbol display process.

FIG. 25 is a flowchart showing standby symbol display processing.

FIG. 26 is a flowchart showing another example of the gaming state restoring process.

[Explanation of symbols]

 1 Pachinko gaming machine 31 Main board 53 Basic circuit 56 CPU 80 Symbol control board 101 Symbol control CPU 372,570 Input port 910 Power supply board

Claims (10)

[Claims] 1. A game machine capable of playing a predetermined game, comprising: an electric component control board mounted with an electric component control microcomputer for controlling an electric component provided in the game machine; Fluctuation data storage means for storing fluctuation data generated when the control microcomputer performs control, and storage contents capable of retaining final storage contents of the fluctuation data storage means immediately before power-off for at least a predetermined period after power supply is stopped Holding means, and control restoring means capable of restoring control of an electrical component based on the final storage content when the variation data storage means has retained the final storage content when power supply is started And a recovery start suspending means capable of suspending the start of control restoration by the control restoration means. If the recovery start signal for variable has been input, the gaming machine characterized by capable of releasing the hold of the recovery period. 2. The gaming machine according to claim 1, wherein the recovery start suspending means can determine whether to suspend the recovery start by referring to the contents of the last storage. 3. A game control means capable of controlling a specific game state advantageous to a player on condition that a result of a predetermined game becomes a specific mode, wherein the recovery start holding means includes a final storage. 3. The gaming machine according to claim 2, wherein when the content is at least content indicating a specific gaming state, the start of recovery is suspended. 4. A start detecting means for detecting start in response to a predetermined winning, and a predetermined state for determining whether or not to enter a gaming state advantageous to the player in accordance with the start detection of (1). The start of the game is started, a predetermined number of start detections can be held, and the recovery start holding unit holds the recovery start when the final storage content indicates that at least the start detection number is held. 3. The gaming machine according to claim 2, wherein: 5. The display device according to claim 1, further comprising a display device for performing a predetermined notification to a player, wherein a predetermined screen is displayed on the display device during recovery start suspension. Gaming machine. 6. The gaming machine according to claim 5, wherein the predetermined screen display includes a display for instructing a player on a method of starting recovery. 7. The gaming machine according to claim 5, wherein the predetermined screen display includes a display for notifying a final storage content. 8. The gaming machine according to claim 1, wherein the recovery start signal is transmitted by a predetermined operation of the player. 9. The gaming machine according to claim 8, further comprising a touch sensor for detecting that the player has touched the gaming machine, and transmitting a recovery start signal in response to the detection of the touch sensor. 10. A shooting operation means operated by a player to fire a game ball, and a shooting ball detector for detecting a game ball fired in response to a predetermined operation of the shooting operation means by the player. The gaming machine according to claim 8, further comprising: transmitting a recovery start signal in response to detection of the launching ball detector.