JP4347378B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine, a coin gaming machine, or a slot machine in which a game is performed according to a player's operation, and particularly, a game is performed according to a player's operation in a gaming area on a gaming board. It relates to gaming machines.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Further, a variable display unit capable of changing the display state is provided, and is configured to give a predetermined game value to the player when the display result of the variable display unit becomes a predetermined specific display mode There is.

  Note that the game value is the right that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous for a player who is likely to win a ball, or the advantageous state for a player. Or a condition that a condition for giving out premium game media is easily established.

  In a pachinko game machine, the combination of a specific display mode with a predetermined display result of a variable display unit that displays special symbols is usually referred to as “big hit”. When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state in which a hit ball is easy to win. And in each open period, if there is a prize for a predetermined number (for example, 10) of the big prize opening, the big prize opening is closed. And the number of times the special winning opening is opened is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and even if the number of winnings does not reach a predetermined number, the big winning opening is closed when the opening time elapses. Further, when a predetermined condition (for example, winning in the V zone provided in the big prize opening) is not established at the time when the big prize opening is closed, the big hit gaming state is ended.

  In addition, among the combinations of display modes other than the “big hit” combination, the variable display in which the display result has already been derived and displayed at the stage where some of the display results of the plurality of variable display units have not yet been derived and displayed. A state in which the display mode of the part satisfies a display condition that is a combination of specific display modes is referred to as “reach”. Then, if the display result of the identification information variably displayed on the variable display portion does not satisfy the condition of “reach”, it becomes “missing”, and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

  The game progress in the gaming machine is controlled by game control means such as a microcomputer. The identification information, character image, and background image displayed on the variable display device are controlled by display control means that operates in accordance with display control command data from the game control means. In general, the identification information, character image, and background image displayed on the variable display device are a display control microcomputer and a video display processor that generates image data in accordance with instructions from the microcomputer and transfers the image data to the variable display device side ( VDP), the program capacity of the display control microcomputer is large.

  Therefore, it is impossible to control identification information and the like displayed on the variable display device by the microcomputer of the game control means having a limited program capacity, and the display control microcomputer (separate from the microcomputer of the game control means) Display control means) is used. Therefore, the game control means for controlling the progress of the game needs to transmit a display control command to the display control means.

  In such a gaming machine, a speaker is provided on the game board, and various sound effects are emitted from the speaker as the game progresses in order to enhance the gaming effect. In addition, light emitters such as lamps and LEDs are provided on the game board, and these light emitters are turned on and off as the game progresses in order to enhance the gaming effect. In general, sound control for generating sound effects and lamp lighting / extinguishing timing control are performed by game control means for controlling the progress of the game. Therefore, it is necessary for the game control means to transmit a command to the sound control means or the lamp control means for actually generating sound or driving the lamp / LED.

  Also, a player generally borrows game media through a gaming machine. In that case, a gaming medium lending mechanism is provided in the gaming machine. Since the progress of the game is controlled by the game control means mounted on the main board, the number of winning balls based on the winning is determined by the game control means and transmitted to the payout control board.

  As described above, various control means are mounted on the gaming machine in addition to the game control means. Then, the game control means for controlling the progress of the game transmits each command indicating an operation instruction according to the game situation to each control means mounted on each control board. Hereinafter, each control means mounted on each control board other than the game control board may be referred to as an electrical component control means. A board other than the game control board may be referred to as an electrical component control board.

  When the power supply to the gaming machine is stopped, the drive voltage (for example, + 5V) for driving each control means gradually decreases. Each control means generally includes a microcomputer, but the voltage at which each control means becomes inoperable is different due to variations in elements. When a command is transmitted from the game control means to each control means, it is configured not to take a response from each control means from the viewpoint of preventing illegal signal input to the game control board on which the game control means is mounted. Yes. Then, for example, even if the game control means sends a command immediately before the power supply to the gaming machine stops, the control means on the command receiving side may already be inoperable. In this case, the game control means recognizes that the command has been sent, but the control means on the side that receives the command cannot receive the command. In that case, in general, there is often no problem because the driving voltage is lost and the game control means and other control means do not operate and are reset when the power is turned on again.

  However, when an unexpected power failure such as a power failure occurs, the necessary data is saved in the power backup RAM, and the saved data is restored when the power is restored to resume the game. Is a problem. For example, the payout control means stores the number of prize balls instructed from the game control means in the backup RAM, and the prize ball payout is continued based on the number of prize balls saved when the power is restored after the power is turned off. If the game control means has issued a predetermined number of prize ball payout instructions immediately before the power is turned off, the payout control means may not have received the instruction. In that case, even if the payout control means resumes paying out the prize balls based on the memory after the power supply is restored, the number of prize balls paid out is smaller than the number of prize balls to be originally paid out. That is, a disadvantage is given to the player.

  Further, not only the payout control means, but also with respect to other control means, if a situation occurs in which the control means cannot receive a command even though the game control means sends a command immediately before the power is turned off, After recovery, the control state may fall into an undesirable state. For example, there is a possibility that a display state or utterance state that should not appear originally occurs after the power supply is restored. Further, even when the power is turned on, the command may be missed if the other control means is not ready for reception even though the game control means has sent the command.

  Accordingly, an object of the present invention is to provide a gaming machine in which each control means can reliably receive a command from the game control means.

The gaming machine according to the present invention is a gaming machine that allows a player to play a predetermined game, and controls a game control microcomputer that controls the progress of the game , and commands based on commands from the game control microcomputer. A payout control microcomputer that performs payout control of game media used, a power supply monitoring means that monitors a predetermined potential power supply used in the game machine and outputs a detection signal when a detection condition is satisfied, and a power supply monitoring means detects the signal after a predetermined period of time has elapsed from the output to the, a non-operation signal output means for outputting a signal for the game control microcomputer and the payout control microcomputer inoperative, the game control microcomputer and the payout control microcomputer The contents immediately before the power supply is stopped by the backup power supply even when the power supply is stopped A RAM capable of holding at least a predetermined time is provided, and the game control microcomputer executes an initialization process only at the start of power supply, and after executing the initialization process, a first random number used for game control A game control process that is activated by an internal timer interrupt of the game control microcomputer when the update process for updating the counter is repeatedly executed, and is different from the first random number counter. A process of updating a counter of a second random number for determining whether or not to enter a specific gaming state advantageous to the player is executed, and the game control microcomputer and the payout control microcomputer are provided with power supply monitoring means. Based on the detection signal from, information necessary for restoring the control state within a predetermined period is stored in the RAM The game control microcomputer sets a flag indicating the execution of the power supply stop process in the RAM in the power supply stop process, and the game control microcomputer and the payout control microcomputer. Executes a return process for restoring the control state based on the information stored in the RAM when the power supply is restored, and the game control microcomputer performs the return process on the condition that the flag is stored in the RAM. The game control microcomputer executes the command transmission process in the power supply stop process, and the payout control microcomputer does not perform the command reception process in the power supply stop process, and detects the detection signal to the game control microcomputer. Detection condition and output control signal to the payout control microcomputer By making the detection condition to be output the same detection condition, the power supply monitoring means outputs a detection signal to the game control microcomputer and the payout control microcomputer at the same timing .

According to the present invention, the gaming machine, the gaming control microcomputer does not perform the command transmission process in the power supply stop process, the payout control microcomputer does not perform the command reception process in the power supply stop process, By setting the detection condition for outputting the detection signal to the game control microcomputer and the detection condition for outputting the detection signal to the payout control microcomputer as the same detection condition, the power supply monitoring means can be used for the game control microcomputer. Since the detection signal is output to the payout control microcomputer at the same timing, there is a disadvantage that the payout control microcomputer does not receive the command sent out by the game control microcomputer immediately before the power is turned off. rather, the payout control microcomputer Yu There is an effect that it is possible to reliably receive the command from the control microcomputer.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. 1 is a front view of the pachinko gaming machine 1 as seen from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the mechanism panel of the pachinko gaming machine 1 as seen from the back. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine. It can also be applied to image-type gaming machines and slot machines.

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray 3. Below the hitting ball supply tray 3, there are provided an extra ball receiving tray 4 for storing prize balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing the hitting ball. A game board 6 is detachably attached to the rear side of the glass door frame 2. A game area 7 is provided in front of the game board 6.

  Near the center of the game area 7, there is provided a variable display device 8 including a variable display unit 9 for variably displaying a plurality of types of symbols and a variable display 10 using 7 segment LEDs. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. A passing gate 11 for guiding a hit ball is provided on the side of the variable display device 8. The hit ball that has passed through the passing gate 11 is guided to the start winning opening 14 through the ball outlet 13. In the passage between the passage gate 11 and the ball exit 13, there is a gate switch 12 that detects a hit ball that has passed through the passage gate 11. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 17. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An open / close plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. In this embodiment, the opening / closing plate 20 is a means for opening and closing the special winning opening. Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V zone) is detected by the V count switch 22. A winning ball from the opening / closing plate 20 is detected by the count switch 23. At the bottom of the variable display device 8, a start winning memory display 18 having four display units for displaying the number of winning balls that have entered the start winning opening 14 is provided. In this example, with the upper limit being four, each time there is a start prize, the start prize storage display 18 increases the number of lit display units one by one. Then, each time the variable display of the variable display unit 9 is started, the lit display unit is reduced by one.

  The game board 6 is provided with a plurality of winning openings 19, 24, and winning of the game balls to the winning openings 19, 24 is detected by winning opening switches 19a, 24a. Decorative lamps 25 blinking during the game are provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a hit ball that has not won a prize is provided below. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a game effect LED 28a and game effect lamps 28b and 28c are provided.

  In this example, a prize ball lamp 51 that is lit when the prize ball is paid out is provided in the vicinity of one speaker 27, and a ball break lamp 52 that is lit when the supply ball is cut is provided in the vicinity of the other speaker 27. Is provided. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and enables lending of a ball by inserting a prepaid card.

  The card unit 50 has a usable indicator lamp 151 indicating whether or not it is in a usable state, and when the remaining amount information recorded in the card has a fraction (a number less than 100 yen), the fraction is indicated as a hitting tray. 3, a fraction display switch 152 for displaying on a frequency display LED provided in the vicinity of 3, a connecting table direction indicator 153 indicating which side of the pachinko gaming machine 1 corresponds to the card unit 50, in the card unit 50 Check the card insertion indicator lamp 154 indicating that a card is inserted, the card insertion slot 155 into which a card as a recording medium is inserted, and the mechanism of the card reader / writer provided on the back of the card insertion slot 155. In some cases, a card unit lock 156 is provided for releasing the card unit 50.

  The hit ball fired from the hit ball launching device enters the game area 7 through the hit ball rail, and then descends the game area 7. When the hit ball is detected by the gate switch 12 through the passing gate 11, the display number of the variable display 10 changes continuously. Further, when the hit ball enters the start winning opening 14 and is detected by the start opening switch 17, the symbol in the variable display portion 9 starts to rotate if the variation of the symbol can be started. If it is not in a state where the change of the symbol can be started, the start winning memory is increased by 1.

  The rotation of the image in the variable display unit 9 stops when a certain time has elapsed. If the combination of images at the time of the stop is a combination of jackpot symbols, the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of hit balls wins. When the hit ball enters the specific winning area while the opening / closing plate 20 is opened and is detected by the V count switch 22, a right to continue is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of images in the variable display section 9 at the time of stop is a combination of jackpot symbols with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in a high probability state. Further, when the stop symbol on the variable display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol in the variable display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG.
On the back surface of the variable display device 8, as shown in FIG. 2, a prize ball tank 38 is provided on the top of the mechanism plate 36, and the prize ball is placed from above in a state where the pachinko gaming machine 1 is installed on the gaming machine installation island. It is supplied to the prize ball tank 38. The prize balls in the prize ball tank 38 pass through the guide rod 39 and reach the ball dispensing device.

  The mechanism plate 36 includes a variable display control unit 29 for controlling the variable display unit 9 via the relay board 30, a game control board (main board) 31 covered with a board case 32 and mounted with a game control microcomputer, etc. A prize ball control board (payout control board) on which a relay board 33 for relaying signals between the variable display control unit 29 and the main board 31, a prize ball control microcomputer for performing prize ball payout control, and the like are mounted. 37) is installed. Further, at the lower part of the mechanism plate 36, a hitting ball launching device 34 that launches a hitting ball into the game area 7 using the rotational force of the motor, game effect lamps / LEDs 28a, 28b, 28c, a prize ball lamp 51, and a ball break lamp A lamp control board 35 for sending a signal to 52 is installed.

  FIG. 3 is a rear view of the mechanism board of the pachinko gaming machine 1 as seen from the back. As shown in FIG. 3, the ball passing through the guide rod 39 passes through the ball break detectors 187a and 187b and reaches the ball dispensing device 97 via the ball supply rods 186a and 186b. The prize balls paid out from the ball payout device 97 are supplied to the hit ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the connection port 45. A surplus ball passage 46 communicating with the surplus ball receiving tray 4 provided on the front surface of the pachinko gaming machine 1 is formed on the side of the communication port 45. A lot of premium balls based on the winnings are paid out and the hitting ball supply tray 3 becomes full. Finally, when the premium balls are paid out after the premium balls reach the contact port 45, the premium balls pass through the surplus ball passage 46 and surplus. It is guided to the ball receiving tray 4. When the prize ball is further paid out, the sensing lever 47 presses the full tank switch 48 and the full tank switch 48 is turned on. In this state, the rotation of the stepping motor in the ball dispensing device 97 is stopped, the operation of the ball dispensing device 97 is stopped, and the driving of the ball striking device 34 is stopped as necessary.

  In order to perform prize ball payout control, signals from the prize opening switches 19 a and 24 a, the start opening switch 17 and the V count switch 22 are sent to the main board 31. The CPU 56 of the main board 31 knows that a winning corresponding to six prize ball payout has occurred when the start port switch 17 is turned on. Further, when the count switch 23 is turned on, it is known that a winning corresponding to 15 prize ball payouts has occurred. Then, when the winning opening switch is turned on, it is known that a winning corresponding to ten winning ball payouts has occurred. In this embodiment, for example, a game ball won in the winning opening 24 is detected by a winning opening switch 24 a provided in a winning ball flow path from the winning opening 24 and won in the winning opening 19. Is detected by a winning port switch 19a provided in a winning ball flow path from the winning port 19.

  FIG. 4 is a block diagram illustrating an example of a circuit configuration in the main board 31. FIG. 4 also shows a prize ball control board 37, a lamp control board 35, a sound control board 70, a launch control board 91, and a display control board 80. The main circuit board 31 includes a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 12, a start port switch 17, a V count switch 22, a count switch 23, a full switch 48, and ball break switches 187a and 187b ( Hereinafter, it may be expressed as a ball cut switch 187.) and a switch circuit 58 for supplying a signal from the winning opening switch 19a, 24a to the basic circuit 53, and a solenoid 16 and an opening / closing plate 20 for opening and closing the variable winning ball apparatus 15. A solenoid circuit 59 that drives the solenoid 21 that opens and closes in accordance with a command from the basic circuit 53, a lamp that lights and extinguishes the start-up memory display 18, and that drives the variable display 10 and the decoration lamp 25 by 7-segment LEDs. An LED circuit 60 is provided.

  Further, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the effective starting information indicating the number of starting winning balls used for starting the image display of the variable display unit 9, and the fact that the probability variation has occurred. An information output circuit 64 is provided for outputting the probability variation information and the like to a host computer such as a hall management computer.

  The basic circuit 53 includes a ROM 54 that stores a game control program and the like, a RAM 55 that is used as a work memory, a CPU 56 that performs a control operation according to a control program, and an I / O port unit 57. In this embodiment, the ROM 54 and RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the RAM 55, and the ROM 54 and the I / O port unit 57 may be externally attached.

Further, the main board 31 includes an initial reset circuit 65 for resetting the basic circuit 53 when power is turned on, and an address signal supplied from the basic circuit 53 to decode any I / O port 57. An address decode circuit 67 for outputting a signal for selecting the / O port is provided.
Note that there is also switch information input to the main board 31 from the ball dispensing device 97, but these are omitted in FIG.

  A ball hitting device for hitting and launching a game ball is driven by a drive motor 94 controlled by a circuit on the launch control board 91. Then, the driving force of the drive motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

  FIG. 5 is a block diagram showing a circuit configuration in the display control board 80 together with a CRT 82 which is an example of realization of the variable display unit 9, output ports (ports A and B) 571 and 572 of the main board 31, and the output buffer circuit 63. It is. The output port 571 outputs 8-bit data, and the output port 572 outputs a 1-bit strobe signal (INT signal).

  The display control CPU 101 operates in accordance with a program stored in the control data ROM 102. When a strobe signal is input from the main board 31 via the noise filter 107 and the input buffer circuit 105, the display control CPU 101 performs display control via the input buffer circuit 105. Receive commands. As the input buffer circuit 105, for example, 74HC244, which is a general-purpose IC, can be used. When the display control CPU 101 does not have an I / O port, an I / O port is provided between the input buffer circuit 105 and the display control CPU 101.

  Then, the display control CPU 101 performs display control of the screen displayed on the CRT 82 in accordance with the received display control command. Specifically, a command corresponding to the display control command is given to the VDP 103. The VDP 103 reads out necessary data from the character ROM 86. The VDP 103 generates image data to be displayed on the CRT 82 according to the input data, and stores the image data in the VRAM 87. The image data in the VRAM 87 is converted into R, G, and B signals, converted into analog signals by the DA conversion circuit 104, and output to the CRT 82.

  5 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, animal, or an image made up of characters, figures, symbols, or the like displayed on the CRT 82. In this embodiment, the display control CPU 101 is a one-chip microcomputer and incorporates at least a RAM.

  The input buffer circuit 105 can pass signals only in the direction from the main board 31 to the display control board 80. Therefore, there is no room for signals to be transmitted from the display control board 80 side to the main board 31 side. Even if the tampering is added to the circuit in the display control board 80, the signal output by the tampering is not transmitted to the main board 31 side. The outputs of the output ports 571 and 572 may be output to the display control board 80 as they are. However, by providing the output buffer circuit 63 capable of transmitting signals only in one direction, the main board 31 to the display control board 80 can be provided. Unidirectional signal transmission can be made more reliable. In addition, for example, a three-terminal capacitor or a ferrite bead is used as the noise filter 107 that cuts off the high-frequency signal. However, even if noise is added to the display control command between the substrates due to the presence of the noise filter 107, the influence is removed. Is done.

  FIG. 6 is a block diagram showing a configuration example of the voice control command signal transmission portion of the main board 31 and the voice control board 70. In this embodiment, a voice control command for instructing voice output from the speaker 27 provided outside the gaming area 7 is output from the main board 31 to the voice control board 70 as the game progresses.

  As shown in FIG. 6, the voice control command is output from the output ports (output ports C and D) 573 and 574 of the I / O port unit 57 in the basic circuit 53. The output port 573 outputs 8-bit data, and the output port 574 outputs a 1-bit strobe signal (INT signal). In the sound control board 70, each signal from the main board 31 is input to the sound control CPU 701 via the input buffer circuit 705. When the audio control CPU 701 does not have an I / O port, an I / O port is provided between the input buffer circuit 705 and the audio control CPU 701. In this embodiment, the voice control CPU 701 is a one-chip microcomputer and incorporates at least a RAM.

  Then, for example, a voice synthesis circuit 702 using a digital signal processor generates voice and sound effects according to instructions from the voice control CPU 701 and outputs them to the volume switching circuit 703. The volume switching circuit 703 sets the output level of the audio control CPU 701 to a level corresponding to the set volume and outputs the level to the volume amplification circuit 704. The volume amplifier circuit 704 outputs the amplified audio signal to the speaker 27.

  As the input buffer circuit 705, for example, a general-purpose CMOS-IC 74HC244 is used. The enable terminal of 74HC244 is always given a low level (GND level). Therefore, the output level of each buffer is fixed to the input level, that is, the signal level from the main board 31. Therefore, there is no room for signals to be transmitted from the voice control board 70 side to the main board 31 side. Therefore, even if unauthorized modification is added to the circuit in the voice control board 70, a signal output by the unauthorized modification is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuit 705.

  In addition, a buffer circuit 67 is provided outside the output ports 574 and 575 in the main board 31. As the buffer circuit 67, for example, a general-purpose CMOS-IC 74HC244 is used. The enable terminal is always given a low level (GND level). According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, it is possible to further reliably eliminate a signal line from which a signal may be given from the voice control board 70 to the main board 31. be able to.

  FIG. 7 is a block diagram showing signal transmission / reception portions in the main board 31 and the lamp control board 35. In this embodiment, a lamp control command for turning on / off the game effect LED 28a and game effect lamps 28b, 28c provided on the outside of the game area 7 and turning on / off the prize ball lamp 51 and the ball-out lamp 52 is shown. Is output.

  As shown in FIG. 7, the lamp control command related to the lamp control is output from the output ports (output ports E and F) 575 and 576 of the I / O port unit 57 in the basic circuit 53. The output port 575 outputs 8-bit data, and the output port 576 outputs a 1-bit strobe signal (INT signal). In the lamp control board 35, a control command from the main board 31 is input to the lamp control CPU 351 through the input buffer circuit 355. When the lamp control CPU 351 does not include an I / O port, an I / O port is provided between the input buffer circuit 355 and the lamp control CPU 351. In this embodiment, the lamp control CPU 351 is a one-chip microcomputer and has at least a built-in RAM.

  In the lamp control board 35, the lamp control CPU 351 applies the game effect LED 28a and the game effect lamps 28b and 28c to the game effect LED 28a and the game effect lamps 28b and 28c according to the turn-on / off pattern of the game effect LED 28a and the game effect lamps 28b and 28c. On / off signal is output. The on / off signal is output to the game effect LED 28a and the game effect lamps 28b and 28c. The on / off pattern is stored in the built-in ROM or external ROM of the lamp control CPU 351.

  On the main board 31, the CPU 56 outputs a control command for instructing the lighting of the award ball lamp at the time of the award ball, and instructs the lighting of the out-of-ball lamp when the ball-out detection sensor installed in the game ball supply path on the back of the game board is turned on. Output control commands. In the lamp control board 35, each control command is input to the lamp control CPU 351 via the input buffer circuit 355. The lamp control CPU 351 turns on / off the prize ball lamp 51 and the ball-out lamp 52 in accordance with these control commands.

  As the input buffer circuit 355, for example, a general-purpose CMOS-IC 74HC244 is used. The enable terminal of 74HC244 is always given a low level (GND level). Therefore, the output level of each buffer is fixed to the input level, that is, the signal level from the main board 31. Therefore, there is no room for signals to be transmitted from the lamp control board 35 side to the main board 31 side. Even if unauthorized modification is added to the circuit in the lamp control board 35, a signal output by the unauthorized modification is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuit 355.

  In the configuration shown in FIG. 7, it is possible to eliminate a signal line that may give a signal from the lamp control board 35 to the main board 31. That is, the unidirectionality of the signal from the main board 31 to the lamp control board 35 is ensured, and the possibility that the lamp control board 35 influences the game control in the main board 31 is eliminated. As a result, for example, even if the lamp control board 35 is modified so as to give an illegal signal for causing a big hit to the basic circuit 53 of the main board 31, the illegal signal cannot be transmitted to the main board 31.

  Further, a buffer circuit 62 is provided outside the output ports 575 and 576 in the main board 31. As the buffer circuit 62, for example, 74HC244 which is a general-purpose CMOS-IC is used. The enable terminal is always given a low level (GND level). According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line that can give a signal to the main board 31 from the lamp control board 35 is more reliably provided. Can be eliminated.

  In FIG. 7, a signal instructing to turn on or off the game effect LED 28a, the game effect lamps 28b and 28c, the prize ball lamp 51 and the ball-out lamp 52 is output from the built-in output port of the lamp control CPU 351. Actually, a driver circuit is inserted between the output port and each lamp / LED.

  FIG. 8 is a block diagram showing components related to the prize ball, such as components of the prize ball control board 37 and the ball payout device 97. As shown in FIG. 8, the detection signal from the full switch 48 is input to the I / O port 57 of the main board 31 via the relay board 71. The full tank switch 48 is a switch for detecting a full tank of the surplus ball receiving tray 4. The prize ball control CPU 371 mounted on the prize ball control board 37 constitutes a payout control means for performing a game ball payout control based on winning and a game ball payout control based on a ball lending request.

  A detection signal from the ball break switch 187 (187a, 187b) is input to the I / O port 57 of the main board 31 via the relay board 72 and the relay board 71. The ball break detection switch 167 is a switch for detecting the shortage of replenishment balls in the prize ball tank 38, and the ball break switch 187 is a switch for detecting the presence or absence of a prize ball in the prize ball passage.

  The CPU 56 of the main board 31 instructs the ball lending prohibition when the detection signal from the ball break switch 187 indicates a ball shortage state or when the detection signal from the full tank switch 48 indicates a full tank state. Send out a prize ball control command. When receiving a prize ball control command for instructing prohibition of ball rental, the prize ball control CPU 371 of the prize ball control board 37 stops the ball rental process.

  Further, a detection signal from the prize ball count switch 301 </ b> A is also input to the I / O port 57 of the main board 31 via the relay board 72 and the relay board 71. Further, a drive signal from the I / O port 57 of the main board 31 to the winning ball discharge solenoid 127 is supplied to the winning ball discharge solenoid 127 via the relay board 71. The prize ball count switch 301A is provided in the prize ball mechanism portion of the ball dispensing device 97 and detects the prize ball actually paid out.

  When there is a prize, a prize ball control command indicating the number of prize balls is input to the prize ball control board 37 from the output ports (ports G and H) 577 and 578 of the main board 31. The output port 577 outputs 8-bit data, and the output port 578 outputs a 1-bit strobe signal (INT signal). A prize ball control command indicating the number of prize balls is input to the I / O port 372a via the input buffer circuit 373. The prize ball control CPU 371 inputs a prize ball control command via the I / O port 372a, and drives the ball payout device 97 in accordance with the prize ball control command to perform a prize ball payout. In this embodiment, the winning ball control CPU 371 is a one-chip microcomputer and incorporates at least a RAM.

  Each buffer in the input buffer circuit 373 can pass a signal only in the direction from the main board 31 toward the prize ball control board 37. Therefore, there is no room for signals to be transmitted from the prize ball control board 37 side to the main board 31 side. Even if unauthorized modification is added to the circuit in the prize ball control board 37, a signal output by the unauthorized modification is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuit 373.

  In addition, a buffer circuit 68 is provided outside the output ports 577 and 578 for outputting a prize ball control command on the main board 31. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line that can give a signal from the prize ball control board 37 to the main board 31 is more surely provided. Can be eliminated.

  Further, the prize ball control CPU 371 outputs a ball lending number signal indicating the number of lending balls to the terminal board 160 and a buzzer driving signal to the buzzer board 75 via the output port 372g. A buzzer is mounted on the buzzer substrate 75. Further, an error signal is output to the error display LED 374 via the output port 372e.

  Further, the detection signal of the prize ball count switch 301A and the detection signal of the ball rental count switch 301B are input to the input port 372b of the prize ball control board 37 via the relay board 72. The ball lending count switch 301B detects a game ball actually lent. A drive signal from the prize ball control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the prize ball mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72.

  The card unit 50 is equipped with a card unit control microcomputer. Further, the card unit 50 is provided with a fraction display switch 152, a connecting table direction indicator 153, a card insertion display lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected with a frequency display LED, a ball lending switch, and a return switch provided in the vicinity of the hitting ball supply tray 3.

  A ball lending switch signal and a return switch signal are given from the balance display board 74 to the card unit 50 via the prize ball control board 37 in accordance with the player's operation. Further, a card balance display signal indicating a balance of the prepaid card and a ball lending possible display signal are given to the balance display board 74 from the card unit 50 via the prize ball control board 37. Between the card unit 50 and the prize ball control board 37, a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal (PRDY signal) are I / O. Exchanged via the O port 372f.

  When the power of the pachinko gaming machine 1 is turned on, the prize ball control CPU 371 of the prize ball control board 37 outputs a PRDY signal to the card unit 50. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the prize ball control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the prize ball control board 37. Then, the prize ball control CPU 371 of the prize ball control board 37 drives the payout motor 289 to pay out a predetermined number of lending balls to the player. When the payout is completed, the prize ball control CPU 371 outputs an EXS signal to the card unit 50.

  As described above, all signals from the card unit 50 are input to the prize ball control board 37. Accordingly, with respect to the ball lending control, no signal is input from the card unit 50 to the main board 31, and there is no room for an illegal signal input from the card unit 50 side to the basic circuit 53 of the main board 31. The main board 31 and the prize ball control board 37 are mounted with driver circuits for driving solenoids, motors and lamps, but these circuits are omitted in FIG.

  In this embodiment, at least a part of the RAM is backed up at least on the main board 31. That is, even if the power supply to the gaming machine is stopped, the data in the backup RAM area is saved. Further, the display control CPU 101, the sound control CPU 701, the lamp control CPU 351, and the prize ball control CPU 371 may be configured such that a part of the RAM is backed up.

  FIG. 9 is a block diagram showing a configuration around the CPU in the main board 31, the display control board 80, the sound control board 70, the lamp control board 35 and the prize ball control board 37. In this example, in the main board 31 and the prize ball control CPU 371, a part of the CPU built-in RAM is backed up by connecting a backup power supply to the backup terminal.

  As shown in FIG. 9, on the main board 31, the power monitoring IC 901 introduces a + 30V voltage, and detects the occurrence of a power interruption by monitoring the + 30V voltage. Specifically, when the + 30V voltage becomes equal to or lower than a predetermined value (for example, + 22V), an interrupt signal is given to the CPU 56 in order to notify that the power is cut off. In the CPU 56, this interrupt is input to a non-maskable interrupt (INT) terminal. A signal input to the NMI terminal is also input to an input port built in the CPU 56.

  The predetermined value for the power monitoring IC 901 to detect the power interruption is lower than the normal voltage, but is a voltage that allows the CPU 56 to operate for a while. Further, since the power monitoring IC 901 is configured to monitor a voltage that is higher than the voltage required by the CPU 56 (in this example, +5 V) and immediately after being converted from AC to DC, the CPU 56 is necessary. The monitoring range can be expanded with respect to the voltage. Therefore, more precise monitoring can be performed. Further, when + 30V is used as the monitoring voltage, the voltage supplied to the various switches of the gaming machine is + 12V, so that it can be expected to prevent erroneous switch-on detection at the time of instantaneous power interruption. That is, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in the level before + 12V created after the creation of + 30V starts to drop. Therefore, when the voltage of the + 12V power supply decreases, the switch output becomes in the on state. However, if the power supply interruption is recognized by monitoring the + 30V power supply voltage that decreases faster than + 12V, the switch output becomes the power It is possible to enter a state of waiting for recovery and not detect switch output.

  In the prize ball control board 371, the power supply monitoring IC 931 introduces a + 30V voltage and monitors the + 30V voltage to detect the occurrence of a power interruption. Specifically, when the + 30V voltage becomes lower than a predetermined value (for example, + 22V) which is a voltage lower than the voltage at the time of detection of the power monitoring IC 901 described above, a prize ball control is performed in order to notify that a power interruption occurs. An interrupt signal is given to the CPU 371. In the winning ball control CPU 371, this interrupt is input to the non-maskable interrupt (INT) terminal. A signal input to the NMI terminal is also input to an input port built in the prize ball control CPU 371.

  In the configuration shown in FIG. 9, the output of the power monitoring IC is input to the NMI terminal of the CPU, but may be input to the maskable interrupt terminal (IRQ terminal). The output of the power monitoring IC is also input to the CPU input port, but it may be configured to be input only to the interrupt terminal. Further, the audio control board 70, the lamp control board 35, and the display control board 80 are also mounted with the same power supply monitoring ICs 901 and 931, and are configured to give signals to each CPU when the + 30V voltage becomes a predetermined value or less. May be.

  In the configuration shown in FIG. 9, the voltage of the + 30V power supply from which the power monitoring IC 901 outputs a signal is set to be the same as the voltage of the + 30V power supply from which the power monitoring IC 931 outputs a signal. . Further, ICs of the same type are used as the power monitoring ICs 901 and 931. Accordingly, when the power supply voltage decreases, an NMI interrupt is applied to the prize ball control CPU 371 of the prize ball control board 37 at the same timing as when the NMI interrupt is applied to the CPU 56 of the main board 31. As will be described later, since each CPU stops normal control in accordance with NMI, the game progress control stop condition and the payout control stop condition are the same for the game control means and the payout control means. .

  Therefore, the substantial NMI processing start timing when there is no timing shift due to variations in the power monitoring ICs 901 and 931 is the same between the CPU 56 of the main board 31 and the winning ball control CPU 371. Then, the CPU 56 of the main board 31 and the prize ball control CPU 371 interrupt the normal control process at substantially the same time and perform a predetermined process at the time of power-off (for example, for saving the RAM contents as a backup). Process).

  Accordingly, there is no inconvenience that the prize ball control command 371 sent out by the CPU 56 of the main board 31 is not received by the prize ball control CPU 371 immediately before the power is turned off. For example, when the prize ball control CPU 371 interrupts the normal control process early and starts a predetermined process when the power is turned off, the prize ball control command sent by the CPU 56 of the main board 31 immediately before the power is turned off. The winning ball control CPU 371 will not receive the signal. However, such an inconvenience does not occur in this embodiment.

  Further, an initial reset circuit 65 including a reset IC 651 is mounted on the main board 31. When the initial reset circuit 65 detects that + 5V has risen when the power is turned on, the initial reset circuit 65 outputs a signal indicating reset release after a predetermined time (a time determined by the external resistance value and the capacitor capacity). A similar initial reset circuit is also mounted on the display control board 80, the sound control board 70, the lamp control board 35, and the prize ball control board 37. However, in FIG. 9, only the initial reset circuit including the reset IC 380 in the winning ball control board 37 is shown.

  In the configuration shown in FIG. 9, the resistance value and the capacitance value of the initial reset circuit 65 of the main board 31 are the resistance value and the resistance value of the capacitor and the external resistance of the reset IC 380 on the other control board. Equal to capacity. That is, it has the same configuration. Therefore, when the gaming machine is powered on, the reset signals from the reset ICs 651 and 380 rise substantially simultaneously.

  In the main board 31, the output of the initial reset circuit 65 is input to the reset terminal of the CPU 56 via the delay circuit 655. Therefore, when the power is turned on, the CPU 56 of the main board 31 rises later than the CPUs of all other boards. The output of the delay circuit 655 is input to the reset terminal of the output port 570 via the two gate circuits 656 and 657. The output port 570 is a port for sending a command to another board. When the reset signal indicates a reset release state, the information output state is enabled. The output port 570 corresponds to the output ports 571 to 578 shown in FIGS.

  Since the CPU 56 of the main board 31 rises later than the CPUs of all other boards, the CPU 56 of the main board 31 is ready to receive a command after completing the rise of the CPU on the other boards. become. Therefore, even if the command is sent from the game control means to the other electrical component control means immediately after the power is turned on, the command is reliably received by the other control means.

  In the configuration shown in FIG. 9, power supply monitoring means for monitoring power interruption is mounted on each board. For example, power supply monitoring means is mounted on a power supply board described later, and voltage is applied to each board from there. A signal indicating a decrease may be supplied.

  FIG. 10 is a block diagram illustrating a configuration example of the power supply substrate 910. The power supply board 910 is installed independently of control boards such as the main board 31, the display control board 80, the voice control board 70, the lamp control board 35, and the prize ball control board 37, and each control board and mechanical parts in the gaming machine are installed. Generate the voltage to be used. In this example, AC24V, DC + 30V, DC + 21V, DC + 12V and DC + 5V are generated. A capacitor 916 serving as a backup power supply is charged from a line of power supply for driving DC + 5V, that is, an IC or the like on each substrate.

  The transformer 911 converts AC voltage from the AC power source into 24V. The AC 24V voltage is output to the connector 915. The rectifier circuit 912 also generates a DC voltage of +30 V from AC 24 V and outputs it to the DC-DC converter 913 and the connector 915. The DC-DC converter 913 generates + 21V, + 12V, and + 5V and outputs them to the connector 915. The connector 915 is connected to, for example, a relay board, and power of a voltage necessary for each control board and mechanism component is supplied from the relay board.

  The + 5V line from the DC-DC converter 913 branches to form a backup + 5V line. A large-capacitance capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 serves as a backup power source for the backup RAM area in each control board when the power supply to the gaming machine is cut off. Further, a backflow preventing diode 917 is inserted between the + 5V line and the backup + 5V line.

  A battery that can be charged from a + 5V power supply may be used as the backup power supply. In the case of using a battery, a rechargeable battery is used in which the capacity disappears when a state in which no power is supplied from the +5 V power source continues for a predetermined time.

  A second power supply monitoring circuit may be mounted on the main board and the electrical component control board. For example, the second power supply monitoring circuit monitors the + 30V power supply voltage, which is the same as the power supply voltage monitored by the first power supply monitoring circuit (power supply monitoring ICs 901 and 931), and when the voltage value becomes a predetermined value or less. A low level voltage drop signal is generated. For example, the detection voltage of the first power supply monitoring circuit (voltage that outputs a voltage drop signal) is + 22V, and the detection voltage of the second power supply monitoring circuit is + 9V.

  Further, the voltage drop signal from the second power supply monitoring circuit is logically summed with the initial reset signals from the reset ICs 651 and 380 and then input to the reset terminal of the CPU. Therefore, the CPU enters a reset state (non-operating state) when the initial reset signal is low level or when the voltage drop signal from the second power supply monitoring circuit is low level.

  In such a configuration, the CPU is system reset after the CPU performs a predetermined power supply stop process according to the detection signal from the first power supply monitoring circuit. Therefore, the CPU is reset in a voltage unstable state when the power supply voltage is lowered, and the risk of CPU runaway is avoided. Since the same voltage is monitored, the difference between the timing at which the first voltage monitoring circuit outputs the voltage drop signal and the timing at which the second voltage monitoring circuit outputs the voltage drop signal is reliably set to a desired predetermined period. can do. The desired predetermined period is a period from when the power supply stop process is started in response to the voltage drop signal from the first power supply monitoring circuit until the power supply stop process is reliably completed.

Next, the operation of the gaming machine will be described.
When power is turned on to the gaming machine, the capacitor is charged through the resistor in the initial reset circuit 65 of the main board 31 shown in FIG. Therefore, the potential of the capacitor increases. When the potential of the capacitor exceeds a predetermined value, the reset IC 651 changes the output level from the low level to the high level as shown in FIG. The delay circuit 655 delays the output of the reset IC 651 and supplies it to the CPU 56 as a reset signal. Therefore, as shown in FIG. 11, a low level reset signal is given to the CPU 56 until a time later than the time when the output signal of the initial reset circuit 65 rises, and then the reset signal rises to a high level. That is, the reset of the CPU 56 is released at that time.

  Note that the delay amount in the delay circuit 655 is set, for example, such that a command is not sent from the game control means before the CPU in each control board completes the execution of the initialization program.

  Since each electrical component control board other than the main board 31 is not provided with a delay circuit, the reset signal input to each CPU rises early. That is, each CPU is in an operable state earlier than the CPU 56 of the main board 31. Therefore, there is no situation where each electrical component control means cannot receive the command sent by the CPU 56 of the main board 31 immediately after the gaming machine is turned on.

  FIG. 12 is a flowchart showing the game control process of the CPU 56 in the main board 31. 12A shows the main process executed by the CPU 56, and FIG. 12B shows the interrupt process. When the power-on reset is released, the CPU 56 first sets the built-in clock monitor register to the clock monitor enable state in order to enable the clock monitor control (step S1). The clock monitor control is a control that automatically generates a reset within the CPU 56 when a drop or stop of the input clock signal is detected. Next, the CPU 56 performs initialization processing (step S2). In the initialization process, a timer setting process is performed so that a timer interrupt is generated after a predetermined period (for example, after 2 ms). Thereafter, the process of updating the display random number such as a random number for determining the stop symbol type is repeatedly executed (step S17).

  The process shown in FIG. 12B is started by a timer interrupt inside the CPU 56. In the interrupt process, the CPU 56 first performs a timer setting process so that a timer interrupt is again applied after a predetermined period (for example, after 2 ms) (step S20).

  Next, after performing a process of setting a display control command sent to the display control board 80 in a predetermined area of the RAM 55 (display control data setting process: step S4), a process of outputting a display control command is performed (display) Control data output process: Step S5).

  Next, a process of outputting the contents of the storage area for various output data to each output port is performed (data output process: step S6). Further, an output data setting process is performed for setting output data such as jackpot information, start information, probability variation information, etc., output to the hall management computer in the storage area (step S8). Further, various abnormality diagnosis processes are performed by the self-diagnosis function provided in the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S9).

  Next, a process of updating each counter indicating each determination random number such as a big hit determination random number used for game control is performed (step S10).

  Next, the CPU 56 performs special symbol process processing (step S11). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Also, normal symbol process processing is performed (step S12). In the normal symbol process, the corresponding process is selected and executed in accordance with the normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Further, the CPU 56 inputs the states of the gate sensor 12, the start port sensor 17 and the count sensor 23 via the switch circuit 58, and determines whether or not each winning port or winning device has been won (switch processing: step S13). ). The CPU 56 further performs a process of updating a display random number such as a random number that determines the type of stop symbol (step S15).

  Further, the CPU 56 performs signal processing with the prize ball control board 37 (step S16). That is, when a predetermined condition is satisfied, a prize ball control command is output to the prize ball control board 37. The prize ball control CPU mounted on the prize ball control board 37 drives the ball payout device 97 according to the prize ball control command.

  In this embodiment, the game control process of steps S20 and S4 to S16 is executed in the 2 ms timer interrupt process. However, in the timer interrupt process, only a flag set indicating that a timer interrupt has occurred is performed. The flag may be monitored in the process, and the game control process may be executed when the flag is turned on.

  FIG. 13 is a flowchart showing the NMI interrupt processing of the CPU 56. As described above, when the power supply monitoring IC 901 detects a drop in the power supply voltage, an NMI interrupt is applied to the CPU 56. In this embodiment, the process shown in FIG. 13 corresponds to the power supply stop process.

  In the NMI interrupt process based on the power supply voltage drop, the CPU 56 first transfers the contents of the register to the backup RAM (step S31). Next, the NMI flag is set (step S32). The NMI flag is an internal flag indicating that an interrupt based on a power supply voltage drop has occurred. The NMI flag is set in the backup RAM area. Further, the CPU 56 disables RAM access (step S33), and continues to monitor the level of the input port into which the output of the power monitoring IC 901 is introduced (step S34). In this state, the power supply voltage further decreases, and finally the operation of the CPU 56 stops.

  However, when the level of the input port returns to the normal level, the CPU 56 enables the RAM access (step S35) and restores the register value stored in the backup RAM to the original register ( Step S36). Then, the NMI flag is reset (step S37), and the address where the NMI interrupt has occurred is restored.

  As described above, when the CPU 56 detects that the power supply voltage has returned to normal, the CPU 56 returns the state of the register to the address at which the NMI interrupt has been applied. Therefore, the control can be returned to the normal state even when noise is applied to the NMI line.

  However, the input port monitoring process in step S34 may not be performed. In this case, the RAM access is prohibited and then the program is put into a loop state or a HALT (halt) instruction is issued. When the input port monitoring process is not performed, it is not necessary to connect the NMI signal to the CPU input port in the configuration shown in FIG.

  As shown in FIG. 11, the time when the power monitoring IC 901 on the main board 31 detects a voltage drop of + 30V is the same as the time when the power monitoring IC 931 on the prize ball control board detects a voltage drop of + 30V. is there. That is, when the CPU 56 of the main board 31 starts the NMI process, the prize ball control CPU 371 also starts the NMI process. In the NMI processing of the CPU 56, since a loop is performed in step S34, new command transmission is not started. Therefore, the winning ball control CPU 371 does not fall into a situation in which a command from the main board 31 cannot be received when the power is turned off.

  FIG. 14 is a flowchart showing an example of the initialization process (step S2) in the main process shown in FIG. When power supply to the gaming machine is resumed, a reset signal is input from the initial reset circuit 65 to the CPU 56. The CPU 56 starts the main process in response to the initial reset signal. In the system check process, the CPU 56 first checks whether the NMI flag is set (step S42).

  If the NMI flag is not set, all the registers and the RAM area are cleared (step S46), and necessary initial values are set (step S47). Then, a power-on screen display command transmission request is set (step S48), the stack pointer is initialized (step S49), and the initialization process is terminated.

  When the power-on screen display command transmission request is set, for example, the power-on screen display command is transmitted to the display control board 80 by the display control data output process (step S5) shown in FIG. Upon receiving the power-on screen display command, the display control CPU 101 on the display control board 80 displays a predetermined screen on the variable display unit 9 as a screen to be displayed when the power is turned on.

  When it is confirmed in step S42 that the NMI flag is set, the CPU 56 restores the register value stored in the backup RAM to the original register (step S43). Then, the NMI flag is reset (step S44), and an error screen display command transmission request is set (step S45).

  When an error screen display command transmission request is set, for example, an error screen display command is transmitted to the display control board 80 by display control data output processing (step S5). When receiving the power-on screen display command, the display control CPU 101 on the display control board 80 displays a predetermined error screen on the variable display unit 9.

  Then, the CPU 56 jumps to the stack area value pointed to by the stack pointer as a jump destination. Since the stack pointer is one of the registers, it is restored to the value when the power is turned off by the processing in step S43. In this embodiment, the stack area is formed in the backup RAM area. That is, it is preserved even when the power is turned off. Therefore, the control state returns to the state when the power is cut off.

  For example, it is assumed that the display control CPU 101 on the display control board 80 is performing symbol variation display on the variable display unit 9 when the power is turned off. Then, when power is restored, the display control CPU 101 receives an error screen display command, and displays an error screen on the variable display unit 9. On the other hand, the CPU 56 of the main board 31 returns to the state when the power is cut off, that is, the gaming state during the special symbol change. Then, when the gaming state during the special symbol change ends, a command indicating symbol stop and a command indicating jackpot display are transmitted. At that stage, the display control CPU 101 can stop the error display and continue the subsequent display control.

  As described above, the CPU 56 performs data restoration processing if the NMI flag is set at the time of restoration, and performs normal initial setting processing (steps S46 and S47) if the NMI flag is not set. In the data restoration process, the saved register restoration process and the NMI flag reset process are performed. In addition, since the return to the return address stored in the stack area in the RAM area where the power is backed up, the game control means can return to the game state when the power is cut off.

  In this embodiment, when the power is turned on, whether to perform the initialization process or the state return process is determined depending on whether the NMI flag is set or not. However, the parity check data is determined in the NMI process when the power is turned off. It is calculated and stored in the RAM area that is backed up, and if the NMI flag is turned on when the power is turned on, a check based on the parity check data is performed, and if the data is saved correctly, the status recovery process is performed. May be.

  In the above embodiment, the resistance value and the capacitance value of the resistor and the capacitor in the initial reset circuit 65 of the main board 31 are the resistance value of the resistor and the capacitor externally attached to the reset IC 380 in the other electric component control board, and The capacity was set to an equal value. However, the capacity of the capacitor in the initial reset circuit 65 may be larger than the capacity of the capacitor in the other electrical component control board. In such a configuration, the rising point of the reset signal from the reset IC 651 of the initial reset circuit 65 is later than the rising point of the reset signal from the reset IC 380 in the other electrical component control board. Therefore, even if the delay circuit 655 is eliminated and the output of the initial reset circuit 65 is supplied to the CPU 56 as it is, the CPU 56 of the main board 31 can rise later than the CPUs of all other boards.

  The CPU 56 of the main board 31 may be configured to execute a predetermined security check program prior to the game control program after reset is released. If it takes a certain amount of time to execute the security check program, it is possible to expedite reset release of each CPU in another electrical component control board when the power is turned on by using that time. FIG. 15 is a block diagram showing another embodiment based on such a concept.

  In this case, the delay circuit 655 is not provided in the main board 31, and the output of the initial reset circuit 65 is directly connected to the reset input terminal of the CPU 56. Then, the resistance value and the capacitance value of the resistor and the capacitor in the initial reset circuit 65 of the main board 31 are set to be equal to the resistance value and the capacitance value of the resistor and the capacitor externally attached to the reset IC 380 in the other electric component control board. The However, if the CPU on the other electrical component control board starts up and completes the execution of the initialization program before the CPU 56 of the main board 31 completes the execution of the security check program, the capacitor of the other electrical component control board The resistance value and the capacitance of the capacitor may not be equal to the resistance value and the capacitance of the capacitor of the main board 31.

  Therefore, as shown in FIG. 16, the CPU 56 of the main board 31 and the CPUs of the other electrical component control boards are released from reset almost simultaneously. When the reset is released, the CPU 56 first executes a security check program. While the security check program is being executed, commands for other electrical component control boards are not output from the CPU 56. If it takes a sufficient time to execute the security check program, the CPUs of the other electric component control boards complete the execution of the initialization program. Thus, the command is waiting.

  In this embodiment, as shown in FIG. 16, when the execution of the security check program is completed, the reset release timing of the CPU 56 is substantial. Therefore, also in this embodiment, after the game machine is turned on, the timing of reset release of each CPU in each electric component control means is substantially earlier than the timing of reset release of CPU 56 in the game control means. Therefore, there is no situation where a command is sent from the game control means before the execution of the initialization program in each electric component control means is completed, and the respective electric component control means fail to take command data.

  As described above, in each of the above-described embodiments, when the power is turned on, the CPU 56 of the main board 31 is configured to start up later than the CPUs of all other electrical component control means. The possibility that each of the CPUs cannot receive a command from the main board 31 can be eliminated.

  When the power is turned on, the CPU 56 of the main board 31 substantially sets the delay time by other software before the CPU 56 of the main board 31 sends a command to the other electric parts control board. You may make it stand up later than each CPU of a control means.

  Also, at least when the gaming machine is powered off, the timing at which the CPU 56 of the main board 31 is interrupted to indicate that the power is cut off is substantially the same as the timing at which the prize ball control CPU 371 is interrupted to indicate that the power is off. Therefore, the possibility that the command sent immediately before the power is turned off cannot be received on the receiving side is reduced.

  Hereinafter, the power supply stop process in each electrical component control means other than the game control means will be described. Here, the prize ball control means is taken as an example, but the other control means for executing the NMI interrupt processing also performs the same processing. In this embodiment, the NMI interrupt process corresponds to a process at the time of stopping power supply. As shown in FIG. 17, the winning ball control CPU 371 first sets the NMI flag (step S801). Further, the RAM access is disabled (step S802), and the level of the input port into which the output of the power monitoring IC 931 is introduced is continuously monitored (step S803).

  When the input port level returns to the normal level, the winning ball control CPU 371 enables the RAM access (step S804), resets the NMI flag (step S805), and interrupts the NMI. Return to the previous address.

  In this way, when the prize ball control CPU 371 detects that the power supply voltage has returned to normal, it returns the state of the register to the address at which the NMI interrupt occurred. Therefore, the control can be returned to the normal state even when noise is applied to the NMI line.

  However, the input port monitoring process in step S803 may not be performed. In this case, the RAM access is prohibited and then the program is put into a loop state or a HALT (halt) instruction is issued. When the input port monitoring process is not performed, it is not necessary to connect the NMI signal to the input port of the prize ball control CPU 371 in the configuration shown in FIGS.

  FIG. 18 is a flowchart showing an initialization process in the main process executed by the prize ball control CPU 371. In this case, the prize ball control CPU 37 first checks whether or not the NMI flag is set (step S812). If not set, all the registers and the RAM area are cleared (step S814), and necessary initial values are set (step S815). Then, the stack pointer is initialized (step S816), and the initialization process is terminated.

  If it is confirmed in step S812 that the NMI flag is set, the CPU 56 resets the NMI flag (step S813), and jumps to the value of the stack area pointed to by the stack pointer as a jump destination. In this embodiment, it is not necessary to save the general-purpose register values in the backup RAM when the power is turned off, but at least the stack pointer needs to be saved. Since the stack area is formed in the backup RAM area, the winning ball control CPU 371 reliably returns to the control state when the power is turned off by detecting that the NMI flag is set when the power is turned on. Can do.

  For example, if the winning ball flag is formed in the backup RAM area, it is detected that the flag indicating the winning ball is set, and the CPU 371 for controlling the winning ball is immediately stored in the backup RAM area. The prize ball payout process can be resumed based on the value of each counter.

  Even if the flags are not set in the backup RAM area, if the number counter is set in the backup RAM area, the winning ball control CPU 371 performs a game state storage read process when power is restored, that is, It is possible to read the set value of each number counter and detect whether there is an unpaid prize ball. When it is detected that there is an unpaid prize ball, for example, the prize ball payout process can be restarted by setting a prize ball payout flag.

  FIG. 19 is a flowchart showing another example of the NMI interrupt process executed by the prize ball control CPU 371. In this case, the prize ball control CPU 371 first checks whether or not the number of unpaid prize balls or the number of unpaid balls lent is stored (step S821). If there is such a memory, the NMI flag is set (step S822). Further, the RAM access is prohibited (step S823), and the level of the input port into which the output of the power monitoring IC 931 is introduced is continuously monitored (step S803).

  When the input port level returns to the normal level, the winning ball control CPU 371 enables the RAM access (step S804), resets the NMI flag (step S805), and interrupts the NMI. Return to the previous address.

  If there is no storage of the number of unpaid prize balls or the number of unpaid balls, the RAM access is prohibited (step S823), and the process proceeds to step S803. According to such control, preparation for returning to the control state at the time of power recovery is performed only when the power is cut off in the unpaid state, that is, only when necessary.

  In each of the above embodiments, the case where processing based on the NMI interrupt from the power monitoring IC is performed in each electric component control means when the power is cut off is illustrated. However, the power is supplied only to the necessary electric component control board. You may comprise so that monitoring IC may be mounted. In each of the above embodiments, the NMI interrupt is exemplified. However, an interrupt based on the interrupt signal of the INT terminal is introduced by introducing a signal indicating a power supply voltage drop to an external interrupt (INT) terminal that is not maskable. Processing may be performed.

  Similarly to the RAM in the prize ball control means, the RAM in the sound control means, the lamp control means, and the display control means may have a portion that is backed up.

  Further, the game control means and the payout control means perform a predetermined power supply stop process when the power supply is stopped, and the power supply state and the payout control means for causing the game control means to start the power supply stop process. You may be comprised so that it may be the same as the power supply state for starting a process at the time of an electric power supply stop.

  Power supply monitoring means for monitoring a predetermined potential power supply used in the gaming machine and outputting a detection signal when a detection condition is satisfied, and the game control means and the payout control means are configured to generate power according to the detection signal from the power supply monitoring means. You may be comprised so that the process at the time of a supply stop may be performed.

  The game control unit and the payout control unit may be configured to execute a power supply stop process by an interrupt process when a detection signal from the power supply monitoring unit is received.

  The game control board is provided with storage means capable of holding the contents immediately before the power supply is stopped for a predetermined time even when the power supply is cut off by the backup power supply, and the storage means displays the gaming state when the power supply is restored. Information required for restoration may be held.

  The storage means capable of holding the content immediately before the power supply is stopped may be included in the game control means. That is, the storage means may be, for example, a memory (RAM) built in the game control microcomputer.

  The payout control board on which the payout control means is mounted is provided with a storage means capable of holding the contents immediately before the power supply is stopped for a predetermined time even when the power supply is cut off by the backup power supply. It may be configured such that information necessary for restoring the payout state when it is restored is retained.

  The storage means capable of holding the content immediately before the power supply is stopped may be included in the payout control means. That is, the storage means may be, for example, a memory (RAM) built in the payout control microcomputer.

  The game control board and the payout control board are equipped with an initial reset means for outputting a reset signal to the game control means and the payout control means, and a delay is supplied to the game control means by delaying the reset signal from the initial reset means. Means may be provided.

  The game control board and the payout control board are equipped with an initial reset means for outputting a reset signal to the game control means and the payout control means, and the capacitance of the capacitor for creating the reset signal in the initial reset means of the game control board May be configured to be larger than the capacity of the capacitor for creating the reset signal in the initial reset means of the payout control board.

  The game control board and the payout control board are equipped with initial reset means for outputting a reset signal to the game control means and the payout control means, and the game control means executes a predetermined program when the power-on reset is released. Thus, the initial reset means in the game control board and the initial reset means in the payout control board may be configured to have the same configuration.

  When the power supply state for causing the game control means to start the power supply stop process and the power supply state for causing the payout control means to start the power supply stop process are configured to be the same, the power supply By starting the stop process at the same time, the game control means and the payout control means can be simultaneously lowered.

  Power supply monitoring means is provided for monitoring a predetermined potential power supply and outputting a detection signal when a detection condition is satisfied, and the game control means and the payout control means perform processing when the power supply is stopped according to the detection signal from the power supply monitoring means. The payout control means can reliably receive a command from the game control means, and the game control means and the payout control means can supply power such as processing for data storage. It is possible to reliably grasp the timing for performing the processing at the time of stop.

  When the game control means and the payout control means that have received the detection signal of the power supply monitoring means are configured to execute the power supply stop process by the interruption process, the power supply is reliably ensured by the high priority process. Disconnection processing is executed.

  If the storage means on the gaming control board is backed up and is configured to retain information necessary to restore the gaming state when the gaming machine power is restored, the power supply due to unforeseen power outages, etc. Even if the disconnection occurs, the power can be restored to the state when the power is restored, and there is an effect that the player is not disadvantaged.

  When the game control means includes a storage means that can hold the contents immediately before the power supply is stopped, the storage means is integrated with the game control means, thereby reducing the cost of the game control means. be able to.

  When the storage means on the payout control board on which the payout control means is mounted is backed up, and when it is configured to hold information necessary for restoring the payout state when the power of the gaming machine is restored Even if the power is cut off due to an unexpected power failure or the like, it is possible to return to the payout state when the power is turned off when the power is restored, and there is an effect that the player is not disadvantaged.

  In the case where the storage unit capable of holding the contents immediately before the power supply is stopped is included in the payout control unit, the storage unit is integrated with the payout control unit, thereby reducing the cost of the payout control unit. be able to.

  In the case where delay means for delaying a reset signal from the initial reset means and supplying it to the game control means is provided, the initial reset means of the game control board and the initial reset means of the payout control board may have the same configuration. it can.

  When the capacity of the capacitor for creating the reset signal in the initial reset means of the game control board is larger than the capacity of the capacitor for creating the reset signal in the initial reset means of the payout control board, a delay circuit or the like is unnecessary. Therefore, there is an effect that the circuit configuration is simplified.

  The game control means executes a predetermined program when the power-on reset is released, and if the initial reset means on the game control board and the initial reset means on the payout control board have the same configuration, the same design should be performed. Therefore, the design cost is reduced, and as a result, the gaming machine cost is reduced.

It is the front view which looked at the pachinko game machine from the front. It is the front view which looked at the game board of the pachinko machine from the front. It is the rear view which looked at the pachinko game machine from the back. It is a block diagram which shows the circuit structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a display control board. It is a block diagram which shows the circuit structural example of an audio | voice control board. It is a block diagram which shows the circuit structural example of a lamp control board. It is a block diagram which shows the circuit structural example of a prize ball control board. It is a block diagram which shows the structure around CPU in each control board. It is a block diagram which shows one structural example of a power supply board. It is a timing diagram which shows the example of a signal at the time of power-on and power-off. It is a flowchart which shows operation | movement of the basic circuit in a main board | substrate. It is a flowchart which shows the interruption process of CPU of a main board | substrate. It is a flowchart which shows the initialization process in a main process. It is a block diagram which shows the other structure of CPU periphery in each control board. It is a timing diagram which shows the other example of a signal at the time of power-on and power-off. It is a flowchart which shows the NMI process which a prize ball control CPU performs. It is a flowchart which shows the initialization process which a prize ball control CPU performs. It is a flowchart which shows the other example of the NMI process which a prize ball control CPU performs.

Explanation of symbols

1 Pachinko machine 31 Main board 35 Lamp control board 37 Prize ball control board 53 Basic circuit 56 CPU
65 Initial reset circuit 70 Audio control board 80 Display control board 101 Display control CPU
351 CPU for lamp control
371 CPU for prize ball control
701 Voice control CPU
901,931 IC for power monitoring
910 Power supply board 916 Capacitor

Claims (1)

A gaming machine in which a player can play a predetermined game,
A game control microcomputer for controlling the progress of the game;
A payout control microcomputer for performing payout control of game media used in the game based on a command from the game control microcomputer ;
Power monitoring means for monitoring a predetermined potential power source used in a gaming machine and outputting a detection signal when a detection condition is satisfied ;
A non-operation signal output means for outputting a signal for inactivating the game control microcomputer and the payout control microcomputer after a predetermined period of time has elapsed since the power monitoring means output the detection signal ;
The game control microcomputer and the payout control microcomputer are provided with a RAM capable of holding the content immediately before the power supply is stopped for at least a predetermined time by the backup power source even when the power supply is stopped,
The game control microcomputer is:
An initialization process is executed only at the start of power supply, and after executing the initialization process, an update process for updating a first random number counter used for game control is repeatedly executed,
A game control process activated by an internal timer interrupt of the game control microcomputer when the update process is repeatedly executed, which is a counter different from the first random number counter and is advantageous to the player Executing a process of updating a second random number counter for determining whether or not to enter a specific gaming state;
The game control microcomputer and the payout control microcomputer are configured to store, in the RAM, information necessary for restoring a control state within the predetermined period based on a detection signal from the power supply monitoring unit. Processing at the time of supply stop,
The game control microcomputer sets a flag indicating execution of the power supply stop process in the RAM in the power supply stop process.
The game control microcomputer and the payout control microcomputer execute a return process for restoring the control state based on the storage information of the RAM when the power supply is restored,
The game control microcomputer executes the return processing on the condition that the flag is stored in the RAM,
The game control microcomputer does not perform a command transmission process in the power supply stop process.
The payout control microcomputer does not perform a command reception process in the power supply stop process,
By setting the detection condition for outputting the detection signal to the game control microcomputer and the detection condition for outputting the detection signal to the payout control microcomputer as the same detection condition, the power monitoring means A gaming machine that outputs detection signals at the same timing to the game control microcomputer and the payout control microcomputer .

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