JP2001044421A - Ｍｉｓｆｅｔの製造方法 - Google Patents

Ｍｉｓｆｅｔの製造方法

Info

Publication number
JP2001044421A
JP2001044421A JP11211800A JP21180099A JP2001044421A JP 2001044421 A JP2001044421 A JP 2001044421A JP 11211800 A JP11211800 A JP 11211800A JP 21180099 A JP21180099 A JP 21180099A JP 2001044421 A JP2001044421 A JP 2001044421A
Authority
JP
Japan
Prior art keywords
insulating film
gate
dummy gate
interlayer insulating
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11211800A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001044421A5 (https=
Inventor
Yasuyoshi Itou
康悦 伊藤
Yasuaki Inoue
靖朗 井上
Shuichi Oda
秀一 尾田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11211800A priority Critical patent/JP2001044421A/ja
Priority to US09/487,620 priority patent/US6235564B1/en
Publication of JP2001044421A publication Critical patent/JP2001044421A/ja
Publication of JP2001044421A5 publication Critical patent/JP2001044421A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01324—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T or inverted-T
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
    • H10D62/307—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations the doping variations being parallel to the channel lengths
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H10P30/221—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks characterised by the angle between the ion beam and the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
JP11211800A 1999-07-27 1999-07-27 Ｍｉｓｆｅｔの製造方法 Pending JP2001044421A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP11211800A JP2001044421A (ja) 1999-07-27 1999-07-27 Ｍｉｓｆｅｔの製造方法
US09/487,620 US6235564B1 (en) 1999-07-27 2000-01-20 Method of manufacturing MISFET

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11211800A JP2001044421A (ja) 1999-07-27 1999-07-27 Ｍｉｓｆｅｔの製造方法

Publications (2)

Publication Number Publication Date
JP2001044421A true JP2001044421A (ja) 2001-02-16
JP2001044421A5 JP2001044421A5 (https=) 2006-08-24

Family

ID=16611825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11211800A Pending JP2001044421A (ja) 1999-07-27 1999-07-27 Ｍｉｓｆｅｔの製造方法

Country Status (2)

Country Link
US (1) US6235564B1 (https=)
JP (1) JP2001044421A (https=)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008507856A (ja) * 2004-07-28 2008-03-13 インテル コーポレイション 置換金属ゲート形成のための半導体構造の平坦化
WO2008072573A1 (ja) * 2006-12-11 2008-06-19 Sony Corporation 半導体装置の製造方法および半導体装置
JP2008172209A (ja) * 2006-12-11 2008-07-24 Sony Corp 半導体装置の製造方法および半導体装置
KR100935773B1 (ko) * 2007-11-26 2010-01-06 주식회사 동부하이텍 반도체 소자의 제조 방법
WO2011079596A1 (zh) * 2009-12-30 2011-07-07 中国科学院微电子研究所 Mosfet结构及其制作方法
JP2012038821A (ja) * 2010-08-04 2012-02-23 Fujitsu Semiconductor Ltd 半導体装置の製造方法及び半導体装置
JP2019153613A (ja) * 2018-02-28 2019-09-12 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6274421B1 (en) * 1998-01-09 2001-08-14 Sharp Laboratories Of America, Inc. Method of making metal gate sub-micron MOS transistor
WO2005057663A2 (en) * 2003-12-10 2005-06-23 Koninklijke Philips Electronics N.V. Method and apparatus for fabrication of metal-oxide semiconductor integrated circuit devices
DE102007015505B4 (de) * 2007-03-30 2009-01-02 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Halbleiterstruktur
KR20160127891A (ko) * 2015-04-27 2016-11-07 삼성전자주식회사 싸이클 공정을 이용한 수직 패턴의 형성방법
KR102456077B1 (ko) * 2015-06-22 2022-10-19 삼성디스플레이 주식회사 박막 트랜지스터 기판의 제조방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03250741A (ja) 1990-02-28 1991-11-08 Fujitsu Ltd 半導体装置の製造方法
US5227326A (en) * 1991-12-23 1993-07-13 Texas Instruments Incorporated Method for fabricating non-volatile memory cells, arrays of non-volatile memory cells
JPH06342810A (ja) 1993-02-22 1994-12-13 Sumitomo Electric Ind Ltd ショットキ接合型電界効果トランジスタおよびその製造方法
JP3298601B2 (ja) * 1994-09-14 2002-07-02 住友電気工業株式会社 電界効果トランジスタおよびその製造方法
JPH09246543A (ja) 1996-03-07 1997-09-19 Hitachi Ltd 半導体集積回路装置の製造方法
JP4540142B2 (ja) * 1999-01-19 2010-09-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008507856A (ja) * 2004-07-28 2008-03-13 インテル コーポレイション 置換金属ゲート形成のための半導体構造の平坦化
US10868176B2 (en) 2006-12-11 2020-12-15 Sony Corporation Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
JP2008172209A (ja) * 2006-12-11 2008-07-24 Sony Corp 半導体装置の製造方法および半導体装置
US11901454B2 (en) 2006-12-11 2024-02-13 Sony Group Corporation Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
US11404573B2 (en) 2006-12-11 2022-08-02 Sony Group Corporation Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
WO2008072573A1 (ja) * 2006-12-11 2008-06-19 Sony Corporation 半導体装置の製造方法および半導体装置
US8361850B2 (en) 2006-12-11 2013-01-29 Sony Corporation Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
US9673326B2 (en) 2006-12-11 2017-06-06 Sony Corporation Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
US9041058B2 (en) 2006-12-11 2015-05-26 Sony Corporation Metal oxide semiconductor having epitaxial source drain regions and method of manufacturing same using dummy gate process
US9502529B2 (en) 2006-12-11 2016-11-22 Sony Corporation Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
US9419096B2 (en) 2006-12-11 2016-08-16 Sony Corporation Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
US10128374B2 (en) 2006-12-11 2018-11-13 Sony Corporation Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
US9865733B2 (en) 2006-12-11 2018-01-09 Sony Corporation Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
KR100935773B1 (ko) * 2007-11-26 2010-01-06 주식회사 동부하이텍 반도체 소자의 제조 방법
US8658507B2 (en) 2009-12-30 2014-02-25 Institute of Microelectronics, Chinese Academy of Sciences MOSFET structure and method of fabricating the same using replacement channel layer
WO2011079596A1 (zh) * 2009-12-30 2011-07-07 中国科学院微电子研究所 Mosfet结构及其制作方法
JP2012038821A (ja) * 2010-08-04 2012-02-23 Fujitsu Semiconductor Ltd 半導体装置の製造方法及び半導体装置
JP2019153613A (ja) * 2018-02-28 2019-09-12 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP7071841B2 (ja) 2018-02-28 2022-05-19 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2022105184A (ja) * 2018-02-28 2022-07-12 株式会社半導体エネルギー研究所 半導体装置及びその作製方法
JP7372388B2 (ja) 2018-02-28 2023-10-31 株式会社半導体エネルギー研究所 半導体装置及びその作製方法

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